CN104779159A - Method of improving injection performance of hot carriers in N-channel metal oxide semiconductor - Google Patents
Method of improving injection performance of hot carriers in N-channel metal oxide semiconductor Download PDFInfo
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- CN104779159A CN104779159A CN201410010894.2A CN201410010894A CN104779159A CN 104779159 A CN104779159 A CN 104779159A CN 201410010894 A CN201410010894 A CN 201410010894A CN 104779159 A CN104779159 A CN 104779159A
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- ion implantation
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- hot carrier
- low concentration
- oxide layer
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000002347 injection Methods 0.000 title abstract description 12
- 239000007924 injection Substances 0.000 title abstract description 12
- 239000000969 carrier Substances 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a method of improving injection performance of hot carriers in an N-channel metal oxide semiconductor. The traditional lightly-doped injection process is divided into two times of low-concentration lightly-doped injection processes, an electric field of a depletion region is reduced while concentrations at two ends of the depletion region are reduced, saturation current is kept unchanged, hot carrier injection effects are effectively suppressed, performance of a transistor is kept, and the service life of the device is prolonged.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of method improving hot carrier in jection performance in N NMOS N-channel MOS N.
Background technology
The basic structure of N NMOS N-channel MOS N NMOS is in the P-type silicon substrate (providing the hole can moved in a large number) that one piece of doping content is lower, make the N+ district (having in N+ region in a large number for current flowing provides the electron source of free electron) of two high-dopant concentrations, and draw two electrodes with metal (generally using tungsten), make drain D and source S respectively, then the very thin silicon dioxide of one deck (SiO2) insulating barrier is covered at semiconductor surface, the insulating barrier of drain-source interpolar is loaded on an electrode (normally polysilicon), as grid G, substrate is also drawn an electrode B, this just constitutes a N channel enhancement metal-oxide-semiconductor.The source electrode of metal-oxide-semiconductor and substrate are normally connected together, and are insulate between grid and other electrode.
Along with the reduction of chip size, corresponding minimizing is not a lot of for the supply power voltage of chip, operating voltage, so corresponding electric field strength adds, the movement rate that result in electronics increases.When the energy of electronics is sufficiently high time, will leave silicon substrate, tunnelling enters gate oxide, forms hot carrier's effect.Fig. 1 shows the generation of hot carrier and the composition of consequent electric current, I
cHchannel current, I
bBsubstrate current, V
ggrid voltage, I
ggrid current, V
ddrain voltage, V
bunderlayer voltage, V
g<V
d.
The generation of hot carrier's effect is mainly subject to the impact of the electric field strength of horizontal direction, and wherein in the horizontal direction, the maximum place of electric field strength is exactly the place in channel region near drain electrode.A key factor of hot carrier in jection is exactly the depletion region generation avalanche effect between drain electrode and raceway groove, form drain avalanche hot carrier (DAHC) to inject, produce a large amount of electron hole pairs, owing to grid there being certain positive bias, electrons breaks through Si-SiO
2potential barrier on interface, enter gate oxide, cause MOS transistor hydraulic performance decline: first, because hot carrier in jection is to grid oxygen, a part arrives grid, forms gate current, another part is injected in the trapped charge of grid oxygen, this part trapped charge works to the fixed charge item in threshold expression, and accumulates in time, and threshold voltage will produce permanent drift; The second, saturation current can decline; 3rd, due to the increase of substrate current, mutual conductance can reduce; 4th, along with the accumulation of trapped charge, device lifetime will shorten.
In order to solve the harmful effect of hot carrier's effect, most popular device architecture is exactly ldd structure, is called for short LDD.Use LDD structure, depletion region electric field can be reduced, suppress hot carrier injection effect.
At present, normally used LDD ldd structure processing procedure comprises following steps:
Step 1, as shown in Figure 2, P type dopant well (P type substrate) 101 prepares grid structure, the polysilicon gate 103 that this grid structure comprises gate oxide 102 and is arranged on gate oxide;
Step 2, as shown in Figure 3, carry out the ion implantation of single low concentration, in P type substrate 101, form lightly doped drain region 104 and light dope source region 105;
The NMOS energy range of 3.3V and dosage range are very wide, but for 130nm processing procedure, alloy is phosphorus, and energy is below 50K, and dose concentration is 4 × 10
13;
Step 3, as shown in Figure 4, around grid structure, form sidewall structure, this sidewall structure comprises three-decker, is respectively the first silicon oxide layer 106, silicon nitride layer 107 and the second silicon oxide layer 108 from the inside to the outside;
Step 4, as shown in Figure 5, sidewall structure to be etched, remove whole second silicon oxide layer 108, remove part first silicon oxide layer 106 and silicon nitride layer 107, form side wall in grid both sides;
Step 5, as shown in Figure 6, carry out the ion implantation of high concentration, in P type substrate 101, form territory, heavily doped drain region 109 and heavy doping source region 110.
For the N-channel metal-oxide-semiconductor of 3.3V, because the voltage of this device is higher, even if having employed above-mentioned LDD ldd structure processing procedure, neither be fairly obvious to the suppression of hot carrier injection effect, the life-span of device will shorten.
Summary of the invention
A kind of method improving hot carrier in jection performance in N NMOS N-channel MOS N provided by the invention, effectively inhibits hot carrier injection effect, maintains transistor performance, extend device lifetime.
In order to achieve the above object, the invention provides a kind of method improving hot carrier in jection performance in N NMOS N-channel MOS N, the method is for 3.3VN channel metal-oxide-semiconductor, and the method includes the steps of:
Step 1, on P type dopant well, prepare grid structure, this grid structure comprises gate oxide and is arranged on the polysilicon gate on gate oxide;
Step 2, carry out first time low concentration ion implantation, in P type substrate, form lightly doped drain region and light dope source region;
Step 3, around grid structure, form sidewall structure, this sidewall structure comprises three-decker, is respectively the first silicon oxide layer, silicon nitride layer and the second silicon oxide layer from the inside to the outside;
Step 4, carry out second time low concentration ion implantation, in P type substrate, form lightly doped drain region and light dope source region;
Step 5, sidewall structure to be etched, remove whole second silicon oxide layer, remove part first silicon oxide layer and silicon nitride layer, form side wall in grid both sides;
Step 6, carry out the ion implantation of high concentration, in P type substrate, form territory, heavily doped drain region and heavy doping source region.
Described first time, the energy of ion implantation of low concentration was below 50K, and dose concentration is 2 × 10
13~ 3 × 10
13.
The energy of the ion implantation of described second time low concentration is below 50K, and dose concentration is 3.8 × 10
13~ 3.9 × 10
13.
The present invention is in the concentration by reducing two ends, depletion region thus while reducing depletion region electric field, maintenance saturation current is constant, effectively inhibits hot carrier injection effect, maintains transistor performance, extend device lifetime.
Accompanying drawing explanation
Fig. 1 is the schematic diagram producing hot carrier's effect in background technology.
Fig. 2 ~ Fig. 6 is the flowage structure schematic diagram manufacturing lightly doped drain in background technology.
Fig. 7 ~ Figure 12 is a kind of flowage structure schematic diagram improving the method for hot carrier in jection performance in N NMOS N-channel MOS N provided by the invention.
Figure 13 is the substrate current Data Comparison figure of the device in the present invention and background technology.
Figure 14 is the drain current annealing time figure of the device in the present invention and background technology.
Figure 15 is that the life span comparison of device in the present invention and background technology schemes.
Embodiment
Illustrate preferred embodiment of the present invention according to Fig. 7 ~ Figure 15 below.
The invention provides a kind of method improving hot carrier in jection performance in N NMOS N-channel MOS N, the method is for 3.3VN channel metal-oxide-semiconductor, and the method includes the steps of:
Step 1, as shown in Figure 7, P type dopant well (P type substrate) 101 prepares grid structure, the polysilicon gate 103 that this grid structure comprises gate oxide 102 and is arranged on gate oxide;
Step 2, as shown in Figure 8, carries out the ion implantation of first time low concentration, formation lightly doped drain region 104 and light dope source region 105 P type substrate 101 in;
This, energy of ion implantation of low concentration was the same with the energy of the ion implantation of single low concentration in background technology first time, and dosage is approximately the half of the dosage of the ion implantation of single low concentration in background technology;
That is, energy is below 50K, and dose concentration is 2 × 10
13~ 3 × 10
13;
Step 3, as shown in Figure 9, around grid structure, form sidewall structure, this sidewall structure comprises three-decker, is respectively the first silicon oxide layer 106, silicon nitride layer 107 and the second silicon oxide layer 108 from the inside to the outside;
Step 4, as shown in Figure 10, carries out the ion implantation of second time low concentration, P type substrate 101 in, form lightly doped drain region 104 ' and light dope source region 105 ';
The energy of the ion implantation of this second time low concentration is the same with the energy of the ion implantation of single low concentration in background technology, and dosage is a little less than the dosage of the ion implantation of single low concentration in background technology;
That is, energy is below 50K, and dose concentration is 3.8 × 10
13~ 3.9 × 10
13.
Step 5, as shown in figure 11, sidewall structure to be etched, remove whole second silicon oxide layer 108, remove part first silicon oxide layer 106 and silicon nitride layer 107, form side wall in grid both sides;
Step 6, as shown in figure 12, carry out the ion implantation of high concentration, in P type substrate 101, form territory, heavily doped drain region 109 and heavy doping source region 110.
Light dope injection process in background technology is divided into the light dope injection process of twice low concentration by the present invention, by reduce two ends, depletion region concentration thus while reducing depletion region electric field, keep saturation current constant, effectively inhibit hot carrier injection effect, maintain transistor performance, extend device lifetime.
Table 1
| Unit | Background technology | The present invention | |
| Vt | V | 0.668 | 0.694 |
| I ds | μA/μm | 603.83 | 601.01 |
| I off | pA/μm | 1.117 | 0.508 |
| I b | μA/μm | 0.939 | 0.855 |
Table 1 is the Performance comparision of the lightly doped drain nmos device adopting method of the present invention and adopt the method in background technology to be formed, Vt is cut-in voltage (threshold voltage), Ids is saturation current, Ioff is cut-off current, I b is substrate current, can find out, the performance of the lightly doped drain nmos device adopting method of the present invention to be formed is improved.
As shown in figure 13, the substrate current Data Comparison figure of the device in the present invention and background technology, the reflection of substrate hole current Ib side enters the electronic current of grid, this value is larger, hot carrier in jection performance is poorer, as seen from the figure, device substrate electric current of the present invention is less than the device substrate electric current in background technology.
As shown in figure 14, the drain current annealing time figure of the device in the present invention and background technology, drain current Id degenerates to the life-span that time corresponding to a certain size (normally diminishing 10%) just represents hot carrier in jection, so drain current degeneration is more slow better, as seen from Figure 14, adopt device prepared by method of the present invention, the speed that drain current is degenerated is slower.
As shown in figure 15, be that the life span comparison of the device in the present invention and background technology schemes, as seen from the figure, ordinate is normalization carrier lifetime, in background technology, the life-span mean value of device is 100%, adopts device prepared by method of the present invention, and its life-span is obviously longer.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (3)
1. improve a method for hot carrier in jection performance in N NMOS N-channel MOS N, the method, for 3.3VN channel metal-oxide-semiconductor, is characterized in that, the method includes the steps of:
Step 1, on P type dopant well (101), prepare grid structure, this grid structure comprises gate oxide (102) and is arranged on the polysilicon gate (103) on gate oxide;
Step 2, carry out first time low concentration ion implantation, P type substrate (101) in formation lightly doped drain region (104) and light dope source region (105);
Step 3, around grid structure, form sidewall structure, this sidewall structure comprises three-decker, is respectively the first silicon oxide layer (106), silicon nitride layer (107) and the second silicon oxide layer (108) from the inside to the outside;
Step 4, the ion implantation of second time low concentration of carrying out, formation lightly doped drain region (104 ') and light dope source region (105 ') P type substrate (101) in;
Step 5, sidewall structure to be etched, remove whole second silicon oxide layer (108), remove part first silicon oxide layer (106) and silicon nitride layer (107), form side wall in grid both sides;
Step 6, carry out the ion implantation of high concentration, in P type substrate (101), form territory, heavily doped drain region (109) and heavy doping source region (110).
2. the as claimed in claim 1 method improving hot carrier in jection performance in N NMOS N-channel MOS N, is characterized in that, described first time the energy of ion implantation of low concentration be below 50K, dose concentration is 2 × 10
13~ 3 × 10
13.
3. the method improving hot carrier in jection performance in N NMOS N-channel MOS N as claimed in claim 1, it is characterized in that, the energy of the ion implantation of described second time low concentration is below 50K, and dose concentration is 3.8 × 10
13~ 3.9 × 10
13.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410010894.2A CN104779159A (en) | 2014-01-10 | 2014-01-10 | Method of improving injection performance of hot carriers in N-channel metal oxide semiconductor |
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|---|---|---|---|
| CN201410010894.2A CN104779159A (en) | 2014-01-10 | 2014-01-10 | Method of improving injection performance of hot carriers in N-channel metal oxide semiconductor |
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| CN104779159A true CN104779159A (en) | 2015-07-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911282A (en) * | 2018-09-18 | 2020-03-24 | 无锡华润微电子有限公司 | Method for manufacturing N-channel semiconductor component and N-channel semiconductor component |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6479350B1 (en) * | 1999-08-18 | 2002-11-12 | Advanced Micro Devices, Inc. | Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers |
| US6504218B1 (en) * | 1996-09-03 | 2003-01-07 | Advanced Micro Devices, Inc. | Asymmetrical N-channel and P-channel devices |
| KR20060100779A (en) * | 2005-03-18 | 2006-09-21 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having multiple ldd regions |
-
2014
- 2014-01-10 CN CN201410010894.2A patent/CN104779159A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6504218B1 (en) * | 1996-09-03 | 2003-01-07 | Advanced Micro Devices, Inc. | Asymmetrical N-channel and P-channel devices |
| US6479350B1 (en) * | 1999-08-18 | 2002-11-12 | Advanced Micro Devices, Inc. | Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers |
| KR20060100779A (en) * | 2005-03-18 | 2006-09-21 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having multiple ldd regions |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911282A (en) * | 2018-09-18 | 2020-03-24 | 无锡华润微电子有限公司 | Method for manufacturing N-channel semiconductor component and N-channel semiconductor component |
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