CN104754830A - Light dimming circuit - Google Patents
Light dimming circuit Download PDFInfo
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- CN104754830A CN104754830A CN201510135622.XA CN201510135622A CN104754830A CN 104754830 A CN104754830 A CN 104754830A CN 201510135622 A CN201510135622 A CN 201510135622A CN 104754830 A CN104754830 A CN 104754830A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention relates to a light dimming circuit. The light dimming circuit comprises a first high-frequency oscillator for generating a first clock signal, a counter for counting high level time and low level time in an inputted DPWM signal according to a first clock signal generated by a first high frequency oscillator as well as respectively generating high level time number and low level time number, and a second high frequency oscillating circuit for generating second clock signal with the same duty ratio with the DPWM signal according to the high level time number and the low level time number. According to the light dimming circuit, a small-frequency light dimming signal can be utilized to generate high-frequency light dimming voltage, so that the design difficulty of a filter circuit can be reduced, the outputted light dimming voltage can be stable and difficult to fluctuate, the space for a chip of the filter circuit can be reduced, the pressure on the line layout design, radiating and cost can be relieved.
Description
Technical field
The application relates to LED backlight drive technical field, particularly relates to a kind of light adjusting circuit.
Background technology
At LED(Light Emitting Diode, light-emitting diode) light adjusting circuit in backlight drive circuit has two kinds of modes usually, and a kind of is simulation dimming mode, and one is the dimming mode of pulse-width modulation (Pulse WidthModulation, PWM).
PWM dimming mode has the advantages such as high light modulation precision, colourless spectral migration because of it and is widely adopted, but, be but restricted in some applications.First, because the feedback control loop response speed of LED backlight drive circuit is comparatively slow, if light modulating frequency is higher than 500Hz, be then difficult to accomplish the good linearity, because LED electric current rising and falling time will occupy larger duty ratio.Secondly, light modulating frequency is in 3K ~ 50KHz(people ear sensitive frequency scope) between easily produce electric capacity howling, cause audio-frequency noise, this is caused by capacitor charge and discharge.Again, in some tight systems, due to printed circuit board (PCB) (PrintedCircuitBoard, PCB) area is less, cause power supply, grounding wire impedance higher, comparatively low frequency (as below 500Hz) PWM dimming mode can cause power supply produces the power supply noise consistent with light modulating frequency, thus causes some sensitive circuit operational failures.
Existing a kind of common dimming mode is combined with simulation light modulation by the dimming mode of digital pulse width modulation, namely by the dim signal (DPWM) of input numeral, produce a dimmer voltage VDIM, its amplitude is directly proportional (such as: VDIM=VREF.D to the duty ratio of input dim signal, wherein D is the duty ratio of dim signal, VREF is internal reference voltage, such as 0.3V), then with the magnitude of voltage of current feedback signal in this dimmer voltage VDIM control LED drive circuit, current feedback signal is generally connected with LED by a feedback resistance, the magnitude of voltage of current feedback signal is the voltage drop on this feedback resistance, voltage drop on feedback resistance is adjusted to and equals dimmer voltage VDIM by current feedback loop, i.e. ILED.Rs=VDIM=VREF.D, wherein Rs is the resistance value of feedback resistance, ILED is the electric current of LED.Such LED electric current is just directly proportional to the duty ratio D of dim signal, namely achieves dimming effect.
Fig. 1 is the circuit theory diagrams of a kind of light adjusting circuit of prior art, describes the specific implementation being produced dimmer voltage VDIM by dim signal DPWM.Wherein DPWM is the digital dimming signal of outside input, and REF is reference voltage, such as 0.3V, and consequent VDIM average voltage equals VREF.D, and wherein VREF is the magnitude of voltage of REF.The filter circuit utilizing resistance R01, resistance R02, electric capacity C01 and electric capacity C02 to form carries out filtering to DPWM signal and obtains VDIM.Work as R01, when the value of C01, R02, C02 is enough large, VDIM signal will be filtered into an approximate direct voltage.
In order to make the DPWM dim signal of lower frequency, can the less VDIM signal of output pulsation after filtering, the filter circuit in light adjusting circuit needs the R1 of larger resistance value, the C1 of R2 and larger capacitance, C2.Such as, R1=R2=7.5M Ω, C1=C2=12.5pF.Now, frequency can be similar to higher than the dim signal of 10/ (2. π .R1.C1) and filter into the less dimmer voltage signal of fluctuation by filter circuit, and this frequency is about 16.98K hertz.And when PCB design, need to consider the impact of the volume of each element on configuration.1pF electric capacity about needs the chip area of 30X30 square micron, C1 and C2 about needs the area of 150X150 square micron, R1 and R2 also needs the area of about 80X80 square micron.The area that those elements take is quite large, is unfavorable for the design of configuration, and easily all causes larger pressure to heat radiation, cost.
Summary of the invention
The object of the application is to provide a kind of light adjusting circuit, the dim signal of lower frequency can be utilized, produce the dimmer voltage VDIM of upper frequency, reduce the design difficulty of filter circuit, the dimmer voltage exported is made to stablize, not easily fluctuate, and reduce the chip area footprints of filter circuit, alleviate configuration design, heat radiation and the pressure of cost.
For achieving the above object, this application provides a kind of light adjusting circuit, described light adjusting circuit comprises: the first high-frequency generator, counter and the second high-frequency generator;
First high-frequency generator, for generation of the first clock signal;
Counter, is connected with described first high-frequency generator, for counting the high level time in the digital pulse width DPWM signal of input and low level time according to described first clock signal, produces high level time number and low level time number respectively;
Second high-frequency generator, is connected with described counter, for according to described high level time number and low level time number, produces the second clock signal identical with the duty ratio of described DPWM signal.
The light adjusting circuit that the application provides, pass through high-frequency generator, the DPWM dim signal of lower frequency is modulated into the periodic signal of upper frequency, circuit produces dimmer voltage VDIM after filtering again, can avoid easily producing when inputting the DPWM dim signal of upper frequency the problems such as audio-frequency noise, the linearity be bad, make the filter circuit in light adjusting circuit that less resistance and electric capacity can be used to carry out filtering simultaneously, reduce the design difficulty of filter circuit, thus reduction chip area footprints, alleviate configuration design, heat radiation and the pressure of cost.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing a kind of light adjusting circuit;
The theory diagram of a kind of light adjusting circuit that Fig. 2 provides for the embodiment of the present application;
The circuit theory diagrams of the first high-frequency generator that Fig. 3 provides for the embodiment of the present application;
The circuit theory diagrams of the second high-frequency generator that Fig. 4 provides for the embodiment of the present application;
The structure principle chart of the current mirror group that Fig. 5 provides for the embodiment of the present application;
The waveform schematic diagram of each signal in the light adjusting circuit that Fig. 6 provides for the embodiment of the present application;
The circuit theory diagrams of the filter circuit that Fig. 7 provides for the embodiment of the present application;
The circuit theory diagrams of another kind second high-frequency generator that Fig. 8 provides for the embodiment of the present application;
The waveform schematic diagram of each signal in the another kind of light adjusting circuit that Fig. 9 provides for the embodiment of the present application.
Embodiment
Below by drawings and Examples, the technical scheme of the application is described in further detail.
The light adjusting circuit of the application is that the mode adopting digital pulse width modulation to combine with simulation light modulation carries out light modulation, its operation principle is modulated the digital dimming DPWM signal that outside inputs by high-frequency generator, make the periodic signal of a generation upper frequency, the duty ratio of this periodic signal is approximately equal to the duty ratio of DPWM signal, circuit after filtering again, produces dimmer voltage VDIM and exports.The application, by improving light modulating frequency, makes filter circuit that less resistance and electric capacity can be adopted to carry out filtering, thus reduces chip area footprints, alleviates configuration design, heat radiation and the pressure of cost.
Fig. 2 is the schematic diagram of the light adjusting circuit that the present embodiment provides, and as shown in Fig. 2, the light adjusting circuit of the application comprises: the first high-frequency generator 10, counter 20, second high-frequency generator 30 and filter 40.
First high-frequency generator 10 is for generation of the first clock signal C K1 of high frequency.First high-frequency generator 10 is connected with counter 20, provides the sampled signal of the first clock signal C K1 as counter 20 of high frequency.
Fig. 3 is a kind of schematic diagram of the first high-frequency generator 10, as shown in Fig. 3, this first high-frequency generator 10 is ring oscillators, odd number inverter INV1, INV2, INV3 is adopted to connect successively, and output and input end to end, form ring-type, i.e. the first clock signal frequency CK1 of exportable high frequency.
Certainly, first high-frequency generator 10 can adopt other existing high-frequency generators to realize, as long as frequency is higher, less to the error of time counting generation like this, the frequency of the first clock signal frequency CK1 produced is higher, less by counter 20 counting error, maximum time error equal the cycle of CK1.The frequency of the first clock signal frequency CK1 is higher, resistance required in general filter 40 and capacitance less, chip area is less.
Counter 20 is connected with the first high-frequency generator, counts, produce high level time number and low level time number respectively for the high level time in the DPWM signal that inputs outside according to the first clock signal C K1 and low level time.
In this process, counter 20 utilizes the high and low level of the first clock signal C K1 to DPWM signal to sample, and calculates the periodicity of high level time and low level time respectively.In the one-period of DPWM signal, when DPWM signal is in high level state, with the first clock signal C K1, high level time is counted, produce binary data HD1 ~ HDN; When being in low level state, with the first clock signal C K1, low level time being counted, producing binary data LD1 ~ LDN.Because the frequency of the first clock signal C K1 is higher, such as, it can be 100 times of DPWM signal frequency, be so in the one-period of DPWM signal of 3:2 in duty ratio, 60 the first clock signal C K1 cycles are comprised in high level time, then can obtain high level time number is 60, and obtaining binary data HD1 ~ HDN is 00111100.Comprise 40 the first clock signal C K1 cycles in low level time, then can obtain low level time number is 40, and obtaining binary data LD1 ~ LDN is 00101000.In theory, the frequency of the first clock signal C K1 is at least greater than the sample frequency of DPWM signal.
When DPWM signal dutyfactor is constant, the binary data HD1 ~ HDN obtained and binary data LD1 ~ LDN is also constant, is fixing high level time number and low level time number.
Second high-frequency generator 30, for according to described high level time number and low level time number, produces the second clock signal of the high frequency identical with the duty ratio of DPWM signal.
Fig. 4 is the schematic diagram of the present embodiment second high-frequency generator 30, as shown in Fig. 4, the second high-frequency generator 30 comprises the first current mirror group IH, the second current mirror group IL, the first electric capacity C1, the second electric capacity C2, the first comparator COMP1, the second comparator COMP2, the first discharge switch MN1, the second discharge switch MN2 first NOR gate NOR1 and the second NOR gate NOR2.
Binary data HD1 ~ HDN that first current mirror group IH exports with counter 20 is connected, and utilizes binary data HD1 ~ HDN to control the output current of this first current mirror group IH, provides the first charging current.The output of the first current mirror group IH is connected with the first electric capacity C1, utilizes described first charging current to charge to the first electric capacity C1.
Second current mirror group IL is connected with binary data HL1 ~ HLN, utilizes binary data HL1 ~ HLN to control the output current of this second current mirror group IL, provides the second charging current.The output of the second current mirror group IL is connected with the second electric capacity C2, utilizes described second charging current to charge to the second electric capacity C2.
The first input end of the first comparator COMP1 is connected with the first electric capacity C1, and the second input is connected with electric capacity reference voltage, and output is connected with the input of the first NOR gate NOR1.
The first input end of the second comparator COMP2 is connected with the second electric capacity C2, and the second input is connected with electric capacity reference voltage, and output is connected with the input of the second NOR gate NOR2.
First discharge switch MN1 is connected to the both sides of the first electric capacity C1, and its controlled end is connected with the output of the second NOR gate NOR2, and when the first discharge switch MN1 conducting, the first electric capacity C1 discharges, and voltage reduces to low level.
Second discharge switch MN2 is connected to the both sides of the second electric capacity C2, and its controlled end is connected with the output of the first NOR gate NOR1, and when the second discharge switch MN2 conducting, the second electric capacity C2 discharges, and voltage reduces to low level.
First discharge switch MN1 and the second discharge switch MN2 can be the electronic switches such as transistor, field effect transistor, controllable silicon.
The first input end of the first NOR gate NOR1 is connected with the output of the first comparator COMP1, and the second input is connected with the output of the second NOR gate NOR2, and output is connected with the input of the second NOR gate NOR2.
The first input end of the second NOR gate NOR2 is connected with the output of the second comparator COMP2, and output is connected with second input of the first NOR gate NOR1, and as the output of the second high-frequency generator 30, exports second clock signal CK2.
As shown in Fig. 5, first current mirror group IH comprises N Mirroring of tributary current source IH1 ~ IHN, the ratio of the reference current IH0 of its electric current and this first current mirror group IH is binary scale, i.e. IH1=IH0, and IH1:IH2:IH3: ...: IHN=1:2:4: ... 2N-1.Second current mirror group IL comprises N Mirroring of tributary current source IL1 ~ ILN, and the ratio of the reference current IL0 of its electric current and this second current mirror group IL is binary scale, i.e. IL1=IL0, and IL1:IL2:IL3: ...: ILN=1:2:4: ...: 2N-1.VDD is supply voltage.
Binary data HD1 ~ HDN controls each mirror current source IH1 ~ IN respectively by K11 ~ K1N, the output of the first current mirror group IH is connected with the first electric capacity C1, the current value IH=HD1.20.IH0+HD2.21.IH0+ exported ... + HDN.2N-1.IH0, wherein the value of HD1 ~ HDN is 0 or 1.That is, the charging current of the first electric capacity C1 is the reference current of the multiple of high level time number.
Binary data HL1 ~ HLN controls each mirror current source IL1 ~ ILN respectively by K21 ~ K2N, the output of the second current mirror group IL is connected with the second electric capacity C2, the current value L=HD1.20.IL0+HD2.21.IL0+ exported ... + HDN.2N-1.IL0, wherein the value of HD1 ~ HDN is 0 or 1.That is, the charging current of the first electric capacity C2 is the reference current of the multiple of low level time number.
The operation principle of the second oscillator 30 is specially: time initial, voltage on first electric capacity C1 and the second electric capacity C2 is zero (i.e. VC1=VC2=0), first current mirror group IH charges to the first electric capacity C1, when the voltage of node VC1 is greater than electric capacity reference voltage VTH, first comparator COMP1 exports high level, first NOR gate NOR1 exports and becomes low level, namely the grid of the second discharge switch MN2 becomes low level, second discharge switch MN2 is turned off, the second current mirror group IL is allowed to charge to the second electric capacity C2, now two inputs of the second NOR gate NOR2 are all low level, the output of the second NOR gate NOR2 is high level, namely exporting second clock signal CK2 is high level.When node VC2 voltage is greater than electric capacity reference voltage VTH, second comparator COMP2 exports high level, the output of the second NOR gate NOR2 is set to low level, namely the grid of the first discharge switch MN1 becomes low level, first discharge switch MN1 is turned off, allow the first current mirror group IH to charge to the first electric capacity C1, now exporting second clock signal CK2 is low level.When node VC1 be charged to VC1 node voltage be greater than electric capacity reference voltage VTH time, first comparator COMP1 exports high level, first NOR gate NOR1 exports and becomes low level, namely the grid of the second discharge switch MN2 becomes low level, second discharge switch MN2 is turned off, allow the second current mirror group IL to charge to the second electric capacity C2, exporting second clock signal CK2 is high level.Like this, go round and begin again, just define vibration, this creates the terminal periodic second clock signal CK2.Concrete waveform is as shown in Fig. 6.
Wherein, high level time TH=(VTH.C1)/(HD.IH), VTH is the magnitude of voltage of electric capacity reference voltage VTH, C1 is the capacitance of the first electric capacity C1, HD=HD1.20+HD2.21+ ... + HDN.2N-1, HD1 ~ HDN is the binary numeral of signal HD1 ~ HDN, is 0 or 1.
Low level time TL=(VTH.C2)/(LD.IL), VTH is the magnitude of voltage of electric capacity reference voltage VTH, C2 is the capacitance of the second electric capacity C2, LD=LD1.20+LD2.21+ ... + LDN.2N-1, LD1 ~ LDN is the binary numeral of signal LD1 ~ LDN, is 0 or 1.
Duty ratio D_CK2=TL/ (the TL+TH)=HD/ (HD+LD) of second clock signal CK2, and according to counter principle, the high level time T1=T_CK1.HD of DPWM signal, low level time T2=T_CK1.LD, so the duty ratio D_PWM=T1/ of DPWM signal (T1+T2)=HD/ (HD+LD), so D_CK2=D_PWM.And frequency F_CK2=1/ (the TH+TL)=IH1/ of second clock signal CK2 (VTH.C1. (1/HD+1/LD)).In order to the frequency of satisfied design second oscillator is higher, can design very little by the first electric capacity C1 during design, such F_CK2 is very large, and chip area is also very little simultaneously.
Filter 40 for carrying out filtering to second clock signal CK2, and using dimmer voltage VDIM that the voltage exported after filtering exports as light adjusting circuit.
Fig. 7 is the schematic diagram of a kind of filter 40 that the present embodiment provides, as shown in Fig. 7, this filter 40 is second-order low-pass filter, comprise resistance R1, electric capacity C3, resistance R2 and electric capacity C4 and form filter, reference voltage REF is connected with resistance R1 via K switch 1, the second high-frequency signal CK2 control switch K1 and by not gate INV1 control switch K2.Second high-frequency signal CK2 is device 40 rear output dimmer voltage VDIM after filtering.
When the second high-frequency signal CK2 is the periodic signal of upper frequency, required resistance R1, electric capacity C3, resistance R2, the resistance value of electric capacity C4 and capacitance can be very little.Higher than the frequency of dim signal DPWM 100 times for the periodic signal frequency of the second high-frequency signal CK2, required resistance value and capacitance can reduce 10 times respectively.
With in prior art, if resistance R1=R2=7.5M is Ω, frequency can be similar to higher than the dim signal of 10/ (2. π .R1.C1) and filter into the less dimmer voltage signal of fluctuation by the filter of C3=C4=12.5pF, and it is conspicuous that this frequency is about 16.98K
Hereby.And in this application, because the frequency of filter input end is higher, its resistance R1 and R2 can get 0.75M ohm, electric capacity C3 and C4 can get 1.25pF.The area of such element can be reduced to 1/10th of prior art, in actual design, the scheme of comparative optimization preferably reduces the larger part of area, such as electric capacity area occupied ratio resistance is large, electric capacity can be allowed to reduce larger multiple, and such as 20 times, resistance reduces 5 times, its product still maintains reduction 100 times, then area is reduced to:
(150X150/20+80X80/5)/(150X150+80X80)=8.3%
As can be seen here, the application can effectively reduce the resistance of filter circuit and the value of electric capacity, thus reduces chip area footprints, reduces the design difficulty of filter circuit, alleviates the pressure of configuration design.
Fig. 8 is the circuit theory diagrams of another the second high-frequency generator 30 that the embodiment of the present application provides, as shown in Figure 8, this second high-frequency generator 30 comprises: the first current mirror group IH, the second current mirror group IL, electric capacity C, comparator COMP, discharge switch MN, the first control switch KH, the second control switch KL, trigger DFF and delay unit DT.
Identical with in second current mirror group IL and Fig. 4 of first current mirror group IH, is respectively used to provide the first charging current and the second charging current, and is connected with electric capacity C respectively by the first control switch KH, the second control switch KL.The controlled end of the first control switch KH and the D of trigger DFF hold to hold with Q and are connected, the controlled end of the second control switch KL is held with the Q of trigger DFF and is connected, the Q end of trigger DFF, as the output of the second high-frequency generator 30, exports second clock signal CK2.
The first input end of comparator COMP is connected with electric capacity C, and the second input is connected with electric capacity reference voltage, and the output of comparator COMP is connected with the input end of clock of trigger DFF.
Discharge switch MN is connected to the both sides of electric capacity C, and the output of comparator COMP is connected with the controlled end of discharge switch MN through delay unit DT, and during discharge switch MN conducting, electric capacity C discharges, and voltage reduces to low level.
During the charging of electric capacity C odd-times, with the first current mirror group IH for charging current for charging, even-times is charged with the second current mirror group IL for charging current for charging, when the voltage being at every turn charged to node VC is greater than electric capacity reference voltage VTH, discharge switch MN conducting, make electric capacity C discharge into zero, trigger DFF produces periodic signal control switch KH and KL respectively.The reset terminal of trigger DFF can meet power-on reset signal UV, and as shown in Figure 9, VDD is supply voltage to waveform, when powering on, produces UV signal at every turn, resets to sequential logic, also can earth level, never resets.
The application compared with prior art, although add some circuit, such as the first high-frequency generator, second high-frequency generator sum counter, but these circuit take very little chip area, the integrated circuit technology that special use is more advanced, along with minimum processing line reductions is little, most devices can reduce along with square multiple.Such as contrast 0.5um technique and 0.18um technique, in 0.18um technique, the area of counter can be reduced to (0.18/0.5) 2=0.13, is namely reduced to 13%.
The light adjusting circuit that the application provides, pass through high-frequency generator, the DPWM dim signal of lower frequency is modulated into the periodic signal of upper frequency, circuit produces dimmer voltage VDIM after filtering again, can avoid easily producing when inputting the DPWM dim signal of upper frequency the problems such as audio-frequency noise, the linearity be bad, make the filter circuit in light adjusting circuit that less resistance and electric capacity can be used to carry out filtering simultaneously, reduce the design difficulty of filter circuit, thus reduction chip area footprints, alleviate configuration design, heat radiation and the pressure of cost.
Claims (10)
1. a light adjusting circuit, is characterized in that, described light adjusting circuit comprises: the first high-frequency generator, counter and the second high-frequency generator;
First high-frequency generator, for generation of the first clock signal;
Counter, is connected with described first high-frequency generator, for counting the high level time in the digital pulse width DPWM signal of input and low level time according to described first clock signal, produces high level time number and low level time number respectively;
Second high-frequency generator, is connected with described counter, for according to described high level time number and low level time number, produces the second clock signal identical with the duty ratio of described DPWM signal.
2. light adjusting circuit according to claim 1, is characterized in that, the frequency of described first clock signal and second clock signal is higher than the frequency of described DPWM signal.
3. light adjusting circuit according to claim 1, it is characterized in that, described second high-frequency oscillating circuits comprises the first current mirror group, the second current mirror group, the first electric capacity, the first comparator, the second electric capacity, the second comparator, the first discharge switch, the second discharge switch, the first NOR gate and the second NOR gate;
First current mirror group, is connected with described first electric capacity, for producing the first charging current based on described high level time number and reference current, and utilizes described first charging current to charge to described first electric capacity;
Second current mirror group, is connected with described second electric capacity, for producing the second charging current based on described low level time number and reference current, and utilizes described second charging current to charge to described second electric capacity;
First comparator, is connected with described first electric capacity, for the voltage of more described first electric capacity and the size of electric capacity reference voltage, outputs signal when the voltage of described first electric capacity is greater than described electric capacity reference voltage;
Second comparator, is connected with described second electric capacity, for the voltage of more described second electric capacity and the size of electric capacity reference voltage, outputs signal when the voltage of described first electric capacity is greater than described electric capacity reference voltage;
First discharge switch, is connected to the both sides of described first electric capacity, and the controlled end of described first discharge switch is connected with the output of described second NOR gate;
Second discharge switch, is connected to the both sides of described second electric capacity, and the controlled end of described second discharge switch is connected with the output of described first NOR gate;
First NOR gate, the first input end of described first NOR gate is connected with the output of described first comparator, second input of described first NOR gate is connected with the output of described second NOR gate, and the output of described first NOR gate is connected with the second input of described second NOR gate;
Second NOR gate, the first input end of described second NOR gate is connected with the output of described second comparator, the output of described second NOR gate is connected with the second input of described first NOR gate, and as the output of described second high-frequency generator, export described second clock signal.
4. light adjusting circuit according to claim 1, it is characterized in that, described second high-frequency oscillating circuits comprises the first current mirror group, the second current mirror group, electric capacity, comparator, trigger, the first control switch, the second control switch, delay unit and discharge switch;
First current mirror group, is connected with described electric capacity, for producing the first charging current based on described high level time number and reference current, and utilizes described first charging current to charge to described electric capacity;
Second current mirror group, is connected with described electric capacity, for producing the second charging current based on low level time number and reference current, and utilizes described second charging current to charge to described electric capacity;
Comparator, the first input end of described comparator is connected with described electric capacity, second input of described comparator is connected with described electric capacity reference voltage, the output of described comparator is connected through the controlled end of described delay unit with described discharge switch, for the voltage of more described electric capacity and the size of electric capacity reference voltage, when the voltage of described electric capacity is greater than described electric capacity reference voltage, output signal to described discharge switch;
The input end of clock of described trigger is connected with the output of described comparator;
Described discharge switch is connected to the both sides of described electric capacity, and controlled end conducting when receiving the signal that described comparator exports of described discharge switch, makes described capacitor discharge;
Described first current mirror group is connected with described electric capacity by described first control switch, and the controlled end of described first control switch and the D of described trigger hold to hold with Q and be connected;
Described second current mirror group is connected with described electric capacity by described second control switch, the controlled end of described second control switch is held with the Q of described trigger and is connected, the Q end of described trigger, as the output of described second high-frequency generator, exports described second clock signal.
5. the light adjusting circuit according to claim 3 or 4, is characterized in that, described high level time number is binary data HD1 ~ HDN, and described low level time number is binary data LD1 ~ LDN, and wherein N is for presetting positive integer;
Described first current mirror group comprises the mirror current source IH1 ~ IHN of N number of branch road, is connected with described electric capacity respectively by K switch 11 ~ K1N, and the controlled end of described K switch 11 ~ K1N is connected with described binary data HD1 ~ HDN respectively;
Described second current mirror group comprises the mirror current source IL1 ~ ILN of N number of branch road, is connected with described electric capacity respectively by K switch 21 ~ K2N, and the controlled end of described K switch 21 ~ K2N is connected with described binary data HL1 ~ HLN respectively.
6. light adjusting circuit according to claim 5, it is characterized in that, the electric current of the mirror current source IH1 ~ IHN of described N number of branch road and the reference current of described first current mirror group are binary scale relation, i.e. IH1:IH2:IH3: ...: IHN=1:2:4: ...: 2N-1;
The electric current of the mirror current source IL1 ~ ILN of a described N branch road and the reference current of described second current mirror group are binary scale relation, i.e. IL1:IL2:IL3: ...: ILN=1:2:4: ...: 2N-1.
7. light adjusting circuit according to claim 6, is characterized in that, the reference current of described first current mirror group is equal with the reference current of described second current mirror group.
8. light adjusting circuit according to claim 1, is characterized in that, described first high-frequency generator is specially ring oscillator, and the output of described ring oscillator is connected with described counter.
9. light adjusting circuit according to claim 1, it is characterized in that, described light adjusting circuit also comprises: filter, be connected with described second high-frequency generator, second clock signal for producing described second high-frequency generator carries out filtering, and using dimmer voltage that the voltage exported after filtering exports as described light adjusting circuit.
10. light adjusting circuit according to claim 9, is characterized in that, described filter is specially second-order low-pass filter.
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| CN201510135622.XA CN104754830A (en) | 2015-03-26 | 2015-03-26 | Light dimming circuit |
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| CN201510135622.XA CN104754830A (en) | 2015-03-26 | 2015-03-26 | Light dimming circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104981067A (en) * | 2015-07-03 | 2015-10-14 | 英飞特电子（杭州）股份有限公司 | LED driver |
| CN107027222A (en) * | 2017-05-11 | 2017-08-08 | 南京矽力杰半导体技术有限公司 | Load current adjusting circuit and adjusting method |
| CN107588884A (en) * | 2017-08-08 | 2018-01-16 | 中国石油天然气集团公司 | One kind is with brill down-hole pressure measuring circuit and pressure measurement method |
-
2015
- 2015-03-26 CN CN201510135622.XA patent/CN104754830A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104981067A (en) * | 2015-07-03 | 2015-10-14 | 英飞特电子（杭州）股份有限公司 | LED driver |
| CN107027222A (en) * | 2017-05-11 | 2017-08-08 | 南京矽力杰半导体技术有限公司 | Load current adjusting circuit and adjusting method |
| CN107027222B (en) * | 2017-05-11 | 2019-06-11 | 南京矽力杰半导体技术有限公司 | Load current adjusting circuit and adjusting method |
| CN107588884A (en) * | 2017-08-08 | 2018-01-16 | 中国石油天然气集团公司 | One kind is with brill down-hole pressure measuring circuit and pressure measurement method |
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