CN210326473U - Low-edge jitter pulse signal generator - Google Patents
Low-edge jitter pulse signal generator Download PDFInfo
- Publication number
- CN210326473U CN210326473U CN201921470737.4U CN201921470737U CN210326473U CN 210326473 U CN210326473 U CN 210326473U CN 201921470737 U CN201921470737 U CN 201921470737U CN 210326473 U CN210326473 U CN 210326473U
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- pin
- module
- power supply
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
A low-edge jitter pulse signal generator. It includes that low edge jitter pulse signal generator includes: the device comprises a power supply module, a DDS module, a hysteresis voltage comparator module, a monostable trigger pulse width adjusting circuit module and an MCU module; the power supply module is connected with the DDS module, the hysteresis voltage comparator module, the monostable trigger pulse width adjusting circuit module and the MCU module, the DDS module is connected with the hysteresis voltage comparator module, the hysteresis voltage comparator module is connected with the monostable trigger pulse width adjusting circuit module, and the MCU module is connected with the DDS module. The utility model provides a low border shake pulse signal generator can reduce the pulse border shake more effectively, and the light pulse that is favorable to optic fibre pulse laser output is stable, consequently can be applicable to multiple optic fibre pulse laser well.
Description
Technical Field
The utility model belongs to the technical field of fiber laser, especially, relate to a low border shake pulse generator.
Background
The fiber pulse laser is a new generation laser which is receiving attention, and is widely applied to industrial marking and deep carving due to the excellent performance of the fiber pulse laser.
In order to stabilize the laser pulse output by the fiber pulse laser, a low-edge jitter pulse signal generator is necessary. The method for generating pulse signal by traditional pulse signal generator is firstly to generate a sine wave signal, then to compare with a fixed reference voltage to generate pulse signal. Due to the influence of noise of the sine wave signal and noise of the reference voltage, the edge of the pulse signal generated by the method is seriously jittered, and the jitter time is more than tens of nanoseconds to hundreds of nanoseconds. A pulse signal with severe edge jitter will cause instability of the laser pulse signal.
Disclosure of Invention
In order to solve the above problem, an object of the present invention is to provide a low-edge jitter pulse signal generator.
In order to achieve the above object, the present invention provides a low edge jitter pulse signal generator comprising: the device comprises a power supply module, a DDS module, a hysteresis voltage comparator module, a monostable trigger pulse width adjusting circuit module and an MCU module; wherein: the power supply module is connected with the DDS module, the hysteresis voltage comparator module, the monostable trigger pulse width adjusting circuit module and the MCU module, the DDS module is connected with the hysteresis voltage comparator module, the hysteresis voltage comparator module is connected with the monostable trigger pulse width adjusting circuit module, and the MCU module is connected with the DDS module.
The power supply module is a DC/DC integrated circuit module and comprises an integrated circuit LM22676, capacitors C21-C26, C30-C33, resistors R8-R10, diodes D3-D5, an inductor L1, a terminal JP1 and an integrated circuit LD 1117-3.3V; wherein pin 1 of terminal JP1 is connected with external power supply 24V and with the anode of diode D3, pin 2 of terminal JP1 is connected with ground GND, the cathode of diode D3 is connected with pin 7 of integrated circuit LM22676, the two ends of capacitor C22 and capacitor C23 are respectively connected with the cathode of diode D3 and ground GND, one end of capacitor C24 is connected with pin 5 of integrated circuit LM22676 and the other end is connected with ground GND, pin 7 of integrated circuit LM22676 is connected with the cathode of diode D3, pin 6 is connected with ground GND, one end of resistor R8 is connected with pin 4 of integrated circuit LM22676 and the other end is connected with ground GND, one end of resistor R9 is connected with pin 4 of integrated circuit LM22676 and the other end is power supply VDD5V, the two ends of capacitor C21 are respectively connected with pin 1 and pin 8 of integrated circuit LM22676, the cathode of diode D5 is connected with pin 8 of integrated circuit LM22676 and the anode GND is connected with ground GND, one end of an inductor L1 is connected with a pin 8 of an integrated circuit LM22676, the other end is connected with a power supply VDD5V, two ends of a capacitor C25 are respectively connected with a power supply VDD5V and a ground line GND, the anode of a capacitor C26 is connected with a power supply VDD5V, the cathode is connected with the ground line GND, the anode of a diode D4 is connected with the power supply VDD5V, the cathode is connected with the ground line GND through a resistor R10, one end of a capacitor C30 is connected with a pin 3 of an integrated circuit LD1117-3.3V and is connected with the anode of a diode D4, the other end is connected with the ground line GND, the anode of a capacitor C31 is connected with a pin 3 of the integrated circuit LD1117-3.3V, the cathode is connected with the GND ground line GND, the anode of a capacitor C32 is connected with a pin 2 of the integrated circuit LD1117-3.3V, the cathode is connected with the ground line GND, the ground line is connected with a pin 1 of the integrated circuit LD1117-3.3V and is connected with the ground line, the other end is connected with a ground wire GND, and a 4 pin of the integrated circuit LD1117-3.3V is connected with a 2 pin of the integrated circuit LD 1117-3.3V.
The DDS module and the hysteresis voltage comparator module adopt DDS modules with hysteresis voltage comparison inside; the DDS module with the hysteresis voltage comparison inside comprises: an integrated circuit AD9851, capacitors CW2, CW6, CW8-CW12, resistors RW1, RW3, and RW 4; wherein: two ends of a capacitor CW2 are respectively connected with a power supply VDD5V and a ground GND, a 6 pin and a 5 pin of an integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, an anode of a capacitor CW8 is connected with a power supply VDD5V, a cathode of the capacitor CW8 is connected with a ground GND, two ends of a capacitor CW9 are respectively connected with a power supply VDD5V and a ground RW, an 11 pin and a 10 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, two ends of a capacitor CW6 are respectively connected with a power supply VDD5V and a ground GND, a 23 pin and a 24 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, two ends of a capacitor CW10 are respectively connected with a power supply VDD5V and a ground GND, an 18 pin and a 19 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, a resistor CW 48 is connected with a resistor RW3 in parallel, one end of, one end of the integrated circuit AD9851 is connected with a pin 21, the other end of the integrated circuit AD9851 is connected with a ground wire GND, pins 1 to 4 of the integrated circuit AD9851 are sequentially data buses D3-D0 and pins 25 to 28 are sequentially data buses D7-D4, a pin 7 of the integrated circuit AD9851 is a W _ CLK end, a pin 8 of the integrated circuit AD9851 is an FQ _ UD end, a pin 9 of the integrated circuit AD9851 is an R _ CLK end and is used for being connected with an external crystal oscillator, a pin 14 of the integrated circuit AD9851 is a PULSE end, and a pin 22 of the.
The monostable trigger pulse width regulation circuit module adopts an SN74LVC1G123 chip and comprises an integrated circuit SN74LVC1G123, capacitors CW13-CW15, resistors RW2, RW5 and a variable resistor R1; wherein: pins 1 and 4 of the integrated circuit SN74LVC1G123 are connected to a ground GND, pins 3 and 8 are connected to a power supply VDD5V, pin 2 is a PULSE terminal and is connected to pin 14 of the integrated circuit AD9851, one end of a capacitor CW14 is connected to a power supply VDD5V, the other end is connected to a ground GND, two ends of the capacitor CW15 are connected to pins 6 and 7 of the integrated circuit SN74LVC1G123, respectively, one fixed end of a variable resistor R1 is connected to pin 7 of the integrated circuit SN74LVC1G123 through a resistor RW5, the other fixed end and a movable end are connected to a power supply VDD5V, one end of the resistor RW2 is connected to pin 5 of the integrated circuit SN74LVC1G123, the other end is a PULSE output terminal, one end of the capacitor CW13 is connected to the PULSE output terminal, and the other end is connected to the ground GND.
The MCU module adopts a 51-series singlechip or an ARM-series microcontroller chip and comprises an integrated circuit C8051F, capacitors CW16-CW18, resistors RW6 and RW 7; wherein: 26-19 pins of an integrated circuit C8051F are sequentially a data bus D0-D7 end, are respectively connected with a corresponding end of an integrated circuit AD9851 data bus D0-D7, 15 pins and 16 pins of the integrated circuit C8051F are respectively a W _ CLK end and a FQ _ UD end, and are connected with a corresponding end of an integrated circuit AD9851 RW, 17 pin of the integrated circuit C8051F is a RESET end and is connected with a corresponding end of the integrated circuit AD9851, two ends of a capacitor CW16 are respectively connected with 3 pins and 4 pins of the integrated circuit C8051F, 3 pins and 4 pins of the integrated circuit C8051F are respectively connected with a ground wire GND and a power supply VDD3V, one end of a resistor RW7 is connected with a power supply VDD3V, the other end of the resistor RW is connected with a 5 pin of the integrated circuit C8051F through a resistor RW6, and after the capacitors CW17 and the CW18 are connected in parallel, one end of the resistor 6 and the other end of the resistor 7 are connected with the ground.
The utility model provides a low border shake pulse signal generator has following advantage:
the utility model discloses utilize MCU module control DDS module to produce two way sinusoidal wave signals of a homologous opposition, output pulse signal behind the more two way sinusoidal opposition signals of hysteresis voltage comparator module, can realize the pulse signal with adjustable output pulse width behind the pulse width modulation circuit module is triggered to the monostable of rethread, signal frequency is arbitrary adjustable in 20KHz ~ 200KHz, and the output frequency precision can reach 1/10000, pulse width is steerable in several microseconds to tens of microseconds rank, output pulse rises/falls along < 5ns, pulse jitter (jitter) control is within 5 ns. The utility model provides a low border shake pulse signal generator can reduce the pulse border shake more effectively, and the light pulse that is favorable to optic fibre pulse laser output is stable, consequently can be applicable to multiple optic fibre pulse laser well.
Drawings
Fig. 1 is a block diagram of a low edge jitter pulse signal generator according to the present invention.
Fig. 2 is a circuit diagram of a power supply module in the low-edge jitter pulse signal generator according to the present invention.
Fig. 3 is a circuit diagram of a DDS module with a hysteresis voltage comparison module in a low-edge dither pulse signal generator.
Fig. 4 is a circuit diagram of a monostable trigger pulse width adjusting circuit module in the low edge jitter pulse signal generator according to the present invention.
Fig. 5 is a circuit diagram of the MCU module in the low edge dither pulse signal generator according to the present invention.
Detailed Description
The present invention provides a low edge jitter pulse signal generator, which is described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the present invention provides a low edge jitter pulse signal generator comprising: the device comprises a power supply module 1, a DDS module 2, a hysteresis voltage comparator module 3, a monostable trigger pulse width regulation circuit module 4 and an MCU module 5; wherein: the power supply module 1 is connected with the DDS module 2, the hysteresis voltage comparator module 3, the monostable trigger pulse width regulation circuit module 4 and the MCU module 5, the DDS module 2 is connected with the hysteresis voltage comparator module 3, the hysteresis voltage comparator module 3 is connected with the monostable trigger pulse width regulation circuit module 4, and the MCU module 5 is connected with the DDS module 2; the power supply module 1 is mainly used for power supply and power management of the DDS module 2, the monostable trigger pulse width regulation circuit module 4 and the MCU module 5; the DDS module 2 is used for generating two paths of sine wave signals with same source phase inversion, and the hysteresis voltage comparator module 3 outputs pulse signals after comparing the two paths of sine phase inversion signals; the monostable trigger pulse width adjusting circuit module 4 is used for adjusting the output pulse width; the MCU module 5 is used for setting parameters of the DDS module 2 to generate two paths of sine wave signals with same source and opposite phase.
The power supply module 1 is a DC/DC integrated circuit module, and is mainly used for supplying power to the whole device and realizing power supply management.
The DDS module 2 adopts an AD9851 chip or other direct digital frequency synthesis chips and is mainly used for generating two paths of sine wave signals with same source and opposite phase.
The hysteresis voltage comparator module 3 adopts an AD9851 chip, is internally provided with a hysteresis voltage comparator, and is mainly used for comparing two paths of sine wave signals with the same source and opposite phase and then outputting a pulse signal.
The monostable trigger pulse width adjusting circuit module 4 adopts an SN74LVC1G123 chip and is mainly used for adjusting the pulse signal width under different repetition frequencies.
The MCU module 5 adopts a 51 series single chip microcomputer or an ARM (advanced RISC machine) series microcontroller chip, and is mainly used for controlling the DDS module 2 to generate two paths of sine wave signals with the same source and opposite phase.
As shown in fig. 2, the power supply module 1 includes: integrated circuit LM22676, capacitor C21-C26, C30-C33, resistance R8-R10, diode D3-D5, inductor L1, terminal JP1, integrated circuit LD 1117-3.3V; wherein pin 1 of terminal JP1 is connected with external power supply 24V and with the anode of diode D3, pin 2 of terminal JP1 is connected with ground GND, the cathode of diode D3 is connected with pin 7 of integrated circuit LM22676, the two ends of capacitor C22 and capacitor C23 are respectively connected with the cathode of diode D3 and ground GND, one end of capacitor C24 is connected with pin 5 of integrated circuit LM22676 and the other end is connected with ground GND, pin 7 of integrated circuit LM22676 is connected with the cathode of diode D3, pin 6 is connected with ground GND, one end of resistor R8 is connected with pin 4 of integrated circuit LM22676 and the other end is connected with ground GND, one end of resistor R9 is connected with pin 4 of integrated circuit LM22676 and the other end is power supply VDD5V, the two ends of capacitor C21 are respectively connected with pin 1 and pin 8 of integrated circuit LM22676, the cathode of diode D5 is connected with pin 8 of integrated circuit LM22676 and the anode GND is connected with ground GND, one end of an inductor L1 is connected with a pin 8 of an integrated circuit LM22676, the other end is connected with a power supply VDD5V, two ends of a capacitor C25 are respectively connected with a power supply VDD5V and a ground line GND, the anode of a capacitor C26 is connected with a power supply VDD5V, the cathode is connected with the ground line GND, the anode of a diode D4 is connected with the power supply VDD5V, the cathode is connected with the ground line GND through a resistor R10, one end of a capacitor C30 is connected with a pin 3 of an integrated circuit LD1117-3.3V and is connected with the anode of a diode D4, the other end is connected with the ground line GND, the anode of a capacitor C31 is connected with a pin 3 of the integrated circuit LD1117-3.3V, the cathode is connected with the GND ground line GND, the anode of a capacitor C32 is connected with a pin 2 of the integrated circuit LD1117-3.3V, the cathode is connected with the ground line GND, the ground line is connected with a pin 1 of the integrated circuit LD1117-3.3V and is connected with the ground line, the other end is connected with a ground wire GND, and a 4 pin of the integrated circuit LD1117-3.3V is connected with a 2 pin of the integrated circuit LD 1117-3.3V.
The DDS module 2 and the hysteresis voltage comparator module 3 adopt DDS modules with hysteresis voltage comparison inside; as shown in fig. 3, the DDS module with internal hysteresis voltage comparison includes: an integrated circuit AD9851, capacitors CW2, CW6, CW8-CW12, resistors RW1, RW3 and RW 4; wherein: two ends of a capacitor CW2 are respectively connected with a power supply VDD5V and a ground GND, a 6 pin and a 5 pin of an integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, an anode of a capacitor CW8 is connected with a power supply VDD5V, a cathode of the capacitor CW8 is connected with a ground GND, two ends of a capacitor CW9 are respectively connected with a power supply VDD5V and a ground RW, an 11 pin and a 10 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, two ends of a capacitor CW6 are respectively connected with a power supply VDD5V and a ground GND, a 23 pin and a 24 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, two ends of a capacitor CW10 are respectively connected with a power supply VDD5V and a ground GND, an 18 pin and a 19 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, a resistor CW 48 is connected with a resistor RW3 in parallel, one end of, one end of the integrated circuit AD9851 is connected with a pin 21, the other end of the integrated circuit AD9851 is connected with a ground wire GND, pins 1 to 4 of the integrated circuit AD9851 are sequentially data buses D3-D0 and pins 25 to 28 are sequentially data buses D7-D4, a pin 7 of the integrated circuit AD9851 is a W _ CLK end, a pin 8 of the integrated circuit AD9851 is an FQ _ UD end, a pin 9 of the integrated circuit AD9851 is an R _ CLK end and is used for being connected with an external crystal oscillator, a pin 14 of the integrated circuit AD9851 is a PULSE end, and a pin 22 of the.
As shown in fig. 4, the monostable trigger pulse width adjusting circuit block 4 includes: an integrated circuit SN74LVC1G123, capacitors CW13-CW15, resistors RW2, RW5 and a variable resistor R1; wherein: pins 1 and 4 of the integrated circuit SN74LVC1G123 are connected to a ground GND, pins 3 and 8 are connected to a power supply VDD5V, pin 2 is a PULSE terminal and is connected to pin 14 of the integrated circuit AD9851, one end of a capacitor CW14 is connected to a power supply VDD5V, the other end is connected to a ground GND, two ends of the capacitor CW15 are connected to pins 6 and 7 of the integrated circuit SN74LVC1G123, respectively, one fixed end of a variable resistor R1 is connected to pin 7 of the integrated circuit SN74LVC1G123 through a resistor RW5, the other fixed end and a movable end are connected to a power supply VDD5V, one end of the resistor RW2 is connected to pin 5 of the integrated circuit SN74LVC1G123, the other end is a PULSE output terminal, one end of the capacitor CW13 is connected to the PULSE output terminal, and the other end is connected to the ground GND.
As shown in fig. 5, the MCU block 5 includes: an integrated circuit C8051F, capacitors CW16-CW18, resistors RW6, RW 7; wherein: 26-19 pins of an integrated circuit C8051F are sequentially a data bus D0-D7 end, are respectively connected with a corresponding end of an integrated circuit AD9851 data bus D0-D7, 15 pins and 16 pins of the integrated circuit C8051F are respectively a W _ CLK end and a FQ _ UD end, and are connected with a corresponding end of an integrated circuit AD9851 RW, 17 pin of the integrated circuit C8051F is a RESET end and is connected with a corresponding end of the integrated circuit AD9851, two ends of a capacitor CW16 are respectively connected with 3 pins and 4 pins of the integrated circuit C8051F, 3 pins and 4 pins of the integrated circuit C8051F are respectively connected with a ground wire GND and a power supply VDD3V, one end of a resistor RW7 is connected with a power supply VDD3V, the other end of the resistor RW is connected with a 5 pin of the integrated circuit C8051F through a resistor RW6, and after the capacitors CW17 and the CW18 are connected in parallel, one end of the resistor 6 and the other end of the resistor 7 are connected with the ground.
The utility model provides a low border shake pulse signal generator can control the shake of pulse border effectively to be favorable to strengthening the light pulse stability of optic fibre pulse laser output.
The above description is only a detailed description of the present invention, and is not intended to limit the present invention. The scope of protection of the present invention is not limited thereto, and any changes, modifications, additions, substitutions and application extensions that may be made by those skilled in the art based on the devices of the present invention shall be considered to fall within the scope of protection of the present invention.
Claims (5)
1. A low-edge dither pulse signal generator, comprising: the low-edge jitter pulse signal generator comprises: the device comprises a power supply module (1), a DDS module (2), a hysteresis voltage comparator module (3), a monostable trigger pulse width regulation circuit module (4) and an MCU module (5); wherein: the power supply module (1) is connected with the DDS module (2), the hysteresis voltage comparator module (3), the monostable trigger pulse width regulation circuit module (4) and the MCU module (5), the DDS module (2) is connected with the hysteresis voltage comparator module (3), the hysteresis voltage comparator module (3) is connected with the monostable trigger pulse width regulation circuit module (4), and the MCU module (5) is connected with the DDS module (2).
2. The low-edge dithered pulse signal generator of claim 1 wherein: the power supply module (1) is a DC/DC integrated circuit module and comprises an integrated circuit LM22676, capacitors C21-C26, C30-C33, resistors R8-R10, diodes D3-D5, an inductor L1, a terminal JP1 and an integrated circuit LD 1117-3.3V; wherein pin 1 of terminal JP1 is connected with external power supply 24V and with the anode of diode D3, pin 2 of terminal JP1 is connected with ground GND, the cathode of diode D3 is connected with pin 7 of integrated circuit LM22676, the two ends of capacitor C22 and capacitor C23 are respectively connected with the cathode of diode D3 and ground GND, one end of capacitor C24 is connected with pin 5 of integrated circuit LM22676 and the other end is connected with ground GND, pin 7 of integrated circuit LM22676 is connected with the cathode of diode D3, pin 6 is connected with ground GND, one end of resistor R8 is connected with pin 4 of integrated circuit LM22676 and the other end is connected with ground GND, one end of resistor R9 is connected with pin 4 of integrated circuit LM22676 and the other end is power supply VDD5V, the two ends of capacitor C21 are respectively connected with pin 1 and pin 8 of integrated circuit LM22676, the cathode of diode D5 is connected with pin 8 of integrated circuit LM22676 and the anode GND is connected with ground GND, one end of an inductor L1 is connected with a pin 8 of an integrated circuit LM22676, the other end is connected with a power supply VDD5V, two ends of a capacitor C25 are respectively connected with a power supply VDD5V and a ground line GND, the anode of a capacitor C26 is connected with a power supply VDD5V, the cathode is connected with the ground line GND, the anode of a diode D4 is connected with the power supply VDD5V, the cathode is connected with the ground line GND through a resistor R10, one end of a capacitor C30 is connected with a pin 3 of an integrated circuit LD1117-3.3V and is connected with the anode of a diode D4, the other end is connected with the ground line GND, the anode of a capacitor C31 is connected with a pin 3 of the integrated circuit LD1117-3.3V, the cathode is connected with the GND ground line GND, the anode of a capacitor C32 is connected with a pin 2 of the integrated circuit LD1117-3.3V, the cathode is connected with the ground line GND, the ground line is connected with a pin 1 of the integrated circuit LD1117-3.3V and is connected with the ground line, the other end is connected with a ground wire GND, and a 4 pin of the integrated circuit LD1117-3.3V is connected with a 2 pin of the integrated circuit LD 1117-3.3V.
3. The low-edge dithered pulse signal generator of claim 1 wherein: the DDS module (2) and the hysteresis voltage comparator module (3) adopt DDS modules with hysteresis voltage comparison inside; the DDS module with the hysteresis voltage comparison inside comprises: an integrated circuit AD9851, capacitors CW2, CW6, CW8-CW12, resistors RW1, RW3, and RW 4; wherein: two ends of a capacitor CW2 are respectively connected with a power supply VDD5V and a ground GND, a 6 pin and a 5 pin of an integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, an anode of a capacitor CW8 is connected with a power supply VDD5V, a cathode of the capacitor CW8 is connected with a ground GND, two ends of a capacitor CW9 are respectively connected with a power supply VDD5V and a ground RW, an 11 pin and a 10 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, two ends of a capacitor CW6 are respectively connected with a power supply VDD5V and a ground GND, a 23 pin and a 24 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, two ends of a capacitor CW10 are respectively connected with a power supply VDD5V and a ground GND, an 18 pin and a 19 pin of the integrated circuit AD9851 are respectively connected with a power supply VDD5V and a ground GND, a resistor CW 48 is connected with a resistor RW3 in parallel, one end of, one end of the integrated circuit AD9851 is connected with a pin 21, the other end of the integrated circuit AD9851 is connected with a ground wire GND, pins 1 to 4 of the integrated circuit AD9851 are sequentially data buses D3-D0 and pins 25 to 28 are sequentially data buses D7-D4, a pin 7 of the integrated circuit AD9851 is a W _ CLK end, a pin 8 of the integrated circuit AD9851 is an FQ _ UD end, a pin 9 of the integrated circuit AD9851 is an R _ CLK end and is used for being connected with an external crystal oscillator, a pin 14 of the integrated circuit AD9851 is a PULSE end, and a pin 22 of the.
4. The low-edge dithered pulse signal generator of claim 1 wherein: the monostable trigger pulse width regulation circuit module (4) adopts an SN74LVC1G123 chip and comprises an integrated circuit SN74LVC1G123, capacitors CW13-CW15, resistors RW2, RW5 and a variable resistor R1; wherein: pins 1 and 4 of the integrated circuit SN74LVC1G123 are connected to a ground GND, pins 3 and 8 are connected to a power supply VDD5V, pin 2 is a PULSE terminal and is connected to pin 14 of the integrated circuit AD9851, one end of a capacitor CW14 is connected to a power supply VDD5V, the other end is connected to a ground GND, two ends of the capacitor CW15 are connected to pins 6 and 7 of the integrated circuit SN74LVC1G123, respectively, one fixed end of a variable resistor R1 is connected to pin 7 of the integrated circuit SN74LVC1G123 through a resistor RW5, the other fixed end and a movable end are connected to a power supply VDD5V, one end of the resistor RW2 is connected to pin 5 of the integrated circuit SN74LVC1G123, the other end is a PULSE output terminal, one end of the capacitor CW13 is connected to the PULSE output terminal, and the other end is connected to the ground GND.
5. The low-edge dithered pulse signal generator of claim 1 wherein: the MCU module (5) adopts a 51-series single chip microcomputer or an ARM-series microcontroller chip and comprises an integrated circuit C8051F, capacitors CW16-CW18, resistors RW6 and RW 7; wherein: 26-19 pins of an integrated circuit C8051F are sequentially a data bus D0-D7 end, are respectively connected with a corresponding end of an integrated circuit AD9851 data bus D0-D7, 15 pins and 16 pins of the integrated circuit C8051F are respectively a W _ CLK end and a FQ _ UD end, and are connected with a corresponding end of an integrated circuit AD9851 RW, 17 pin of the integrated circuit C8051F is a RESET end and is connected with a corresponding end of the integrated circuit AD9851, two ends of a capacitor CW16 are respectively connected with 3 pins and 4 pins of the integrated circuit C8051F, 3 pins and 4 pins of the integrated circuit C8051F are respectively connected with a ground wire GND and a power supply VDD3V, one end of a resistor RW7 is connected with a power supply VDD3V, the other end of the resistor RW is connected with a 5 pin of the integrated circuit C8051F through a resistor RW6, and after the capacitors CW17 and the CW18 are connected in parallel, one end of the resistor 6 and the other end of the resistor 7 are connected with the ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921470737.4U CN210326473U (en) | 2019-09-05 | 2019-09-05 | Low-edge jitter pulse signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921470737.4U CN210326473U (en) | 2019-09-05 | 2019-09-05 | Low-edge jitter pulse signal generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210326473U true CN210326473U (en) | 2020-04-14 |
Family
ID=70132157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921470737.4U Active CN210326473U (en) | 2019-09-05 | 2019-09-05 | Low-edge jitter pulse signal generator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210326473U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600981A (en) * | 2019-09-05 | 2019-12-20 | 山东海富光子科技股份有限公司 | Low-edge jitter pulse signal generator |
-
2019
- 2019-09-05 CN CN201921470737.4U patent/CN210326473U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600981A (en) * | 2019-09-05 | 2019-12-20 | 山东海富光子科技股份有限公司 | Low-edge jitter pulse signal generator |
| CN110600981B (en) * | 2019-09-05 | 2024-03-22 | 山东海富光子科技股份有限公司 | Low-edge-jitter pulse signal generator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3759105B2 (en) | Clock generator especially for USB devices | |
| CN210326473U (en) | Low-edge jitter pulse signal generator | |
| CN103807192A (en) | Computer fan control circuit | |
| CN105900307B (en) | The control of DC transmission line | |
| CN104133166A (en) | Large-power arbitrary-waveform generation device and method | |
| CN107706737B (en) | A kind of accurate adjustable pulse generating circuit of frequency for semiconductor laser | |
| CN102933003B (en) | Dimming circuit | |
| CN110600981B (en) | Low-edge-jitter pulse signal generator | |
| KR20220162790A (en) | Pulse cancellation circuit, voltage measurement circuit and measurement method | |
| CN117374725A (en) | Burst mode laser drive control circuit and method | |
| CN203377864U (en) | Direct digital frequency synthesizer | |
| CN103677028A (en) | Digital current equalizing method and power supply module | |
| CN104754830A (en) | Light dimming circuit | |
| CN109474239A (en) | 5G standard source high-frequency crystal oscillator circuit | |
| CN205121246U (en) | FPGA -based DDS signal generator | |
| CN201260025Y (en) | Laser driving source | |
| CN202998570U (en) | Dimming circuit | |
| CN107834354A (en) | A kind of signal generator applied to high-peak power laser | |
| CN211127776U (en) | High-speed pulse output circuit based on ARM | |
| CN221102691U (en) | Driving circuit of phase ranging continuous laser diode | |
| RU2624635C1 (en) | Multichannel pulse current stabiliser (versions) | |
| CN210807074U (en) | Voltage regulating circuit of photoelectric detector | |
| CN218040199U (en) | Laser device adjusting circuit and laser device | |
| CN101923379A (en) | Reset voltage generation circuit | |
| CN109309487A (en) | A kind of signal spread spectrum control method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A pulse signal generator with low edge jitter Effective date of registration: 20210517 Granted publication date: 20200414 Pledgee: Weihai City Commercial Bank Limited by Share Ltd. high tech branch Pledgor: HFB Photonics Co.,Ltd. Registration number: Y2021980003674 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |