CN104733534B - P type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor - Google Patents
P type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor Download PDFInfo
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Abstract
The present invention discloses a kind of new SJ LDMOS devices.Compared with traditional SJ LDMOS, the present invention compensate for the charge unbalance between super junction NeiNXing Zhu areas and PXing Zhu areas, overcome substrate secondary effects, improve breakdown voltage by p type buried layer and the collective effect of buffer layers of N-type；Meanwhile, p type buried layer can improve the concentration of buffer layers of N-type, and conducting resistance is compared in reduction.It can be seen that being the balance of high-breakdown-voltage, low on-resistance and super junction layer charge the characteristics of the structure.The new SJ LDMOS devices structure that the present invention is provided also has manufacturing process relatively easy, the characteristics of technology difficulty is relatively low.The present invention is more easy to meet the application requirement of power electronic system.
Description
Technical field
The present invention relates to semiconductor power device technology field, and in particular to a kind of super-junction laterally bilateral diffusion metal oxide
Semiconductor field.
Background technology
What horizontal high voltage power semiconductor device LDMOS (Lateral Double-diffused MOSFET) referred to has
The high-voltage power MOS device of lateral channel structure.Because the drain electrode of this kind of device, source electrode and grid are all on the surface of chip, easily
In integrated with low-voltage signal circuit by inside connection, therefore in high voltage integrated circuit (HVIC) and power integrated circuit (PIC)
It is used as the key of technology.But in power MOS (Metal Oxide Semiconductor) device design, conducting resistance (Ron) as breakdown voltage (BV) is with 2.5 powers
Speed increase so that power MOS high-voltage applications are very restricted.
Superjunction (super junction) structure is the NXing Zhu areas and PXing Zhu areas being alternately arranged, if with super-junction structure come
Replace LDMOS drift region, be formed super junction LDMOS, abbreviation SJ-LDMOS.In theory, super-junction structure by NXing Zhu areas and
Charge balance between PXing Zhu areas can obtain high breakdown voltage, and can be with by the NXing Zhu areas and PXing Zhu areas of heavy doping
Very low conducting resistance is obtained, therefore, superjunction devices can be obtained between two key parameters of breakdown voltage and conducting resistance
One compromise well.
But for SJ-LDMOS, due to substrate-assisted depletion NXing Zhu areas (HuoPXing Zhu areas) so that during device breakdown, P
Xing Zhu areas (HuoNXing Zhu areas) can not be completely depleted, breaks the charge balance between LiaoNXing Zhu areas and PXing Zhu areas, reduces SJ-
The lateral breakdown voltage of LDMOS device.
The content of the invention
The present invention proposes a kind of p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, with
Substrate-assisted depletion effect is solved the problem of reduce SJ-LDMOS breakdown voltage, and improve breakdown voltage with than electric conduction
Contradictory relation between resistance, realizes high breakdown voltage and low ratio conducting resistance.
The present invention program is as follows：
P type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, including：
P-type semiconductor substrate；
The p-type base on a part of surface of N-type epitaxy layer on the P-type semiconductor substrate；
Positioned at the N-type source region of p-type base part surface；
Corresponding to the super interface on N-type epitaxy layer another part surface on the P-type semiconductor substrate, including NXing Zhu areas
With PXing Zhu areas；The NXing Zhu areas in super interface and the adjoining of PXing Zhu areas Jun YuPXing bases；
Positioned at the N-type drain region of super interface part surface；
It is characterized in that：
Have one on the lower surface in super interface and the P-type semiconductor substrate between N-type epitaxy layer another part surface
Buffer layers of N-type of layer；
NXing Zhu areas portion of upper surface covered with the p-type buried dopant layer abutted with the N-type drain region, the NXing Zhu areas
There is difference in height in portion of upper surface, with its another part upper surface so that p-type buried dopant layer is isolated with p-type base；It is described another
Portion of upper surface is concordant with the upper surface in PXing Zhu areas.
Based on above-mentioned basic scheme, the present invention also further does following optimization and limits and improve：
The doping concentration of buffer layers of aforementioned p-type buried dopant layer and N-type is more than the doping concentration of P-type semiconductor substrate.
The surface in above-mentioned NXing Zhu areas is that stepped-style separates two parts to embody the difference in height.It should be appreciated that this
In described stepped-style should broadly understood, that is, be not required for as smooth ladder.
Above-mentioned super interface is discharged using the horizontal period distances in NXing Zhu areas and PXing Zhu areas, the width phase in each NXing Zhu area
Together, the width in each PXing Zhu area is identical.Further, each NXing Zhu areas are preferably also identical with the width in each PXing Zhu areas.
The cross section of aforementioned p-type buried dopant layer is regular figure (it is of course also possible to being irregular figure), with circular or
Rectangle is preferred.
The longitudinal section of aforementioned p-type buried dopant layer is regular figure (it is of course also possible to being irregular figure), with circular or
Rectangle is preferred.
The concentration of aforementioned p-type buried dopant layer is uniform (it is of course also possible to being heterogeneous).
Beneficial effects of the present invention are as follows：
By introducing buffer layers of p type buried layer and N-type above and below super interface, super junction NeiNXing Zhu areas and p-type compensate for
Charge unbalance between post area, overcomes substrate secondary effects, improves breakdown voltage；Meanwhile, p type buried layer can improve N
Conducting resistance is compared in the concentration of type drift region, reduction.Therefore the optimization than general scheme breakdown voltage and than conducting resistance can be with
Further lifted.
This programme device is simple to manufacture, and operability is stronger.
Brief description of the drawings
Fig. 1 is the three-dimensional of p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of the present invention
Schematic diagram.
Fig. 2 is the sectional view of the structure drift region along AOC directions.
Embodiment
Referring to Fig. 1 and Fig. 2, partly led with a kind of p type buried layer cover type N-channel super-junction laterally bilateral diffusion metal oxide below
Specifically new construction in the embodiment of the present invention is introduced exemplified by body FET：
P type buried layer cover type N-channel super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, including：
P-type semiconductor substrate 1；
The adjacent p-type base 2 in the surface of N-type epitaxy layer 9 and N-type buffer layers 3 on the P-type semiconductor substrate；
The super interface adjacent with the p-type base on N-type buffer layers 3, includes the N of arrangement of horizontal cycle
Xing Zhu areas 4 and PXing Zhu areas 5；
The p-type buried dopant layer 8 adjacent only with N-type drain region 6 in NXing Zhu areas 4, between p-type buried dopant layer and base
It is separated by one section of N-type drift region (NXing Zhu areas).
Wherein, p-type buried dopant layer cross section can be regular figure, such as：Circular, rectangle, or irregular
Figure.
Wherein, the longitudinal section of p-type buried dopant layer can be regular figure, such as：Circular, rectangle, or irregular
Figure.
Wherein, it can also be uniformly heterogeneous that the concentration of p-type buried dopant layer, which can be,.
Further, the doping concentration in two region of p-type buried dopant layer and N-type the buffer layer is more than the doping of substrate
Concentration so that electroneutral effect is more obvious.
The preparation method of aforementioned p-type buried regions cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, its
Step includes：
P-type base is formed in N-type epitaxy layer on the P-type semiconductor substrate；
N-type source region 7 is formed in the p-type base；
Buffer layers of N-type is formed in the N-type epitaxy layer；
Super interface is formed on the N-type buffer floor (includes NXing Zhu areas and the p-type post of horizontal period distances discharge
Area)；
P-type buried dopant layer is formed in the NXing Zhu areas；
Heavily doped N-type drain region is formed on the super interface.
Specific doping process, has very ripe technology, will not be described in detail herein in the prior art.
Technical scheme, by introducing p type buried layer and N areas buffer floor above and below super interface, compensate for surpassing
Charge unbalance between Ji JieneiNXing posts area and PXing Zhu areas, overcomes substrate secondary effects, improves breakdown voltage；Together
When, p type buried layer can improve the concentration of buffer layers of N-type, and conducting resistance is compared in reduction.Therefore breakdown voltage and than conducting resistance
It can be optimized.Hence improve LDMOS breakdown voltage and than the contradictory relation between conducting resistance, therefore to realize collection
A kind of new device architecture is provided into technology.
Certainly, LDMOS of the invention can also be " P ", " N " relation pair of P-channel, then structure and above N-channel scheme
Adjust, that is, be changed to " N-type substrate ", " N-type base ", " p-type source region ", " p-type drain region " ... and will not be repeated here.Although claim
It is not construed as limiting, it is apparent that the P-channel scheme of such a structure should be considered as to the equivalent of claim, belongs to claim institute table
The scope of patent protection reached.
Above example is only the preferred embodiment of the present invention, it is noted that for the ordinary skill of the art
For personnel, without departing from the technical principles of the invention, some improvement and replacement can also be made, these improve and replaced
Change and also should be regarded as protection scope of the present invention.
Claims (7)
1.P type buried regions cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistors, including：
P-type semiconductor substrate；
The p-type base on a part of surface of N-type epitaxy layer on the P-type semiconductor substrate；
Positioned at the N-type source region of p-type base part surface；
Corresponding to the super interface on N-type epitaxy layer another part surface on the P-type semiconductor substrate, including NXing Zhu areas and p-type
Post area；The NXing Zhu areas in super interface and the adjoining of PXing Zhu areas Jun YuPXing bases；
Positioned at the N-type drain region of super interface part surface；
It is characterized in that：
There is one layer of N-type on the lower surface in super interface and the P-type semiconductor substrate between N-type epitaxy layer another part surface
Buffer layers；
NXing Zhu areas portion of upper surface covered with the p-type buried dopant layer abutted with the N-type drain region, the part in the NXing Zhu areas
There is difference in height in upper surface, with its another part upper surface so that p-type buried dopant layer is isolated with p-type base；Described another part
Upper surface is concordant with the upper surface in PXing Zhu areas.
2. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The surface in the NXing Zhu areas is that stepped-style separates two parts to embody the difference in height.
3. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The super interface is discharged using the horizontal period distances in NXing Zhu areas and PXing Zhu areas, the width in each NXing Zhu area
Identical, the width in each PXing Zhu area is identical.
4. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The cross section and/or longitudinal section of the p-type buried dopant layer are regular figure.
5. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 4,
It is characterized in that：The regular figure is circular or rectangle.
6. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The concentration of the p-type buried dopant layer is uniform.
7. p type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1,
It is characterized in that：The doping concentration of buffer layers of the p-type buried dopant layer and N-type is more than the doping concentration of P-type semiconductor substrate.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916728A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Manufacture technology of superstructure LDMOS structure on SOI capable of completely eliminating substrate-assisted depletion effect |
| CN103165678A (en) * | 2013-03-12 | 2013-06-19 | 电子科技大学 | Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device |
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| JP4703196B2 (en) * | 2005-01-18 | 2011-06-15 | 株式会社東芝 | Semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916728A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Manufacture technology of superstructure LDMOS structure on SOI capable of completely eliminating substrate-assisted depletion effect |
| CN103165678A (en) * | 2013-03-12 | 2013-06-19 | 电子科技大学 | Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device |
Non-Patent Citations (2)
| Title |
|---|
| SJ LDMOS器件结构仿真与研究;唐盼盼;《中国优秀硕士学位论文电子期刊》;20130228;全文 * |
| 横向超结器件衬底辅助耗尽效应的研究与展望;黄示，etal;《微电子学》;20130831;第43卷(第4期);全文 * |
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