CN104733377A - Method for achieving groove field effect transistor source electrode contact groove self aligned structure - Google Patents
Method for achieving groove field effect transistor source electrode contact groove self aligned structure Download PDFInfo
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- CN104733377A CN104733377A CN201310719625.9A CN201310719625A CN104733377A CN 104733377 A CN104733377 A CN 104733377A CN 201310719625 A CN201310719625 A CN 201310719625A CN 104733377 A CN104733377 A CN 104733377A
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Abstract
The invention discloses a method for achieving a groove field effect transistor source electrode contact groove self aligned structure. The method comprises the steps that 1, first oxidation film is deposited in a silicon substrate to be taken as a groove etching barrier layer; 2, etching is conducted on the groove etching barrier layer, and after a bowl-shaped structure is formed, grooves are formed through etching; 3, grid oxidation film and grid polycrystalline silicon are formed, and the grid polycrystalline silicon is etched back; 4, the positions of contact grooves are defined, etching is conducted, and source electrode contact grooves are formed; 5, second oxidation film is deposited; 6, the second oxidation film is etched to the surfaces of the grid polycrystalline silicon; 7, the surfaces of the grid polycrystalline silicon are etched to the surface of the silicon substrate; 8, the oxidation film of the surface of the silicon substrate is etched; 9, a body injection layer and a source electrode injection layer are completed; 10, an interlayer media layer is formed, and parts of the source electrode contact grooves in the interlayer media layer are defined; 11, metal barrier layers, tungsten plugs and metal layers of the source electrode contact grooves are formed. According to the method for achieving the groove field effect transistor source electrode contact groove self aligned structure, aligned technical window of the contact grooves is effectively improved, and the product integrated level is improved.
Description
Technical field
The present invention relates to the technique manufacturing method realizing contact hole self-alignment structure in trench FET in a kind of semiconductor manufacturing, particularly relate to a kind of method utilizing the special etching technics on etching groove barrier layer to realize trench FET source contact groove self-alignment structure.
Background technology
Along with more and more higher to the requirement of integrated level, the distance between trench FET groove is also more and more less, so the alignment precision of source contact openings faces increasing challenge.In order to address this problem, technique mostly have employed the self aligned Structure and energy of source contact openings.
Wherein, the structural representation of existing two kinds of trench FETs as shown in Figure 1-2.Wherein, the first trench FET (as shown in Figure 1) has following feature:
1) gate polycrystalline silicon face is a lot of lower than surface of silicon;
2) groove becomes horn-like at surface of silicon opening part;
3) an interlayer dielectric layer oxide-film part is deep in silicon substrate;
4) source electrode implanted layer is darker;
5) contact groove and substantially there is no the part in interlayer dielectric layer oxide-film;
6) groove part is in a silicon substrate contacted darker.
The second trench FET (as shown in Figure 2) has following feature:
1) gate polycrystalline silicon face exceeds surface of silicon a lot, for formation sidewall protecting film structure; A lot of for allowing gate polycrystalline silicon face exceed surface of silicon, its technique is there is the enough thick oxide-film of one deck as stop-layer during gate polycrystalline silicon etching when gate polycrystalline silicon growth in surface of silicon;
2) utilize sidewall protecting film, complete contact groove part in a silicon substrate and realize self-alignment structure.
But the technique that realizes for self-alignment structure also has the leeway studied further.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method utilizing the special etching technics on etching groove barrier layer to realize trench FET source contact groove self-alignment structure.The method effectively can improve the Alignment Process window of contact groove, improves product integrated level.
For solving the problems of the technologies described above, the method (namely utilizing the special etching technics on etching groove barrier layer to realize the method for trench FET source contact groove self-alignment structure) realizing trench FET source contact groove self-alignment structure of the present invention, comprises step:
1) on a silicon substrate deposit first oxide-film as etching groove barrier layer;
2) etching groove barrier layer is etched, after forming bowl structure, then form groove with dry etching;
3) use conventional trench FET technological process to form grid oxidation film and grid polycrystalline silicon, then by dry etching, grid polycrystalline silicon is returned quarter to etching groove barrier layer surface;
4) etching selection ratio between grid polycrystalline silicon and etching groove barrier layer is utilized, use the position that is dry-etched in etching groove barrier layer and defines contact groove and be etched to and expose silicon substrate, then, by dry etching, output source contact groove on a silicon substrate;
5) deposit second oxide-film, to fill up source contact groove;
6) use wet etching that the second oxide-film is etched to gate polycrystalline silicon face;
7) use dry etching that grid polycrystalline silicon is etched to surface of silicon;
8) use dry etching that the oxide-film (comprising: the second oxide-film, grid oxidation film and the first oxide-film) of surface of silicon is etched to residue 150 ~ 250 dust;
9) conventional trench FET technological process perfect aspect implanted layer and source electrode implanted layer is used;
10) use conventional trench FET technological process to form interlayer dielectric layer, and utilize mask to define the part of source contact groove in interlayer dielectric layer;
11) metal barrier of conventional trench FET technological process formation source contact groove, tungsten plug and metal level is used.
In described step 1), the method for deposit comprises: Films Prepared by APCVD; The material of the first oxide-film comprises: silicon dioxide; The thickness on etching groove barrier layer (i.e. the first oxide-film) is 5000 ~ 6000 dusts, is preferably 5000 dusts.
Described step 2) in, the method for etching is: after first using wet etching 3000 ~ 3500 dust, then etches by the method for dry etching 2000 ~ 2500 dust; The bottom width of bowl structure depends on the design size to groove width on mask; The degree of depth of groove is 1.5 ~ 1.7 microns.
In described step 4), the degree of depth of source contact groove is 0.35 ~ 0.4 micron.
In described step 5), the method for deposit comprises: chemical gas-phase deposition method, as the method for low-pressure chemical vapor phase deposition and plasma enhanced CVD; The material of the second oxide-film comprises: silicon dioxide; The thickness requirement of the second oxide-film is greater than 1/2nd of groove width.
The present invention uses first wet method, the technique of rear dry etching etches etching groove barrier layer, forms bowl structure, thus uses self aligned technique to open needing the place of carving source contact groove when gate polycrystalline silicon etching, exposes substrate.Then, utilization is dry-etched in the place of exposing substrate and etches source contact groove, and the part of whole contact groove in interlayer dielectric layer and the part in silicon substrate are divided into different process and complete, thus realize trench FET self-aligned source contacts groove structure.
Therefore, method of the present invention effectively can improve the Alignment Process window of contact groove, improves product integrated level.Meanwhile, with existing self-registered technology unlike: do not need grid polycrystalline silicon to make that to exceed surface of silicon a lot of or lower than a lot of pattern of surface of silicon.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing a kind of trench FET;
Fig. 2 is the structural representation of existing another kind of trench FET;
Fig. 3 is the structural representation after deposition oxidation film;
Fig. 4 is the structural representation after forming groove;
Fig. 5 is the structural representation after grid polycrystalline silicon returns quarter;
Fig. 6 is the structural representation after outputing source contact groove;
Fig. 7 is that deposition oxidation film is to fill up the structural representation after source contact groove;
Fig. 8 is the structural representation after being etched to gate polycrystalline silicon face;
Fig. 9 is the structural representation after being etched to surface of silicon;
Figure 10 is the structural representation after being etched by the oxide-film of surface of silicon.
Figure 11 is the structural representation after perfect aspect implanted layer and source electrode implanted layer;
Figure 12 is the structural representation forming interlayer dielectric layer and define the part of source contact groove in interlayer dielectric layer;
Figure 13 is the structural representation after forming metal level.
In figure, description of reference numerals is as follows:
101 is silicon substrate, and 103 is groove, and 104 is contact groove, and 106 is grid oxidation film, and 107 is grid polycrystalline silicon, and 108 is body implanted layer, and 109 is source electrode implanted layer, and 110 is interlayer dielectric layer oxide-film, and 111 is metal barrier, and 112 is tungsten plug, and 113 is metal level;
201 is silicon substrate, and 203 is groove, and 204 is contact groove, and 206 is grid oxidation film, 207 is grid polycrystalline silicon, and 208 is body implanted layer, and 209 is source electrode implanted layer, and 210 is interlayer dielectric layer oxide-film, 211 is metal barrier, and 212 is tungsten plug, and 213 is metal level, and 214 is sidewall protecting film;
1 is silicon substrate, and 2 is etching groove barrier layer, and 3 is groove, and 4 is grid oxidation film, and 5 is grid polycrystalline silicon, 6 is source contact groove, and 7 is the second oxide-film, and 8 is body implanted layer, and 9 is source electrode implanted layer, 10 is interlayer dielectric layer, and 11 is metal barrier, and 12 is tungsten plug, and 13 is metal level.
Embodiment
The process utilizing the special etching technics on etching groove barrier layer to realize trench FET source contact groove self-alignment structure of the present invention, comprises step:
1) on silicon substrate 1, by method deposit first oxide-film (as silicon dioxide film) of normally used Films Prepared by APCVD as etching groove barrier layer 2(as shown in Figure 3);
Wherein, the thickness on etching groove barrier layer 2 is 5000 ~ 6000 dusts, is preferably 5000 dusts.
2) first by the method for dry etching 2000 ~ 2500 dust, etching groove barrier layer 2 is etched with after wet etching 3000 ~ 3500 dust, again, after forming bowl structure, then form groove 3(as shown in Figure 4 with dry etching);
Wherein, the bottom width of bowl structure depends on the design size to groove 3 width on mask; The degree of depth of groove is about 1.6 microns.
3) use conventional trench FET technological process to form grid oxidation film 4 and grid polycrystalline silicon 5, then by dry etching, grid polycrystalline silicon is carved to surface, etching groove barrier layer 2 (as shown in Figure 5) for 5 times;
4) etching selection ratio between grid polycrystalline silicon 5 and etching groove barrier layer 2 is utilized, use the position that is dry-etched in etching groove barrier layer 2 and defines contact groove and be etched to and expose silicon substrate 1, then, by dry etching, silicon substrate 1 is outputed source contact groove 6(as shown in Figure 6);
Wherein, the degree of depth of source contact groove 6 is 0.35 ~ 0.4 micron.
5) the good chemical gas-phase deposition method of step coverage is used, if the method deposit second oxide-film 7(of low-pressure chemical vapor phase deposition and plasma enhanced CVD is as silicon dioxide film), require the source contact groove 6 outputed on silicon substrate 1 to fill up (as shown in Figure 7);
Wherein, the thickness requirement of the second oxide-film 7 is greater than 1/2nd of groove width.
6) use wet etching that the second oxide-film 7 is etched to grid polycrystalline silicon 5 surface (as shown in Figure 8);
7) use dry etching that grid polycrystalline silicon 5 is etched to silicon substrate 1 surface (as shown in Figure 9);
8) use dry etching that the oxide-film (comprising: the second oxide-film 7, grid oxidation film 4 and the first oxide-film) on silicon substrate 1 surface is etched to residue 150 ~ 250 dust, as 200 dusts (as shown in Figure 10);
9) conventional trench FET technological process perfect aspect implanted layer 8 and source electrode implanted layer 9(is used as shown in figure 11);
10) conventional trench FET technological process is used to form interlayer dielectric layer 10, and utilizing mask to define the part of source contact groove 6 in interlayer dielectric layer 10 (as shown in figure 12), this part only source contact groove 6 that is guaranteed and that output on silicon substrate 1 is in advance connected and can ensures its electrology characteristic.Therefore, the Alignment Process window of this layer can be expanded;
11) metal barrier 11 of conventional trench FET technological process formation source contact groove 6, tungsten plug 12 and metal level 13(is used as shown in figure 13).
According to top method, utilize and etching groove barrier layer 2 is etched, made bowl structure, and utilize grid polycrystalline silicon 5 to do etching barrier layer on silicon substrate 1, to do self aligned etching to source electrode groove, thus effectively can expand the Alignment Process window of source contact groove 6 when interlayer dielectric layer 10 etches, process integration is provided.
The self-alignment structure that the present invention is final and existing self-registered technology unlike: do not need grid polycrystalline silicon 5 to make that to exceed silicon substrate 1 surface a lot of or lower than a lot of pattern in silicon substrate 1 surface, meanwhile, the part of whole contact groove in interlayer dielectric layer 10 and the part in silicon substrate 1 are divided into different process and complete.
Claims (7)
1. realize a method for trench FET source contact groove self-alignment structure, it is characterized in that, comprise step:
1) on a silicon substrate deposit first oxide-film as etching groove barrier layer;
2) etching groove barrier layer is etched, after forming bowl structure, then form groove with dry etching;
3) form grid oxidation film and grid polycrystalline silicon, then by dry etching, grid polycrystalline silicon is returned quarter to etching groove barrier layer surface;
4) etching selection ratio between grid polycrystalline silicon and etching groove barrier layer is utilized, use the position that is dry-etched in etching groove barrier layer and defines contact groove and be etched to and expose silicon substrate, then, by dry etching, output source contact groove on a silicon substrate;
5) deposit second oxide-film, to fill up source contact groove;
6) use wet etching that the second oxide-film is etched to gate polycrystalline silicon face;
7) use dry etching that grid polycrystalline silicon is etched to surface of silicon;
8) use dry etching that the oxide-film of surface of silicon is etched to residue 150 ~ 250 dust;
Wherein, oxide-film comprises: the second oxide-film, grid oxidation film and the first oxide-film;
9) perfect aspect implanted layer and source electrode implanted layer;
10) form interlayer dielectric layer, and utilize mask to define the part of source contact groove in interlayer dielectric layer;
11) metal barrier of source contact groove, tungsten plug and metal level is formed.
2. the method for claim 1, is characterized in that: in described step 1), and the method for deposit comprises: Films Prepared by APCVD;
The material of the first oxide-film comprises: silicon dioxide;
The thickness on etching groove barrier layer is 5000 ~ 6000 dusts.
3. method as claimed in claim 2, is characterized in that: the thickness on described etching groove barrier layer is 5000 dusts.
4. the method for claim 1, is characterized in that: described step 2) in, the method for etching is: after first using wet etching 3000 ~ 3500 dust, then etches by the method for dry etching 2000 ~ 2500 dust;
The bottom width of bowl structure depends on the design size to groove width on mask;
The degree of depth of groove is 1.5 ~ 1.7 microns.
5. the method for claim 1, is characterized in that: in described step 4), and the degree of depth of source contact groove is 0.35 ~ 0.4 micron.
6. the method for claim 1, is characterized in that: in described step 5), and the method for deposit comprises: chemical gas-phase deposition method;
The material of the second oxide-film comprises: silicon dioxide;
The thickness requirement of the second oxide-film is greater than 1/2nd of groove width.
7. method as claimed in claim 6, is characterized in that: the method for described deposit is the method for low-pressure chemical vapor phase deposition and plasma enhanced CVD.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022100412A1 (en) * | 2020-11-12 | 2022-05-19 | 重庆万国半导体科技有限公司 | Trench power device and manufacturing method therefor |
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| US20120135573A1 (en) * | 2010-11-29 | 2012-05-31 | Hynix Semiconductor Inc. | Method for manufacturing vertical transistor having one side contact |
| CN102779750A (en) * | 2012-04-23 | 2012-11-14 | 上海先进半导体制造股份有限公司 | Manufacturing method of trench insulated gate bipolar transistor (TIGBT) |
| CN103137687A (en) * | 2011-11-25 | 2013-06-05 | 上海华虹Nec电子有限公司 | Structure of groove type power metal oxide semiconductor (MOS) transistor and manufacture method thereof |
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| CN101645457A (en) * | 2008-08-08 | 2010-02-10 | 万国半导体股份有限公司 | Super-self-aligned trench-dmos structure and method |
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