CN104733369A - Method for eliminating silicon substrate defect in STI process - Google Patents
Method for eliminating silicon substrate defect in STI process Download PDFInfo
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- CN104733369A CN104733369A CN201310705772.0A CN201310705772A CN104733369A CN 104733369 A CN104733369 A CN 104733369A CN 201310705772 A CN201310705772 A CN 201310705772A CN 104733369 A CN104733369 A CN 104733369A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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Abstract
The invention provides a method for eliminating a silicon substrate defect in the STI process. The method includes the following steps that a silicon substrate is provided and is sequentially covered with an oxide layer and a silicon nitride layer, wherein the silicon substrate has the defect; the silicon nitride layer is etched until the surface of the oxide layer is exposed, and then a first trough is formed; the oxide layer is etched along the first trough until the silicon substrate is exposed, and then a second trough is formed; the silicon substrate is etched along the first trough and the second trough until the defect is exposed, and then a third trough is formed; the exposed defect is etched along the first trough, the second trough and the third trough and is eliminated; the silicon substrate is etched along the first trough, the second trough and the third trough, and finally etching on an STI area is completed. According to the method, the defect in the silicon substrate is etched independently, so a defect is prevented from being formed in the isolation trough, the electricity leakage phenomenon in the STI process is lightened, and an isolation effect meeting requirements can be achieved.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, particularly relate to a kind of method eliminating silicon base defect in shallow trench isolation process.
Background technology
Along with the development of ic manufacturing technology, semiconductor process techniques enters deep sub-micron era, and chip integration constantly promotes, and in chip, therefore the size of element also constantly reduces.But no matter how component size reduces, in chip, each element still must have suitable insulation or isolation, the element function that guarantee is good.When components and parts characteristic line breadth narrows down to less than 0.25 micron and even after entering the nanometer stage, traditional native oxide isolation technology (LOCOS) is owing to can not adapting to device electrical characteristic and undersized requirement and being replaced by shallow trench isolation technology (STI).The area of STI technology strict guarantee device active region, improves minimum isolating partition and junction capacitance; Channel isolation technology adopts low temperature process increase yield simultaneously, reduces production cost.Plurality of advantages makes STI technology become the indispensable isolation technology of deep sub-micron era device.
Although channel isolation technology insulation is effective, and area occupied is little.But channel isolation also exists many technical problems in technique realizes, as the control of raceway groove pattern, STI often produce various defects etc. to leakage current in very responsive and STI etching process in channels.And in existing semiconductor fabrication process, the monocrystalline silicon piece as silicon base is cut by the single crystal ingot of silicon and forms through the physical and chemical process of series of complex and Technology for Heating Processing manufacture.The grown-in defect (COP) having empty type is found in the monocrystalline silicon that the method produces.For large diameter pulling of crystals silicon chip, the size of usual this microdefect is below 0.12 micron, and the existence of this microdefect often becomes the key factor affecting ic yield.As easily produced as taper shape (Cone) defect because the existence of COP defect makes STI etch the groove formed in shallow trench isolation etching process.As shown in Figure 1, expression is a Cone defect plane graph amplified under an electron microscope.
By the Cone Defect Scanning of laser scanner to different wafer in the same batch products after STI etching in experiment, observe scanning distribution map known, different product Cone defect distribution after STI etching of same batch is almost identical; By the COP Defect Scanning of bright field inspection instrument to the different monocrystalline silicon pieces of same batch.Observe its scanning distribution map to find, the distribution of COP defect is also almost identical; The distribution of contrast Cone defect distribution and COP defect is learnt, the distribution of Cone defect and the distribution of COP defect are almost as good as, and it is intensive all to have center, the feature that edge is sparse.Experimental result illustrates thus: COP defect is the basic reason causing Cone defect, and irrelevant with the factor such as other factors except COP defect except of product self or etching procedure board used.
Existing shallow trench isolation lithographic technique mainly comprises the processing step of following key: as shown in Figure 2, provides silicon base 21, there is COP defect in this silicon base, forms oxide layer 22, silicon nitride layer 23 successively from below to up on the surface of this silicon base.When utilizing thermal oxidation method to form oxide skin(coating) 22, because silicon substrate surface is oxidized, be present in the void-type defects of silicon base upper surface because it is exposed in oxygen, therefore infiltrate oxygen in cavity and be oxidized to silicon dioxide, define silicon dioxide defect 211 at silicon substrate surface; The photomask pattern etch nitride silicon layer 23 utilizing predefined good, forms groove 1 as shown in Figure 3; Recycling groove 1 is mask and along groove 1 etching oxidation layer 22, as shown in Figure 4, forms the groove 2 through groove 1; Then utilize groove 1 as mask and along through groove 1 and groove 2 etch silicon substrate 21, as shown in Figure 5, the etching gas used due to etching oxidation silicon and etch silicon is different, and the C of etching oxidation silicon, F compound gas can not etch silicon, and the etching gas of silicon can not etching oxidation silicon.Therefore, the void-type defect (being of a size of more than 0.05 micron) that silicon base 21 surface is oxidized can not be removed, and this defect blocks the continuation etching of silicon below it further, in silicon base, thus define a taper defect (Cone) 212.The place not having defect to stop is etched, and forms the isolated groove 3 through groove 1 and groove 2, so far completes the etching procedure of shallow trench isolation.Be received in insulating material in the groove 3 formed after etching, object is the insulation effect in order to reach in active area between device.And the existence of Cone defect, make silicon in isolated groove not by Ex-all, silicon can conduct electricity with the device of active area, forms leaky.
In current existing making technology, solve STI and not very good method to the problem of leakage sensitive, the difficulty therefore affecting ic yield is also difficult to be overcome.
Given this, be necessary that proposing a kind of new method solves above-mentioned technical problem.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of method eliminating silicon base defect in shallow trench isolation process, for solving the problem of taper defect (Cone defect) in shallow trench isolation etching process in prior art, thus solve the leaky in shallow trench isolation process.
For achieving the above object and other relevant objects, the invention provides a kind of method eliminating silicon base defect in shallow trench isolation process, it is characterized in that, the method comprises the following steps:
(1) silicon base is provided, forms oxide skin(coating) and silicon nitride layer successively at this silicon base upper surface, wherein contain defect oxide in silicon base;
(2) utilize photomask pattern as mask, described silicon nitride layer is etched, until expose oxide skin(coating) upper surface, thus form the first groove in described silicon nitride layer;
(3) utilize the first groove as hard mask, along described first groove, etching is continued to described oxide skin(coating), until expose silicon base, thus form the second groove with the first grooves extend;
(4) utilize the first groove as hard mask, along described the first through groove and the second groove, etching is continued to described silicon base, to defect exposes, form the 3rd groove with the second grooves extend;
(5) utilize the first groove as hard mask, along described the first through groove, the second groove and the 3rd groove, by the mode of etching oxide defect, the defect oxide exposed is eliminated;
(6) utilize the first groove as hard mask, along described the first through groove, the second groove and the 3rd groove, continuation etching is carried out to described silicon base, until finally complete the etching of shallow trench isolation regions, form the 4th groove.
Preferably, described oxide skin(coating) and defect oxide comprise silicon dioxide.
Preferably, described silicon substrate material is monocrystalline silicon.
Preferably, the defect oxide contained in described silicon base infiltrates by silicon dioxide the void-type defect inside being positioned at monocrystalline silicon top layer to be formed.
Preferably, in described step (2) to (6), lithographic method adopts dry etching.
Preferably, described dry etching comprises reactive ion etching method.
Preferably, the gas that etch silicon nitride is used comprises CF
4, SF
6in one or both; Etching silicon dioxide gas used comprises CF
4, CHF
3in one or both.
Preferably, the gas that etch silicon substrate is used comprises HBr, SF
6, CL
2in one or more combination.
Preferably, the etching depth of described 3rd groove is 90nm ~ 120nm.
Preferably, in described silicon base, the diameter of defect oxide is 0.1 micron ~ 0.14 micron.
As mentioned above, the method of silicon base defect in elimination shallow trench isolation process provided by the invention, there is following beneficial effect: overcome the inner difficulty being caused producing taper defect by COP defect of raceway groove in shallow trench isolation etching process, thus solve the leaky caused by defect in shallow trench isolation etching process, make to reach good isolation effect between the device of active area.
Accompanying drawing explanation
Fig. 1 is shown as a Cone defect plane graph amplified under an electron microscope of the prior art.
Fig. 2 to Fig. 5 is shown as the operation schematic diagram of shallow trench isolation etching process of the prior art.
Fig. 6 is shown as the schematic flow sheet that the present invention eliminates the method for silicon base defect in shallow trench isolation process.
Fig. 7 is shown as the operation schematic diagram of the method for silicon base defect in elimination shallow trench isolation process of the present invention as Figure 13 b.
Element numbers explanation
21,71 silicon base
22,72 oxide skin(coating)s
23,73 silicon nitride layers
211,711 silicon dioxide defects
1,10,2,11,3,13 grooves
212 taper defects
712 exposed defects
713 incomplete exposed defects
714 residue defects
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Figure 13 b.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.Do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate that the present invention is the problem how solving the leaky caused by defect in shallow trench isolation etching process in prior art.Obviously, enforcement of the present invention does not limit the specific details that semiconductor applications technical staff has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
As shown in Figure 6, in described elimination shallow trench isolation process, the method for silicon base defect at least comprises step S11 to step S16.Step S11: provide a silicon base, forms oxide skin(coating) and silicon nitride layer successively at this silicon base upper surface, wherein contains defect oxide in silicon base.As shown in Figure 7, in the present embodiment, the material of described silicon base 71 is monocrystalline silicon, and there is the grown-in defect (COP defect) of empty type in monocrystalline silicon 71.When silicon base made by monocrystalline silicon, need the thin slice cutting into precise geometrical size, the part COP defect being now present in monocrystalline silicon top layer can come out because of cutting, also has the COP defect on some top layers then not come out.As shown in Figure 7, when monocrystalline silicon surface forms oxide skin(coating) 72, the defect exposed because of cutting and the COP defect inside being positioned at top can be infiltrated oxygen thus be oxidized to silicon dioxide, become the defect oxide being present in silicon base upper surface, i.e. silicon dioxide defect 711.For convenience of description, the COP defect being positioned at monocrystalline silicon other positions inner is not provided in figure.The method forming oxide skin(coating) 72 adopts thermal oxidation method, and oxide skin(coating) 72 is stained as separator protection active area from chemistry in the process removing nitride.The silicon chip comprising oxide skin(coating) 72 is put into high-temperature low-pressure chemical gaseous phase equipment, in the cavity of equipment, ammonia and dichlorosilane react, and generate silicon nitride layer 73 at described oxide skin(coating) 72 upper surface.Silicon nitride layer 73 has two effects in STI process: 1) silicon nitride can be used as the hard mask material of etching; 2) silicon nitride serves as barrier layer in chemical mechanical planarization process.
Step S12: utilize photomask pattern as mask, etches described silicon nitride layer 73, until expose oxide skin(coating) upper surface, thus forms the first groove 10 in described silicon nitride layer 73.Described photomask pattern is existing mask pattern.Lithographic method well known to those skilled in the art can be adopted, the reactive ion etching method (RIE) namely in dry etching to the lithographic method of silicon nitride layer 73.Reacting gas comprises CF
4or SF
6in one or both combination.The reacting gas used in the present embodiment is CF
4.The principle of RIE etching is: reacting gas enters in plasma chamber, ionization under the effect of extra electric field, the activated group produced after reacting gas ionization and the material generation chemical reaction that is etched, and generates the object that escaping gas reaches etch silicon nitride.Except there is chemical reaction, be with during the Ions Bombardment material surface of energy and also physical sputtering can occur, so also can play certain corrasion.Reactive ion etching is the combination that physical etchings and chemical reaction etch.The degree of depth that the method for gas timing under certain flow velocity etches to control silicon nitride layer 73 is adopted in the present embodiment.Experimental result shows, and etch nitride silicon layer 73 time used is about 40 seconds.As shown in Figure 8, the first groove 10 is formed after etching.
Step S13: utilize the first groove 10 as hard mask, continues etching along described first groove 10 to described oxide skin(coating) 72, until expose silicon base 71, thus forms the second groove 11 with the first grooves extend.This oxide skin(coating) 72 is silicon dioxide, and etching oxidation nitride layer 72 principle used is identical with etch silicon nitride with method, also adopts ion reaction etching method.The reacting gas used unlike, etching oxidation nitride layer comprises CF
4or CHF
3in one or both combination.The etching gas used in the present embodiment is CF
4.Etching oxidation nitride layer 72 time used is about 40 seconds.As shown in figure 11, the second groove 11 is formed after etching.
Then implementation step S14: utilize the first groove as hard mask, continues etching along described the first through groove and the second groove to described silicon base, to defect exposes, forms the 3rd groove 12 with the second grooves extend.Because the COP defect of silicon face is oxidized to oxide, form silicon dioxide defect.Etch silicon etching gas used comprises HBr, SF
6, CL
2in one or more combination, use HBr etch silicon in the present embodiment.As shown in figure 11, because HBr can not etching silicon dioxide, therefore after HBr etch silicon, silicon dioxide defect 711 is exposed and forms exposed defect 712, forms the 3rd groove 12 simultaneously.Generally, the size of COP defect is at 0.12 micron and following, and more than the 0.12 micron probability existed almost is less than one thousandth.So the diameter of defect oxide in the present embodiment and silicon dioxide defect is 0.1 micron to 0.14 micron.Show according to experimental result: exposure diameter is the silicon dioxide defect etch period used of 0.1 micron to 0.14 micron is 30 seconds ~ 40 seconds.Due to the octahedral structure of lattice in silicon crystal, it just can be that the defect of 0.1 micron to 0.14 micron comes out by diameter that the degree of depth of silicon etching reaches 90nm ~ 120nm.It should be noted that: " exposure " of this step indication refers to that defect exposes completely or major part exposes.As depicted in fig. 13 a, incomplete exposed defect 713 also has small part not to be exposed.The size of this defect remainder is below 0.05 micron, and this part defect do not exposed can along with the etching ion sputtering of silicon etches away remaining silicon dioxide defect in the operation of subsequent etching silicon.
Step S15: utilize the first groove as hard mask, along described the first through groove, the second groove and the 3rd groove, makes the defect oxide exposed be eliminated by the mode of etching oxide defect.Described oxide is silicon dioxide, and the etching principle that in the present embodiment, this step adopts with etching oxidation nitride layer in step S13 is identical with etching gas, and etching gas is CF
4.Unlike the exposed part that the etching object of this step is in the exposed defect 712 in step S14 or incomplete exposed defect 713 as depicted in fig. 13 a.Incomplete exposed defect expose portion is of a size of 0.05 micron ~ 0.14 micron, and etching required time is about 15 seconds ~ 20 seconds.As shown in figure 11 be remove the raceway groove schematic diagram after exposed defect; What Figure 13 b represented is the schematic diagram that the residue defect 714 of size below 0.05 micron is not etched out.
Step S16: utilize the first groove as hard mask, carries out continuation etching along described the first through groove, the second groove and the 3rd groove to described silicon base, until finally complete the etching of shallow trench isolation regions, forms the 4th groove.This step adopts and continues etch silicon substrate with etching gas HBr identical in step S14.For the situation that the defect shown in Figure 11 is completely removed, the activated group utilizing HBr to produce in ion chamber directly and pasc reaction carry out etch silicon substrate; For the situation of the also remaining a small amount of silicon dioxide residue defect 714 of the silicon substrate surface shown in Figure 13 b, although HBr produce activated group can not with silicon dioxde reaction, but the ion of the band energy produced after etching gas ionization can bombard silicon dioxide residue defect 714 and physical sputtering occurs, and is enough to remove the residue defect remained in silicon.The etching principle of residue defect 714 is different from the ion chemistry reactive ion etching principle in above each step, but utilizes the etching principle of physical sputtering to remove residue defect.As shown in figure 12, till being finally etched to the required STI degree of depth, the groove 13 of formation.In the present embodiment, this step etch silicon substrate time used is 50 seconds ~ 70 seconds.
In sum, the invention solves the inner problem being caused producing taper defect by COP defect of raceway groove in shallow trench isolation etching process.So the present invention effectively overcomes the leaky caused by defect in shallow trench isolation etching process in prior art, make to reach good isolation effect between the device of active area, improve and manufacture the rate of finished products of integrated circuit, thus have a high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (11)
1. eliminate a method for silicon base in shallow trench isolation etching process, it is characterized in that, the method comprises the following steps:
(1) silicon base is provided, forms oxide skin(coating) and silicon nitride layer successively at this silicon base upper surface, wherein contain defect oxide in silicon base;
(2) utilize photomask pattern as mask, described silicon nitride layer is etched, until expose oxide skin(coating) upper surface, thus form the first groove in described silicon nitride layer;
(3) utilize the first groove as hard mask, along described first groove, etching is continued to described oxide skin(coating), until expose silicon base, thus form the second groove with the first grooves extend;
(4) utilize the first groove as hard mask, along described the first through groove and the second groove, etching is continued to described silicon base, to defect exposes, form the 3rd groove with the second grooves extend;
(5) utilize the first groove as hard mask, along described the first through groove, the second groove and the 3rd groove, by the mode of etching oxide defect, the defect oxide exposed is eliminated;
(6) utilize the first groove as hard mask, along described the first through groove, the second groove and the 3rd groove, continuation etching is carried out to described silicon base, until finally complete the etching of shallow trench isolation regions, form the 4th groove.
2. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 1, is characterized in that: described oxide skin(coating) and defect oxide comprise silicon dioxide.
3. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 1, is characterized in that: described silicon substrate material is monocrystalline silicon.
4. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 3, is characterized in that: the defect oxide contained in described silicon base infiltrates by silicon dioxide the void-type defects inside being positioned at monocrystalline silicon top layer to be formed.
5. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 1, is characterized in that: described step adopts dry etching to middle lithographic method.
6. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 5, is characterized in that: described dry etching comprises reactive ion etching method.
7. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 2, is characterized in that: etch nitride silicon layer gas used comprises CF
4, SF
6in one or both; Etching silicon dioxide gas used comprises CF
4, CHF
3in one or both.
8. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 3, is characterized in that: etch silicon substrate gas used comprises HBr, SF
6, CL
2in one or more combination.
9. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 1, is characterized in that: the etching depth of described 3rd groove is 90nm ~ 120nm.
10. the method for silicon base defect in elimination shallow trench isolation etching process according to claim 1, is characterized in that: in described silicon base, the diameter of defect oxide is 0.1 micron ~ 0.14 micron.
The method of silicon base defect in 11. elimination shallow trench isolation etching processes according to claim 1, is characterized in that: the defect in described step exposes and comprises incomplete exposure, and does not have expose portion to be of a size of less than 0.05 micron.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281093B1 (en) * | 2000-07-19 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce trench cone formation in the fabrication of shallow trench isolations |
| US6890859B1 (en) * | 2001-08-10 | 2005-05-10 | Cypress Semiconductor Corporation | Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby |
| CN102610551A (en) * | 2011-10-13 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing shallow trench isolation defects |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281093B1 (en) * | 2000-07-19 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce trench cone formation in the fabrication of shallow trench isolations |
| US6890859B1 (en) * | 2001-08-10 | 2005-05-10 | Cypress Semiconductor Corporation | Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby |
| CN102610551A (en) * | 2011-10-13 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing shallow trench isolation defects |
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