CN104733369B - A kind of method for eliminating silicon base defect in shallow trench isolation etching process - Google Patents
A kind of method for eliminating silicon base defect in shallow trench isolation etching process Download PDFInfo
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- CN104733369B CN104733369B CN201310705772.0A CN201310705772A CN104733369B CN 104733369 B CN104733369 B CN 104733369B CN 201310705772 A CN201310705772 A CN 201310705772A CN 104733369 B CN104733369 B CN 104733369B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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Abstract
The present invention provides a kind of method for eliminating silicon base defect in shallow trench isolation etching process, and this method comprises the following steps：A silicon base is provided, successively covered with oxide skin(coating) and silicon nitride layer in the silicon base, wherein silicon base is containing defective；Silicon nitride layer is performed etching untill oxide layer surface is exposed, forms first groove；Oxide skin(coating) is etched to untill exposing silicon base along first groove, forms second groove；Silicon base is etched to untill defect exposes along first groove and second groove, forms the 3rd groove；Along first groove, second groove and the 3rd groove to exposing the defects of perform etching and be eliminated it；Silicon base is etched along first groove, second groove and the 3rd groove, is finally completed the etching of shallow trench isolation regions.The present invention passes through the independent etching to defect in silicon base, it is therefore prevented that the formation of defect in isolated groove, reduces the leaky during shallow trench isolation, reaches satisfactory isolation effect.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, more particularly to silicon base during one kind elimination shallow trench isolation
The method of defect.
Background technology
With the continuous development of ic manufacturing technology, semiconductor process technique comes into deep sub-micron era, core
Piece integrated level is constantly lifted, and in chip therefore the size of element also constantly reduces.But no matter how component size reduces, chip
In each element still have to appropriate insulation or isolation, just can guarantee that good element function.When component characteristic line breadth contracts
Small to less than 0.25 micron so enter the nanometer stage after, traditional native oxide isolation technology (LOCOS) is not due to adapting to
The requirement of device electrical characteristic and small size and by shallow trench isolation technology (STI) substitute.STI technique strict guarantee device has
The area of source region, improve minimum isolating partition and junction capacity；Channel isolation technology is using low temperature process increase yield, drop simultaneously
Low production cost.Plurality of advantages makes STI technique turn into the indispensable isolation technology of deep sub-micron era device.
Although channel isolation technology insulation effect is good, and area occupied is small.But channel isolation is in technique realization
Many technical problems be present, the control, STI such as raceway groove pattern is extremely sensitive to leakage current and STI etching processes in often
The defects of various etc. is produced in channels.And in existing semiconductor fabrication process, the monocrystalline silicon piece as silicon base is
Cut by the single crystal ingot of silicon and pass through the physical and chemical process of a series of complex and Technology for Heating Processing is fabricated.The method system
Discovery there are the grown-in defect (COP) of empty type in the monocrystalline silicon produced.For the pulling of crystals silicon chip of major diameter,
The size of usual this microdefect is below 0.12 micron, and the presence of this microdefect often turns into influence integrated circuit finished product
The key factor of rate.Because the presence of COP defects causes STI to etch the groove to be formed and hold such as in shallow trench isolation etching process
It is also easy to produce such as taper shape (Cone) defect.As shown in figure 1, what is represented is that the Cone amplified under an electron microscope a defect is put down
Face figure.
The Cone defects of different wafers are swept in same batch products after being etched in experiment by laser scanner to STI
Retouch, observation scanning distribution map understands that the different product of the same batch Cone defect distributions after STI is etched are almost identical；It is logical
Cross COP Defect Scanning of the bright field inspection instrument to the different monocrystalline silicon pieces of same batch.Its scanning distribution graph discovery is observed, COP is lacked
Sunken distribution is also almost identical；The distribution of contrast Cone defect distributions and COP defects learns that the distribution of Cone defects and COP are lacked
Sunken distribution is almost no different, and all has the characteristics of center is intensive, and edge is sparse.Thus experimental result explanation：COP defects are
Cause the basic reason of Cone defects, and with other factors of the product itself in addition to COP defects or etching procedure used in machine
The factors such as platform are unrelated.
Existing shallow trench isolation lithographic technique mainly includes following crucial processing step：As shown in Figure 2, there is provided
Silicon base 21, COP defects be present in the silicon base, sequentially form oxide layer 22, nitridation from below to up on the surface of the silicon base
Silicon layer 23.When forming oxide skin(coating) 22 using thermal oxidation method, because silicon substrate surface is oxidized, it is present in silicon base upper surface
Void-type defects are because its is exposed in oxygen, therefore oxygen is penetrated into cavity and is oxidized to silica, in silicon base
Surface forms silica defect 211；Using the good photomask pattern etch nitride silicon layer 23 of predefined, such as Fig. 3 is formed
Shown groove 1；Groove 1 is recycled for mask and along the etching oxidation layer 22 of groove 1, as shown in figure 4, being formed through groove 1
Groove 2；Silicon base 21 is etched followed by groove 1 as mask and along the groove 1 and groove 2 of insertion, as shown in figure 5, by
Different with the etching gas used in etching silicon in etching oxidation silicon, C, the F compound gas of etching oxidation silicon can not etch silicon,
And the etching gas of silicon are unable to etching oxidation silicon.Therefore, (size is for the surface of silicon base 21 has been oxidized void-type defect
More than 0.05 micron) it can not be removed, the defect further blocks silicon below and continues to etch, thus the shape in silicon base
Into a taper defect (Cone) 212.The place for not having defect to stop is etched, formed through groove 1 and groove 2 every
From the etching procedure of groove 3, so far completion shallow trench isolation.Insulating materials is received in the groove 3 formed after etching, it is therefore an objective to
In order to reach the insulation effect in active area between device.And the presence of Cone defects so that silicon in isolated groove not by except
Only, silicon can occur conductive with the device of active area, form leaky.
In current existing making technology, solve the problems, such as that STI does not have very good method to leakage sensitive, because
This difficulty for influenceing ic yield is also difficult to be overcome.
In consideration of it, it is necessary to propose a kind of new method to solve above-mentioned technical problem.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide one kind to eliminate shallow trench isolation process
The method of middle silicon base defect, for solving taper defect (Cone defects) in shallow trench isolation etching process in the prior art
Problem, so as to solve the leaky during shallow trench isolation.
In order to achieve the above objects and other related objects, the present invention provides a kind of silicon base during eliminating shallow trench isolation
The method of defect, it is characterised in that this method comprises the following steps：
(1) silicon base is provided, oxide skin(coating) and silicon nitride layer, wherein silicon base are sequentially formed in the silicon base upper surface
In contain defect oxide；
(2) by the use of photomask pattern as mask, the silicon nitride layer is performed etching, until exposing on oxide skin(coating)
Surface, so as to form first groove in the silicon nitride layer；
(3) by the use of first groove as hard mask, the oxide skin(coating) is continued to etch along the first groove, until sudden and violent
Expose silicon base, so as to form the second groove with first groove insertion；
(4) by the use of first groove as hard mask, along the first groove and second groove of the insertion to the silicon base
Continue to etch, untill defect exposes, form the 3rd groove with second groove insertion；
(5) by the use of first groove as hard mask, along the first groove of the insertion, second groove and the 3rd groove, use
The defect oxide that the mode of etching oxide defect makes to expose is eliminated；
(6) by the use of first groove as hard mask, along the first groove of the insertion, second groove and the 3rd groove to institute
State silicon base to carry out continuing to etch, untill being finally completed the etching of shallow trench isolation regions, form the 4th groove.
Preferably, the oxide skin(coating) and defect oxide include silica.
Preferably, the silicon substrate material is monocrystalline silicon.
Preferably, the defect oxide contained in the silicon base is that the sky positioned at monocrystalline silicon top layer is penetrated into by silica
Hole type defect is internally formed.
Preferably, the step (2) lithographic method into (6) uses dry etching.
Preferably, the dry etching includes reactive ion etching method.
Preferably, the gas used in etch silicon nitride includes CF4、SF6One or both of；Used in etching silicon dioxide
Gas include CF4、CHF3One or both of.
Preferably, etching the gas used in silicon base includes HBr, SF6、CL2In one or more combination.
Preferably, the etching depth of the 3rd groove is 90nm~120nm.
Preferably, a diameter of 0.1 micron~0.14 micron of defect oxide in the silicon base.
As described above, the method provided by the invention for eliminating silicon base defect during shallow trench isolation, having following has
Beneficial effect：Overcome is caused the difficulty of generation taper defect by COP defects inside raceway groove in shallow trench isolation etching process, so as to
Solve the leaky as caused by defect in shallow trench isolation etching process, make to reach good isolation between active area device
Effect.
Brief description of the drawings
Fig. 1 is shown as the one of the prior art Cone amplified under an electron microscope defect plan.
Fig. 2 to Fig. 5 is shown as the process schematic diagram of shallow trench isolation etching process of the prior art.
Fig. 6 be shown as the present invention eliminate shallow trench isolation during silicon base defect method schematic flow sheet.
Fig. 7 as Figure 13 b be shown as the present invention elimination shallow trench isolation during silicon base defect method process
Schematic diagram.
Component label instructions
21st, 71 silicon base
22nd, 72 oxide skin(coating)
23rd, 73 silicon nitride layer
211st, 711 silica defect
1st, 10,2,11,3,13 groove
212 taper defects
712 exposed defects
713 incomplete exposed defects
714 remaining defects
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1 to Figure 13 b.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way
The basic conception of the present invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.In the case where not influenceing the effect of present invention can be generated and the purpose that can reach,
Should still it fall in the range of disclosed technology contents are obtained and can covered.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to illustrate the present invention be as
What solves the problems, such as the leaky as caused by defect in shallow trench isolation etching process in the prior art.Obviously, it is of the invention
Implementation does not limit the specific details that semiconductor applications technical staff is familiar with.Presently preferred embodiments of the present invention is described in detail such as
Under, but in addition to these detailed descriptions, the present invention can also have other embodiment.
As shown in fig. 6, the method for silicon base defect comprises at least step S11 to step during the elimination shallow trench isolation
Rapid S16.Step S11：One silicon base is provided, oxide skin(coating) and silicon nitride layer, wherein silicon are sequentially formed in the silicon base upper surface
Contain defect oxide in substrate.As shown in fig. 7, in the present embodiment, the material of the silicon base 71 is monocrystalline silicon, and monocrystalline
The grown-in defect (COP defects) of empty type in silicon 71 be present., it is necessary to cut into precise geometrical chi when silicon base is made in monocrystalline silicon
Very little thin slice, being now present in the part COP defects on monocrystalline silicon top layer can be exposed because of cutting, also have some top layers
COP defects are not exposed then.As shown in fig. 7, when monocrystalline silicon surface forms oxide skin(coating) 72, exposed because of cutting
Defect and positioned at top COP defects inside can be infiltrated oxygen so as to be oxidized to silica, turn into and be present in silicon base
The defect oxide of upper surface, i.e. silica defect 711.For convenience of description, it is not provided inside the monocrystalline silicon in figure
The COP defects of his position.The method for forming oxide skin(coating) 72 uses thermal oxidation method, and oxide skin(coating) 72 will be used as separation layer protection to have
Source region stains during nitride is removed from chemistry.Silicon chip including oxide skin(coating) 72 is put into high-temperature low-pressure chemistry gas
In phase equipment, ammonia reacts with dichlorosilane in the cavity of equipment, generates and nitrogenizes in the upper surface of oxide skin(coating) 72
Silicon layer 73.Silicon nitride layer 73 has two effects during STI：1) silicon nitride can be as the hard mask material of etching；2) nitrogenize
Silicon serves as barrier layer in chemical mechanical planarization process.
Step S12：By the use of photomask pattern as mask, the silicon nitride layer 73 is performed etching, until exposing oxygen
Compound layer upper surface, so as to form first groove 10 in the silicon nitride layer 73.The photomask pattern is existing mask
Figure.Lithographic method well known to those skilled in the art can be used to the lithographic method of silicon nitride layer 73, i.e., in dry etching
Reactive ion etching method (RIE).Reacting gas includes CF4Or SF6One or both of combination.Used in the present embodiment
Reacting gas be CF4.RIE etching principle be：Reacting gas enter plasma chamber body in, in the presence of extra electric field from
Sonization, caused activated group chemically reacts with the material that is etched after reacting gas ionization, and generation escaping gas reaches
To the purpose of etch silicon nitride.Thing can also occur in addition to chemically reacting, during Ions Bombardment material surface with energy
Reason sputtering, can also so play certain corrasion.Reactive ion etching is the knot of physical etchings and chemical reaction etching
Close.The depth that silicon nitride layer 73 etches is controlled using the method for gas timing under certain flow velocity in the present embodiment.Experiment
As a result show, the time used in etch nitride silicon layer 73 is 40 seconds or so.As shown in figure 8, first groove 10 is formed after etching.
Step S13：By the use of first groove 10 as hard mask, the oxide skin(coating) 72 is continued along the first groove 10
Etching, until silicon base 71 is exposed, so as to form the second groove 11 with first groove insertion.The oxide skin(coating) 72 is dioxy
SiClx, the principle and method used in etching oxidation nitride layer 72 are identical with etch silicon nitride, also using ion reaction etching method.It is different
, the reacting gas used in etching oxidation nitride layer includes CF4Or CHF3One or both of combination.Used in the present embodiment
Etching gas be CF4.Time used in etching oxidation nitride layer 72 is 40 seconds or so.As shown in figure 11, second is formed after etching
Groove 11.
Then implementation steps S14：By the use of first groove as hard mask, along the first groove and second groove of the insertion
The silicon base is continued to etch, untill defect exposes, forms the 3rd groove 12 with second groove insertion.Due to silicon table
The COP defects in face are oxidized to oxide, form silica defect.Etching gas used in etching silicon include HBr, SF6、CL2
In one or more combination, etch silicon with HBr in the present embodiment.As shown in figure 11, because HBr is unable to etching silicon dioxide,
Therefore after HBr etching silicon, silica defect 711 is exposed to form exposed defect 712, while forms the 3rd groove 12.One
As in the case of, the size of COP defects is at 0.12 micron and its following, 0.12 micron present on probability almost be less than thousand/
One.So the defect oxide in the present embodiment is a diameter of 0.1 micron to 0.14 micron of silica defect.Factually test knot
Fruit shows：Etch period used in the silica defect of a diameter of 0.1 micron to 0.14 micron of exposure is 30 seconds~40 seconds.Due to
The octahedral structure of lattice in silicon crystal, the depth of silicon etching reaches 90nm~120nm can be by a diameter of 0.1 micron to 0.14
The defects of micron, is exposed.It should be noted that：The step signified " exposure " refers to that defect is completely exposed or major part is sudden and violent
Dew.As depicted in fig. 13 a, not exclusively exposed defect 713 also has small part not to be exposed.The size of the defect remainder
Below 0.05 micron, the defects of this part does not expose, can be in the process of subsequent etching silicon with the etching ion of silicon
Ise falls remaining silica defect.
Step S15：By the use of first groove as hard mask, along the first groove of the insertion, second groove and the 3rd ditch
Groove, the defect oxide for making to expose with the mode of etching oxide defect are eliminated.The oxide is silica, this reality
Apply and etch principle used by the step is with etching oxidation nitride layer in step S13 in example and etching gas are identical, etching gas are
CF4.The difference is that the etching object of the step is incomplete exposed for the exposed defect 712 in step S14 or as depicted in fig. 13 a
Exposed part in defect 713.The size of incomplete exposed defect expose portion is 0.05 micron~0.14 micron, needed for etching
Time is about 15 seconds~20 seconds.As shown in Fig. 11 the raceway groove schematic diagram after exposed defect is removed；What Figure 13 b were represented is size
The schematic diagram that remaining defect 714 below 0.05 micron is not etched.
Step S16：By the use of first groove as hard mask, along the first groove of the insertion, second groove and the 3rd ditch
Groove carries out continuing to etch to the silicon base, untill being finally completed the etching of shallow trench isolation regions, forms the 4th groove.Should
Step using with identical etching gas HBr in step S14 come continue etch silicon base.The defects of for shown in Figure 11, is complete
The situation of removing, using HBr, caused activated group is directly in ion chamber and pasc reaction etches silicon base；For Figure 13 b
The situation of the also remaining a small amount of silica residue defect 714 of shown silicon substrate surface, although activated group is not caused by HBr
Energy and silicon dioxde reaction, but the ion with energy caused by after etching gas ionization can bombard silica residue defect
714 occur physical sputtering, it is sufficient to remove the remaining defect remained in silicon.More than the etching principle of remaining defect 714 is different from
Ion chemistry reactive ion etching principle in each step, but remaining defect is removed using the etching principle of physical sputtering.Such as figure
Shown in 12, untill being finally etched to required STI depth, the groove 13 of formation.In the present embodiment, used in step etching silicon base
Time be 50 seconds~70 seconds.
In summary, the present invention is solved to cause to produce by COP defects inside raceway groove in shallow trench isolation etching process and bored
The problem of shape defect.So the present invention is effectively overcome in the prior art as caused by defect in shallow trench isolation etching process
Leaky, make to reach good isolation effect between active area device, improve the yield rate of manufacture integrated circuit, thus have
High industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (11)
- A kind of 1. method for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that this method includes following Step：(1) silicon base is provided, oxide skin(coating) and silicon nitride layer is sequentially formed in the silicon base upper surface, wherein contains in silicon base There is defect oxide；(2) by the use of photomask pattern as mask, the silicon nitride layer is performed etching, until exposing oxide skin(coating) upper table Face, so as to form first groove in the silicon nitride layer；(3) by the use of first groove as hard mask, the oxide skin(coating) is continued to etch along the first groove, until exposing Silicon base, so as to form the second groove with first groove insertion；(4) by the use of first groove as hard mask, the silicon base is continued along the first groove and second groove of the insertion Etching, untill defect exposes, form the 3rd groove with second groove insertion；(5) by the use of first groove as hard mask, along the first groove of the insertion, second groove and the 3rd groove, with etching The defect oxide that the mode of defect oxide makes to expose is eliminated；(6) by the use of first groove as hard mask, along the first groove of the insertion, second groove and the 3rd groove to the silicon Substrate carries out continuing to etch, and untill being finally completed the etching of shallow trench isolation regions, forms the 4th groove.
- 2. the method according to claim 1 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： The oxide skin(coating) and defect oxide include silica.
- 3. the method according to claim 1 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： The silicon substrate material is monocrystalline silicon.
- 4. the method according to claim 3 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： The defect oxide contained in the silicon base is to be penetrated into by silica in the void-type defects on monocrystalline silicon top layer What portion was formed.
- 5. the method according to claim 1 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： Lithographic method uses dry etching in the step.
- 6. the method according to claim 5 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： The dry etching includes reactive ion etching method.
- 7. the method according to claim 2 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： Gas used in etch nitride silicon layer includes CF4、SF6One or both of；Gas used in etching silicon dioxide includes CF4、 CHF3One or both of.
- 8. the method according to claim 3 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： Gas used in etching silicon base includes HBr, SF6、Cl2In one or more combination.
- 9. the method according to claim 1 for eliminating silicon base defect in shallow trench isolation etching process, it is characterised in that： The etching depth of 3rd groove is 90nm~120nm.
- 10. the method according to claim 1 for eliminating silicon base defect in shallow trench isolation etching process, its feature exist In：A diameter of 0.1 micron~0.14 micron of defect oxide in the silicon base.
- 11. the method according to claim 1 for eliminating silicon base defect in shallow trench isolation etching process, its feature exist In：The exposure of the defects of described step includes not exclusively exposure, and is less than 0.05 micron without the size of expose portion.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281093B1 (en) * | 2000-07-19 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce trench cone formation in the fabrication of shallow trench isolations |
| US6890859B1 (en) * | 2001-08-10 | 2005-05-10 | Cypress Semiconductor Corporation | Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby |
| CN102610551A (en) * | 2011-10-13 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing shallow trench isolation defects |
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- 2013-12-19 CN CN201310705772.0A patent/CN104733369B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281093B1 (en) * | 2000-07-19 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce trench cone formation in the fabrication of shallow trench isolations |
| US6890859B1 (en) * | 2001-08-10 | 2005-05-10 | Cypress Semiconductor Corporation | Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby |
| CN102610551A (en) * | 2011-10-13 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing shallow trench isolation defects |
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