CN100501938C - Method of protecting plow groove bottom in deep plow groove techniques - Google Patents

Method of protecting plow groove bottom in deep plow groove techniques Download PDF

Info

Publication number
CN100501938C
CN100501938C CNB2006101193914A CN200610119391A CN100501938C CN 100501938 C CN100501938 C CN 100501938C CN B2006101193914 A CNB2006101193914 A CN B2006101193914A CN 200610119391 A CN200610119391 A CN 200610119391A CN 100501938 C CN100501938 C CN 100501938C
Authority
CN
China
Prior art keywords
deep trench
layer
oxide layer
channel bottom
deep
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2006101193914A
Other languages
Chinese (zh)
Other versions
CN101202228A (en
Inventor
迟玉山
吕煜坤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CNB2006101193914A priority Critical patent/CN100501938C/en
Publication of CN101202228A publication Critical patent/CN101202228A/en
Application granted granted Critical
Publication of CN100501938C publication Critical patent/CN100501938C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

The invention discloses a method for protecting a groove bottom in a deep groove process. After a deep groove is formed, photo resistance or organic anti reflection coat material is adopted to fill into the groove. Then, in the process of adopting plasma to etch an oxide mask, a surface filling material layer and an upper oxide layer are removed and the filled materials can protect the groove bottom. In the end a plasma cineration method is adopted to remove the remnant filling materials. The invention can avoid the damages to deep groove bottom in deep groove process.

Description

The method of protection channel bottom in the deep trench processes
Technical field
The invention belongs to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to the method for protection channel bottom in a kind of deep trench processes.
Background technology
Integrated circuits such as bipolar tube often utilize deep groove structure to realize the isolation of certain depth.Existing deep trench processes generally comprises following a few step flow process:
1) utilize photoetching process to define required pattern to photoresist layer; 2) by technologies such as plasma etchings with the photoresist layer design transfer to the hard mask layers of below, this mask layer generally comprises oxide skin(coating), nitride and oxide skin(coating) from top to bottom; 3) utilize method such as plasma ashing to remove the residual light resistance layer; 4) utilize hard mask layers as mask, prepare deep groove structure by plasma etching industrial; 5) utilize plasma etching industrial to remove the upper strata residual oxide layer.
Wherein, the 5th) go on foot in the flow process, plasma process can cause certain damage to the deep trench bottom simultaneously in the process of removing the remaining oxide-film in upper strata, and it comprises effects such as chemical etching or physical bombardment.This damage can cause the variation of roughness, smoothness and the material character of deep trench bottom, and can have influence on other processing step subsequently.
When removing the upper strata residual oxide in order to reduce plasma etching to the damage of deep trench bottom, mainly be the process conditions of improving plasma etching at present, improve the selection ratio of the oxide of plasma process to silicon matrix, reduce physical bombardment effect wherein, thereby must reduce damage as far as possible, but and can not eliminate this damage fully the deep trench bottom.Therefore, in this technical field, need a kind of deep trench manufacturing process, remove in the process of the residual film of oxide layer, the loss to channel bottom is avoided in protection deep trench bottom, reduces the technical difficulty of technology.
Summary of the invention
The technical problem to be solved in the present invention provides in a kind of deep trench processes the method for protection channel bottom, and it can effectively eliminate in the deep trench processes damage to the deep trench bottom.
For solving the problems of the technologies described above, deep trench manufacturing process of the present invention, at first, have from top to bottom on the surface on the silicon chip of top oxide layer, nitride layer and lower oxide layer and form deep trench, insert mobile organic filler material in the described deep trench, form encapsulant layer on the whole silicon wafer surface; Then, remove surperficial encapsulant layer and top oxide layer; Afterwards, remove residual filling materials layer in the deep trench.
Described packing material is photoresist or organic antireflective coating material.
The method of the surperficial packing material of described removal is plasma etching or plasma ashing method.
The method of described removal top oxide layer is the plasma etching method.
The method of the remaining packing material of described removal is plasma ashing or wet method.
Technology of the present invention is removed in the residual membrane process of oxide layer at plasma etching, and the deep trench bottom is filled material protection, has avoided chemical reaction and physical bombardment in the plasma etching process to the damage bottom the deep trench.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is conventional deep trench manufacturing process structural representation;
Fig. 2 is a deep trench packing material structural representation of the present invention;
Fig. 3 is that the present invention removes top oxide layer and packing material structural representation;
Fig. 4 to 5 is structural representations that the present invention removes remaining packing material.
Embodiment
For avoiding the upper strata oxide-film to remove the damage of process ionic medium etching to the deep trench bottom, the method that the present invention proposes is as described below:
As shown in Figure 1, be that the deep trench top oxide layer is removed process schematic representation, number in the figure 1 is a top oxide layer, the 2nd, nitride layer, the 3rd, lower oxide layer, the 4th, silicon matrix material.
The first step is that deep trench is filled, as shown in Figure 2, after deep trench forms, utilize coating device (coater) organic fillibility material that will flow to be packed in the deep trench, deep trench is filled, and forms certain thickness surperficial packed layer on the whole silicon wafer surface, described packing material comprises common photoresist or organic antireflective coating, these materials can be filled in the deep trench under conditions such as certain temperature, rotating speed well;
Second step was the removal of surperficial packed layer and top oxide layer.Adjust the existing plasma etching industrial of removing oxide skin(coating), make it comprise two stages, promptly surperficial packed layer is removed and top oxide layer is removed.In phase I, as shown in Figure 3, the packed layer of silicon chip surface is removed, and top oxide layer is come out, simultaneously the certain altitude that is etched of the packing material in the deep trench.After second stage in, as shown in Figure 4, the top oxide layer of utilizing the plasma etching method remove to expose, the packing material in the deep trench is further etched certain altitude simultaneously.
The 3rd step was the removal of remaining packing material in the deep trench.Utilize technologies such as plasma ashing or wet method to remove residual filling materials in the deep trench, as shown in Figure 5.
Wherein, second step process also can be decomposed into two independent step process, and can realize its purpose by diverse ways, equipment or technology respectively.
Surperficial packed layer in second step is removed the stage, can adopt plasma etching commonly used or plasma ashing technology and equipment.Under radio frequency (RF) effect, oxygen (O2), the nitrogen all gases such as (N2) in the equipment cavity partly is dissociated into active plasma, with packing material, and for example material such as photoresistance, organic antireflective coating reaction.Behind the certain hour, the packing material on surface is removed fully.Simultaneously, the packing material in the deep trench is etched into certain altitude, as shown in Figure 3.
By above-mentioned technology; utilize mobile organic materials such as photoresistance or organic antireflective coating material to be packed into groove inside; and control certain filling degree of depth; remove in the oxide mask process at plasma etching subsequently; packing material can be protected channel bottom; eliminated damage effectively, simultaneously, reduced the technical difficulty of mask removal technology channel bottom.

Claims (5)

1, the method for protection channel bottom in a kind of deep trench processes, it is characterized in that: at first, have from top to bottom on the surface on the silicon chip of top oxide layer, nitride layer and lower oxide layer and form deep trench, insert mobile organic filler material in the described deep trench, form encapsulant layer on the whole silicon wafer surface; Then, remove surperficial encapsulant layer and described top oxide layer; Afterwards, remove residual filling materials layer in the deep trench.
2, the method for protection channel bottom in the deep trench processes as claimed in claim 1, it is characterized in that: described packing material is photoresist or organic antireflective coating material.
3, the method for protection channel bottom in the deep trench processes as claimed in claim 1, it is characterized in that: the method for the surperficial packing material of described removal is plasma etching or plasma ashing method.
4, the method for protection channel bottom in the deep trench processes as claimed in claim 1, it is characterized in that: the method for described removal top oxide layer is the plasma etching method.
5, the method for protection channel bottom in the deep trench processes as claimed in claim 1, it is characterized in that: the method for remaining encapsulant layer is plasma ashing or wet method in the described removal deep trench.
CNB2006101193914A 2006-12-11 2006-12-11 Method of protecting plow groove bottom in deep plow groove techniques Active CN100501938C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006101193914A CN100501938C (en) 2006-12-11 2006-12-11 Method of protecting plow groove bottom in deep plow groove techniques

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006101193914A CN100501938C (en) 2006-12-11 2006-12-11 Method of protecting plow groove bottom in deep plow groove techniques

Publications (2)

Publication Number Publication Date
CN101202228A CN101202228A (en) 2008-06-18
CN100501938C true CN100501938C (en) 2009-06-17

Family

ID=39517297

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101193914A Active CN100501938C (en) 2006-12-11 2006-12-11 Method of protecting plow groove bottom in deep plow groove techniques

Country Status (1)

Country Link
CN (1) CN100501938C (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054743B (en) * 2009-10-30 2013-05-01 中芯国际集成电路制造(上海)有限公司 Method for forming contact hole in semiconductor device
CN104241097A (en) * 2014-09-02 2014-12-24 上海华力微电子有限公司 Method for avoiding residual defect of integrated etching of semiconductor device
CN106158599A (en) * 2015-04-13 2016-11-23 中芯国际集成电路制造(上海)有限公司 It is etched back the method for hard mask and the manufacture method of interconnection layer structure
CN110553601B (en) * 2019-09-06 2021-05-18 长江存储科技有限责任公司 Morphology analysis method and device for etched structure
CN117877974B (en) * 2024-03-11 2024-06-11 合肥晶合集成电路股份有限公司 Preparation method of deep trench structure and deep trench structure

Also Published As

Publication number Publication date
CN101202228A (en) 2008-06-18

Similar Documents

Publication Publication Date Title
CN105336571B (en) The forming method of autoregistration multiple graphics mask
CN101459115A (en) Shallow groove isolation construction manufacturing method
CN100501938C (en) Method of protecting plow groove bottom in deep plow groove techniques
CN102054672B (en) Process method for forming minisize pattern on substrate with waved surface
CN100565817C (en) A kind of method of improving deep plough groove etched oxide hard mask profile
JP2013089801A (en) Method of manufacturing semiconductor device
KR100680948B1 (en) Method for manufacturing storage node contact of semiconductor device
JP2009152586A (en) Method of manufacturing semiconductor device
KR20090045754A (en) Method for forming pattern in semiconductor device using hardmask
CN102254854B (en) The forming method of double; two groove isolation constructions
CN108933132B (en) Semiconductor device and method of forming the same
CN100524689C (en) Method for avoiding generating angle groove in deep plow groove technics
CN111403278B (en) Method for forming mandrel pattern
KR101004526B1 (en) Method for forming capacitor of semiconductor device
CN110993559B (en) Method for forming semiconductor device
US11205572B2 (en) Semiconductor device and fabrication method thereof
KR102153515B1 (en) Sacrificial material for stripping masking layers
KR100713315B1 (en) Method for forming non-salicide in fabricating semiconductor devices
KR100751662B1 (en) Method of manufacturing a flash memory device
CN110797344B (en) Method for manufacturing semiconductor device
CN102087960A (en) Method for forming active area
KR100745051B1 (en) Method for forming the contact in semiconductor device
CN115589724A (en) Method for improving hole defect of flash memory device
KR100579851B1 (en) Isolation Method for semiconductor device
KR20020002164A (en) Method of forming isolation layer of semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140108

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TR01 Transfer of patent right

Effective date of registration: 20140108

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.