CN108649015B - Preparation method of SON device - Google Patents
Preparation method of SON device Download PDFInfo
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- CN108649015B CN108649015B CN201810482594.2A CN201810482594A CN108649015B CN 108649015 B CN108649015 B CN 108649015B CN 201810482594 A CN201810482594 A CN 201810482594A CN 108649015 B CN108649015 B CN 108649015B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Abstract
The invention provides a preparation method of an SON device, which comprises the steps of providing a substrate, forming a transition layer on the substrate, forming a first dielectric layer and a semiconductor layer which are arranged at intervals on the transition layer, and forming a mask layer on the first dielectric layer and the semiconductor layer; carrying out first etching to form a first opening, and exposing the first group of side faces of the transition layer; performing second etching to enable the transition layer below the semiconductor layer to be partially etched; carrying out third etching to form a second opening, and exposing the second group of side faces of the transition layer; and etching for the fourth time to remove all the transition layers below the semiconductor layer and form a cavity layer below the semiconductor layer. The method provided by the invention etches the transition layer under the semiconductor layer twice, realizes twice etching of the transition layer through the formed first opening and the second opening, forms the SON device structure, can simply and effectively form the cavity layer under the semiconductor layer, and thus can better finish the preparation of the device.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a preparation method of an SON device.
Background
To improve the performance and cost-to-performance ratio of integrated circuit chips, shrinking the device feature size and thus increasing the integration density is a major approach. However, as the device size is reduced, power consumption and leakage current become the most significant concerns. Silicon-On-Insulator (SOI) structures have become the preferred structure for deep sub-micron MOS devices because of their ability to suppress short channel effects and improve device scaling.
With the development of SOI technology, researchers have developed a new transistor structure, son (silicon on nothing) transistor. SON (Silicon-On-Nothing) is a high-grade technology developed for sub-90 nm CMOS by CEA-LETI and ST Italian semiconductor company, SON forms local Silicon-On-insulator under a channel through a 'hollow' structure, SON (Silicon-On-Nothing) technology is a method for reducing effects such as short channel of an SOI (Silicon On insulator) device, compared with an SO1 device, the SON MOS device greatly reduces the influence of a buried oxygen two-dimensional electric field effect due to reduction of dielectric constant of a buried medium layer, a DIBL effect can be greatly reduced, and good short channel characteristics can be obtained by controlling the thickness of a Silicon film and the thickness of the buried medium layer, a steep sub-threshold slope can be obtained, and the self-heating effect of the SOI device can be improved.
However, the manufacturing process of the SON device is usually complicated, and the existing transistor manufacturing process needs to be changed to a great extent, so that a new manufacturing method of the SON device needs to be developed, and the void layer below the source/drain region and/or the channel region of the transistor can be formed simply and effectively, so as to complete the device manufacturing better.
Disclosure of Invention
The invention aims to provide a preparation method of an SON device, which aims to solve the problems that the manufacturing process of the SON device is usually complex and the existing transistor manufacturing process needs to be changed to a great extent.
In order to achieve the above object, the present invention provides a method for manufacturing a SON device, including the following steps:
providing a substrate, forming a transition layer on the substrate, forming a first dielectric layer and a semiconductor layer which are arranged at intervals on the transition layer, and forming a mask layer on the first dielectric layer and the semiconductor layer;
performing first etching on the area where the first dielectric layer is located to form a first opening, and exposing partial surface of the substrate and the first group of side faces of the transition layer;
taking the first group of side faces of the transition layer as a reaction interface, and performing second etching to enable the transition layer below the semiconductor layer to be partially etched;
filling from the first opening to form a first shallow trench isolation;
performing third etching between the adjacent first shallow trench isolations to form a second opening, and exposing partial side surfaces of the adjacent first shallow trench isolations and a second group of side surfaces of the transition layer;
taking the second group of side surfaces of the transition layer as a reaction interface, and performing fourth etching to completely remove the transition layer below the semiconductor layer and form a cavity layer below the semiconductor layer; and
and filling the second opening to form a second shallow trench isolation.
Optionally, a gap is formed between the first shallow trench isolation and the transition layer.
Optionally, the first etching and the third etching use dry etching.
Optionally, the first etching includes etching the mask layer, the oxide layer, and the transition layer.
Optionally, a second dielectric layer is further included between the layer where the first dielectric layer and the semiconductor layer are located and the mask layer.
Optionally, the third etching includes etching the mask layer, the second dielectric layer, the semiconductor layer, and the transition layer.
Optionally, the third etching includes etching the mask layer, the second dielectric layer, the first dielectric layer, the semiconductor layer, and the transition layer.
Optionally, the first etching and the third etching use CF4 gas to etch the transition layer.
Optionally, the second etching and the fourth etching use wet etching.
Optionally, the second etching and the fourth etching use a CF4 etchant to etch the transition layer.
Optionally, the first shallow trench isolation and the second shallow trench isolation are formed by a high-density plasma chemical vapor deposition method.
Optionally, the step of filling from the second opening to form a second shallow trench isolation further includes: and removing the mask layer, the second dielectric layer and the first shallow trench isolation and the second shallow trench isolation in the layer where the mask layer and the second dielectric layer are located.
Optionally, when the fourth etching is performed, the first shallow trench isolation provides support for the fourth etching.
In summary, in the preparation method of the SON device provided by the present invention, a substrate is provided, a transition layer is formed on the substrate, a first dielectric layer and a semiconductor layer are formed on the transition layer at intervals, and a mask layer is formed on the first dielectric layer and the semiconductor layer; performing first etching on the area where the first dielectric layer is located to form a first opening, and exposing partial surface of the substrate and the first group of side faces of the transition layer; taking the first group of side faces of the transition layer as a reaction interface, and performing second etching to enable the transition layer below the semiconductor layer to be partially etched; filling from the first opening to form a first shallow trench isolation; performing third etching between the adjacent first shallow trench isolations to form a second opening, and exposing partial side surfaces of the adjacent first shallow trench isolations and a second group of side surfaces of the transition layer; taking the second group of side surfaces of the transition layer as a reaction interface, and performing fourth etching to completely remove the transition layer below the semiconductor layer and form a cavity layer below the semiconductor layer; and filling from the second opening to form a second shallow trench isolation. The method provided by the invention etches the transition layer under the semiconductor layer twice, realizes the etching of the transition layer through the formed first opening and the second opening, forms the SON device structure, can simply and effectively form the cavity layer under the semiconductor layer, and thus can better finish the preparation of the device.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing an SON device according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a substrate after a transition layer is formed thereon according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram illustrating a first dielectric layer formed on a transition layer according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram illustrating a semiconductor layer region formed by etching a first dielectric layer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a semiconductor layer formed by filling a dielectric in a semiconductor layer region according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a second dielectric layer and a mask layer formed on a layer where the first dielectric layer and the semiconductor layer are located according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view of a device structure after a first etch in accordance with an embodiment of the present invention;
FIG. 8 is a cross-sectional view of the device structure after a second etch as provided by an embodiment of the present invention;
FIG. 9 is a cross-sectional view of the device structure after forming a first shallow trench isolation provided in an embodiment of the present invention;
FIG. 10 is a top view of the device structure after a third etch in accordance with an embodiment of the present invention;
FIG. 11 is a cross-sectional view of the device structure at the second opening along the AA' direction after the third etching according to the embodiment of the present invention;
FIG. 12 is another cross-sectional view of the device structure at the second opening along the AA' direction after the third etching according to the embodiment of the invention;
fig. 13 is a cross-sectional view of the device structure at the second opening in the BB' direction after the third etching according to the embodiment of the present invention;
FIG. 14 is a cross-sectional view of a device structure after a fourth etch in the direction of device structure CC' in accordance with an embodiment of the present invention;
FIG. 15 is a cross-sectional view of the device structure after the fourth etching in the direction of device structure BB' according to the embodiment of the present invention;
FIG. 16 is a cross-sectional view of the device structure after forming a second shallow trench isolation according to an embodiment of the present invention;
fig. 17 is a cross-sectional view of a device structure of a SON device in the CC' direction according to an embodiment of the present invention;
fig. 18 is a cross-sectional view of a device structure of a SON device in a BB' direction according to an embodiment of the present invention;
the method comprises the steps of 1-substrate, 2-transition layer, 3-first dielectric layer, 4-semiconductor layer, 5-second dielectric layer, 6-mask layer, 7-first opening, 8-first shallow trench isolation, 9-gap, 10-second opening, 11-cavity layer and 12-second shallow trench isolation.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
As described in the background, the most critical issue for fabricating SON devices is how to fabricate the void layer, however, the fabrication process of SON devices is usually complicated and requires a great deal of modification to the existing transistor fabrication process.
Therefore, in order to solve the above problems in manufacturing a semiconductor device, the present invention provides a method for manufacturing a SON device.
Referring to fig. 1, which is a schematic flow chart of a method for fabricating a SON device according to an embodiment of the present invention, as shown in fig. 1, the method for fabricating a SON device includes the following steps:
step S1: providing a substrate, forming a transition layer on the substrate, forming a first dielectric layer and a semiconductor layer which are arranged at intervals on the transition layer, and forming a mask layer on the first dielectric layer and the semiconductor layer;
step S2: performing first etching on the area where the first dielectric layer is located to form a first opening, and exposing partial surface of the substrate and the first group of side faces of the transition layer;
step S3: taking the first group of side faces of the transition layer as a reaction interface, and performing second etching to enable the transition layer below the semiconductor layer to be partially etched;
step S4: filling from the first opening to form a first shallow trench isolation;
step S5: performing third etching between the adjacent first shallow trench isolations to form a second opening, and exposing partial side surfaces of the shallow trench isolations and a second group of side surfaces of the transition layer;
step S6: taking the second group of side surfaces of the transition layer as a reaction interface, and performing fourth etching to completely etch the transition layer below the semiconductor layer and form a cavity layer below the semiconductor layer; and
step S7: and filling the second opening to form a second shallow trench isolation.
Specifically, in step S1, referring to fig. 2, a substrate 1 is provided, the substrate 1 is made of high resistivity silicon, and a transition layer 2 is formed on the substrate 1. Preferably, the transition layer 2 is a silicon germanium layer, and the forming of the first dielectric layer and the semiconductor layer arranged at intervals on the transition layer 2 with reference to fig. 3 to 5 specifically includes forming the first dielectric layer 3 on the transition layer 2, then defining a pattern of the semiconductor layer on the first dielectric layer 3 by photolithography, then performing etching to form a semiconductor layer region, and extending monocrystalline silicon in the formed semiconductor layer region to form the semiconductor layer 4. Referring to fig. 6, after the semiconductor layer 4 is formed, a second dielectric layer 5 is formed on the level of the first dielectric layer and the semiconductor layer 4, and in particular, the first dielectric layer 3 and the second dielectric layer 5 include an oxide layer. A mask layer 6 is formed on the second dielectric layer 5, and specifically, the mask layer 6 may include a silicon nitride layer. Preferably, the transition layer, the first dielectric layer 3, the second dielectric layer 5 and the mask layer 6 are formed by a chemical vapor deposition method; the semiconductor layer can be formed by an epitaxial method.
Next, referring to fig. 7, further, in step S2, etching the device structure formed in step S1, where the first etching in the area where the first dielectric layer is located specifically includes: and sequentially etching the mask layer 6, the second dielectric layer 5, the first dielectric layer 3 and the transition layer 2 to the surface of the substrate 1. The above-mentionedAfter the first etching is completed, a first opening 7 is formed to expose a portion of the surface of the substrate 1 and a first set of side surfaces of the transition layer 2. Further, the first etching is a dry etching method, and specifically, the mask layer 6 may be etched by CF4Or CHF3Gas, the etching of the second dielectric layer 5 and the first dielectric layer 3 can adopt CF4Or CHF3Gas, CF may be used for etching the transition layer 24A gas.
Continuing with fig. 8, in step S3, a second etching is performed to partially etch the transition layer 2 under the semiconductor layer 4 by using the exposed first group of sides of the transition layer 2 as a reaction interface. Further, the second etching is performed on the transition layer 2 by using the first opening 7 formed in step S2 and using the exposed first group of side surfaces of the transition layer 2 as a reaction interface, and by using a wet etching method. Specifically, CF can be used4The transition layer 2 is etched by an etchant.
Then, referring to fig. 9, in step S4, the first opening 7 is filled with a dielectric to form a first shallow trench isolation 8. Specifically, the dielectric may be silicon dioxide, and further, the first shallow trench isolation 8 may be formed by a high density plasma chemical vapor deposition method; and after the first shallow trench isolation 8 is formed, flattening the shallow trench isolation by adopting chemical mechanical polishing. Further, the first shallow trench isolation 8 fills a part of the cavity formed by the second etching, so that a gap 9 is left between the first shallow trench isolation 8 and the transition layer 2.
Next, referring to fig. 10, in step S5, a third etching is performed to form a second opening 10. Further, the third etching is performed between adjacent first shallow trench isolations 8 to form the second opening 10, so as to expose a part of the side surfaces of the first shallow trench isolations 8 and the second group of side surfaces of the transition layer 2. Further, referring to fig. 11 and 12, cross-sectional views of the device structure along the direction of the second opening AA'; referring to fig. 13, a cross-sectional view of the device structure in the direction of BB' at the second opening is shown.Specifically, the third etching is performed by a dry etching method. Optionally, referring to fig. 11, the third etching includes etching the mask layer 6, the second dielectric layer 5, the semiconductor layer 4, and the transition layer 2; optionally, referring to fig. 12, the third etching includes etching the mask layer 6, the second dielectric layer 5, the first dielectric layer 3, the semiconductor layer 4, and the transition layer 2. Preferably, CF may be used for etching the mask layer 54Or CHF3The etching of the second dielectric layer 5 and the first dielectric layer 3 may be performed using CF gas4Or CHF3Gas, etching of the semiconductor layer 4 may use SF6Or O2Gas, CF may be used for etching the transition layer 24A gas.
Continuing to refer to fig. 11 to 15, in step S6, a fourth etching is performed with the exposed second group of side surfaces of the transition layer 2 as a reaction interface, so that the transition layer 2 under the semiconductor layer 4 is completely removed, and a void layer 11 is formed under the semiconductor layer 4. Further, the fourth etching utilizes the second opening 10 formed in step S5, and etches the remaining transition layer 2 under the semiconductor layer 4 by using the exposed second group of side surfaces of the transition layer 2 as a reaction interface and using a wet etching method. Preferably, CF can be used4The transition layer 2 is etched by an etchant. Further, when the fourth etching is performed, the first shallow trench isolation 8 provides support for the fourth etching to prevent the transition layer 2 below the semiconductor layer 4 from being hollowed and collapsed. Specifically, fig. 14 is a cross-sectional view of the device structure in the CC 'direction after the fourth etching is completed, and fig. 15 is a cross-sectional view of the device structure in the BB' direction after the fourth etching is completed.
Finally, referring to fig. 14, in step S7, the second opening 10 formed by the third etching is filled with a dielectric to form a second shallow trench isolation 12. In particular, the dielectric may be silicon dioxide. Further, the second shallow trench isolation 12 may be formed by a high density plasma chemical vapor deposition method, and after the second shallow trench isolation 12 is formed, the second shallow trench isolation 12 is planarized by a chemical mechanical polishing method.
Further, referring to fig. 17 and 18, the step of filling the second opening 10 formed by the third etching and forming the second shallow trench isolation 12 further includes: and removing the mask layer 6, the second dielectric layer 5, and the first shallow trench isolation 8 and the second shallow trench isolation 12 in the layer where the mask layer 5 and the second dielectric layer 6 are located, so as to form the SON device structure.
In summary, in the method for manufacturing an SOI wafer according to the present invention, a substrate is provided, a transition layer is formed on the substrate, a first dielectric layer and a semiconductor layer are formed on the transition layer at intervals, and a mask layer is formed on the first dielectric layer and the semiconductor layer; performing first etching on the area where the first dielectric layer is located to form a first opening, and exposing partial surface of the substrate and the first group of side faces of the transition layer; taking the first group of side faces of the transition layer as a reaction interface, and performing second etching to enable the transition layer below the semiconductor layer to be partially etched; filling from the first opening to form a first shallow trench isolation; performing third etching between the adjacent first shallow trench isolations to form a second opening, and exposing partial side surfaces of the adjacent first shallow trench isolations and a second group of side surfaces of the transition layer; taking the second group of side surfaces of the transition layer as a reaction interface, and performing fourth etching to completely remove the transition layer below the semiconductor layer and form a cavity layer below the semiconductor layer; and filling from the second opening to form a second shallow trench isolation. The method provided by the invention etches the transition layer under the semiconductor layer twice, realizes the etching of the transition layer through the formed first opening and the second opening, forms the SON device structure, can simply and effectively form the cavity layer under the semiconductor layer, and thus can better finish the preparation of the device.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A preparation method of the SON device is characterized by comprising the following steps:
providing a substrate, forming a transition layer on the substrate, forming a first dielectric layer and a semiconductor layer which are arranged at intervals on the transition layer, and forming a mask layer on the first dielectric layer and the semiconductor layer; wherein the first dielectric layer comprises an oxide;
performing first etching on the region where the first dielectric layer is located to form a first opening, and exposing partial surface of the substrate and the first group of side faces of the transition layer;
taking the first group of side faces of the transition layer as a reaction interface, and performing second etching to enable the transition layer below the semiconductor layer to be partially etched;
filling from the first opening to form a first shallow trench isolation;
performing third etching between the adjacent first shallow trench isolations to form a second opening, and exposing partial side surfaces of the adjacent first shallow trench isolations and a second group of side surfaces of the transition layer;
taking the second group of side surfaces of the transition layer as a reaction interface, and performing fourth etching to completely remove the transition layer below the semiconductor layer and form a cavity layer below the semiconductor layer; filling from the second opening to form a second shallow trench isolation; and the first etching comprises etching the mask layer, the first dielectric layer and the transition layer and stopping on the surface of the semiconductor substrate.
2. The method of fabricating the SON device of claim 1, wherein there is a gap between the first shallow trench isolation and the transition layer.
3. The method of fabricating the SON device of claim 1, wherein the first etching and the third etching are dry etching.
4. The method of fabricating the SON device of claim 1, further comprising a second dielectric layer between the mask layer and a level of the first dielectric layer and the semiconductor layer.
5. The method of fabricating the SON device of claim 4, wherein the third etching includes etching the mask layer, the second dielectric layer, the semiconductor layer, and the transition layer.
6. The method of fabricating the SON device of claim 4, wherein the third etching includes etching the mask layer, the second dielectric layer, the first dielectric layer, the semiconductor layer, and the transition layer.
7. The method of fabricating the SON device of claim 3, wherein the first etching and the third etching use CF4 gas to etch the transition layer.
8. The method of fabricating the SON device of claim 1, wherein the second etching and the fourth etching are wet etching.
9. The method of fabricating the SON device of claim 8, wherein the second etching and the fourth etching etch the transition layer with a CF4 etchant.
10. The method of fabricating the SON device of claim 1, wherein the first shallow trench isolation and the second shallow trench isolation are formed using a high density plasma chemical vapor deposition (hdpcvd) process.
11. The method of fabricating the SON device of claim 4, wherein the step of filling from the second opening to form the second shallow trench isolation further comprises: and removing the mask layer, the second dielectric layer and the first shallow trench isolation and the second shallow trench isolation in the layer where the mask layer and the second dielectric layer are located.
12. The method of fabricating the SON device of claim 1, wherein the first shallow trench isolation provides support for the fourth etching while the fourth etching is performed.
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| US7015147B2 (en) * | 2003-07-22 | 2006-03-21 | Sharp Laboratories Of America, Inc. | Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer |
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