CN104733313A - Fin-type field effect transistor forming method - Google Patents

Fin-type field effect transistor forming method Download PDF

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Publication number
CN104733313A
CN104733313A CN201310698757.8A CN201310698757A CN104733313A CN 104733313 A CN104733313 A CN 104733313A CN 201310698757 A CN201310698757 A CN 201310698757A CN 104733313 A CN104733313 A CN 104733313A
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fin
coating
oxide skin
field effect
effect transistor
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CN104733313B (en
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刘海龙
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention discloses a fin-type field effect transistor forming method. After a semiconductor substrate is etched to form an oxide layer coating a fin, the oxide layer is etched, the fin with a partial height is exposed, and part of the oxide layer is kept on the side wall of the fin; and then ions are injected in the remaining oxide layer on the side wall of the fin, and the remaining oxide layer injected with ions on the side wall of the fin is removed. After the ions are injected in the oxide layer, binding of the oxide is broken, the etching speed of the oxide layer can be effectively improved, the oxide layer attached to the side wall of the fin can be effectively removed, bad influences on a subsequent manufacturing process of the fin-type field effect transistor by the remaining oxide layer on the side wall of the fin can be avoided, and the performance of the finally-formed fin-type field effect transistor is improved.

Description

The formation method of fin formula field effect transistor
Technical field
The present invention relates to semiconductor and form field, especially relate to a kind of formation method of fin formula field effect transistor.
Background technology
Along with the develop rapidly of integrated circuit (being called for short IC) manufacturing technology, after especially entering sub-micron features size field, traditional integrated circuit size constantly reduces, and the size of semiconductor element also must correspondingly diminish.
But, if MOS transistor is by applying voltage at grid, regulates and producing switching signal by the electric current of channel region, but when semiconductor technology enters 45 nanometers with lower node, the traditional control ability of plane formula MOS transistor to channel current dies down, and causes serious leakage current.Conventional MOS transistor cannot meet the demand to device performance, and multi-gate device is paid close attention to widely as alternative the obtaining of conventional device.
Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device.Shown in figure 1, conventional Fin FET comprises: Semiconductor substrate 1; Be positioned at the fin 3 in Semiconductor substrate 1; Be positioned at the oxide skin(coating) 2 in Semiconductor substrate 1; Be positioned at oxide skin(coating) 2 surface successively and across the gate oxide layers (not shown) of fin 3 and grid 4; Side wall 6 between the fin being positioned at fin 3 both sides; Be positioned at the grid curb wall 5 of grid 4 both sides; Be positioned at the source/drain 31 of grid 4 and grid curb wall 5 both sides fin 3.
For Fin FET, the part that the top of fin 3 and the sidewall of both sides contact with grid all becomes channel region, namely has multiple grid, is conducive to increasing drive current, improves device performance.
Incorporated by reference to reference to shown in figure 2, the preparation technology of Fin FET is as follows:
First be etched in Semiconductor substrate 1 and form multiple fin 3; Form oxide skin(coating) 2 on semiconductor substrate 1 afterwards; Remove the oxide skin(coating) 2 of segment thickness, after making fin 3 upper end expose described oxide skin(coating) 2, gate dielectric and semiconductor material layer (not shown) is formed according to this above described fin 3 with oxide skin(coating) 2, and form side wall 5 between grid curb wall 6 as shown in Figure 1 and fin in described fin 3 and semiconductor material layer both sides, and form source-drain electrode by modes such as ion implantations.
But in actual fabrication process, after the described oxide skin(coating) 2 of etching exposes described fin 3, on described oxide skin(coating) 2 surface, oxide skin(coating) 2 and the intersection of fin 3 form residual (footing) 21 being attached at fin 3 sidewall.In subsequent technique prepared by follow-up Fin FET, described residual 21 can affect after the gate dielectric Rotating fields that formed on described fin 3 surface and quality, thus the performance of the final Fin FET formed of impact.
For this reason, etching the oxide skin(coating) that is deposited on above described fin, to expose in the technique of described fin upper end, removing after how guaranteeing etching technics that the oxide skin(coating) being attached to fin surface remains is the problem that those skilled in the art need solution badly.
Summary of the invention
The problem that the present invention solves is in fin formula field effect transistor preparation process, effectively can improve the efficiency that etching is deposited on the oxide skin(coating) above described fin, avoids oxide skin(coating) to remain and is attached in fin sidewall.
For solving the problem, the invention provides a kind of formation method of fin formula field effect transistor, comprising:
Semiconductor substrate is provided;
Etching institute Semiconductor substrate, forms fin;
Form oxide skin(coating) on the semiconductor substrate, and described oxide skin(coating) covers described fin;
Etch described oxide skin(coating), the fin of gauge height, remain portions of oxide layer at the sidewall of the fin of exposed portion;
Ion is injected in the oxide skin(coating) that the sidewall of described fin is residual;
Remove the oxide skin(coating) that fin sidewall injects ion.
Alternatively, the energy of ion implantation is 1 ~ 10Kev, and dosage is 1 × 10 14~ 1 × 10 16cm -2.
Alternatively, described ion comprises N, He or Ar.
Alternatively, the angle of ion implantation is be 10 ~ 80 ° with described fin height direction.
Alternatively, ion implantation angle is be 30 ~ 60 ° with described fin height direction.
Alternatively, etching removes the technique of the oxide skin(coating) of fin sidewall injection ion is wet-etching technology.
Alternatively, described wet-etching technology comprises: adopt hydrofluoric acid aqueous solution as etching agent, the volumetric concentration of described hydrofluoric acid aqueous solution is 0.1% ~ 1%, and temperature is 20 ~ 60 DEG C.
Alternatively, the duration of described wet etching is 10 ~ 60s.
Alternatively, after removing the oxide skin(coating) of fin sidewall injection ion, annealing process is carried out.
Alternatively, the temperature of described annealing process is 30 DEG C ~ 200 DEG C, and lasting annealing time is 10 ~ 60s.
Compared with prior art, technical scheme of the present invention has the following advantages:
At the described oxide skin(coating) of etching, after the fin of gauge height, injecting ion to being attached in oxide skin(coating) residual in fin sidewall, described in removing afterwards, being injected with the oxide skin(coating) of ion.Based on inject ion in described oxide skin(coating) after, described ion makes the oxide binding in described oxide skin(coating) rupture, and new binding can not be formed, and then effectively can improve the removal efficiency of oxide skin(coating), the oxide skin(coating) avoiding remaining in fin sidewall causes adverse effect for the follow-up preparation technology of fin formula field effect transistor, and then improves the performance of the final fin formula field effect transistor formed.
Further, the ion injected in described oxide skin(coating) adopts the gas ions such as Ar, N, He, described gas ion can cause the oxide binding in oxide skin(coating) to rupture, but new binding can't be formed, thus carry out in annealing process follow-up, can remove efficiently and remainingly be infused in ion in described Semiconductor substrate and oxide skin(coating), thus avoid these residual ions to produce harmful effect to semiconductor device.
Accompanying drawing explanation
The structural representation of the existing fin formula field effect transistor of Fig. 1;
Fig. 2 is the preparation process schematic diagram of fin formula field effect transistor in Fig. 1;
Fig. 3 to Fig. 8 is the schematic diagram of the formation method of the fin formula field effect transistor that one embodiment of the invention provides.
Embodiment
As described in the background art, in fin formula field effect transistor preparation process, etching the oxide skin(coating) be covered in above fin, with in the fin process of gauge height, can at the sidewall residual fraction oxide skin(coating) of fin.This part oxide skin(coating) directly can affect the performance of the fin formula field effect transistor of follow-up formation.Analyze its reason, may be, in fin formula field effect transistor preparation process, based on the structural requirement of the fin formula field effect transistor of required formation, and process conditions, the density of the oxide that described fin is formed is different, based on the oxide skin(coating) density variation of different parts, and causes the etch rate difference of the oxide skin(coating) of subsequent etching different parts.Typical example is such as:
In fin formula field effect transistor preparation process, the forming process of described oxide skin(coating) comprises: after forming fin on the semiconductor device, first thermal oxidation technology can be adopted to form thermal oxide layer, in order to protect fin from damage in subsequent technique in Semiconductor substrate and fin surface; Afterwards again in employing CVD(chemical vapor deposition method) continue deposited oxide layer on established thermal oxide layer surface.Namely the oxide skin(coating) covered in described fin and Semiconductor substrate includes the oxide skin(coating) of thermal oxide layer and the follow-up employing CVD technique formation adopting thermal oxidation technology to be formed.And the density of thermal oxide layer is greater than the oxide skin(coating) adopting CVD technique to be formed, thus when etching described oxide skin(coating), when etching thermal oxide layer, with when etching the oxide skin(coating) adopting CVD technique to be formed, there is obvious etch rate difference, the etch rate of thermal oxide layer is starkly lower than the oxide skin(coating) adopting CVD technique to be formed, and thus the surface of fin can retain the oxide skin(coating) of part.And if strengthen etching dynamics to remove this layer and be attached to oxide skin(coating) above fin, then may occur over etching phenomenon, impact is finally formed at the quality of the oxide skin(coating) of semiconductor substrate.
Damage in etching technics based on this part oxide skin(coating) be attached to above fin, even if follow-up after fin surface forms gate dielectric layer, this part oxide skin(coating) damaged still can produce harmful effect to the semiconductor device of follow-up formation.
For this reason, the invention provides a kind of formation method of fin formula field effect transistor, while removal is covered in described fin oxide layer, avoids over etching to produce, thus guarantee the stuctures and properties of the final fin formula field effect transistor formed.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The formation method of the present embodiment fin formula field effect transistor comprises:
Shown in figure 3, provide Semiconductor substrate 10, etching institute Semiconductor substrate 10, forms fin 20.Described fin 20 is raised in the surface of Semiconductor substrate 10.
Described Semiconductor substrate 10 can be silicon substrate, and also can be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, common Semiconductor substrate all can be used as the Semiconductor substrate in the present embodiment.
Semiconductor substrate 10 in the present embodiment is chosen as silicon substrate.
The formation method of described fin comprises: first form photoresist layer on the semiconductor substrate; After exposure, developing process, in described photoresist layer, form photoetching agent pattern; Afterwards with the photoresist layer after patterning for Semiconductor substrate described in mask etching, thus form fin on a semiconductor substrate.The formation process of above-mentioned fin is the maturation process of this area, does not repeat them here.
In the present embodiment, after etching described Semiconductor substrate 10, form multiple convex fin 20 over the semiconductor substrate 10, and the spacing of adjacent two fins 20 is 10 ~ 30nm simultaneously.
Shown in figure 4, described Semiconductor substrate 10 forms oxide skin(coating) 30, described oxide skin(coating) 30 covers fin 20 described in each.
In the present embodiment, described oxide skin(coating) 30 comprises thermal oxide layer 31, and is covered in the suboxide layer 32 on described thermal oxide layer 31.
The technique that described thermal oxide layer 31 is formed is thermal oxide layer technique, comprise: in the reaction chamber of the described Semiconductor substrate 10 of placement, pass into oxygen or ozone, thus make Semiconductor substrate oxidized, form thermal oxide layer 31 on Semiconductor substrate 10 surface, described thermal oxide layer 31 wraps up the surface of each fin 20 simultaneously.Described thermal oxide layer 31 in the preparation technology of follow-up fin formula field effect transistor, can available protecting Semiconductor substrate 10 from damage.The formation process of described thermal oxide layer 31 is the maturation process of this area, does not repeat them here.
After described thermal oxide layer 31 is formed, such as CVD(chemical vapor deposition method can be adopted) etc. technique on described thermal oxide layer 31, cover one deck suboxide layer 32, described suboxide layer 32 covers fin 20 described in each.
Described suboxide layer 32 can adopt such as TEOS(tetraethoxysilane) formed with the raw material reaction such as O2, the formation process of described suboxide layer 32 is the well-known processes of this area, does not repeat them here.
Shown in figure 5, after described fin 20 forms described oxide skin(coating) after 30, remove the oxide skin(coating) 30 above described fin 20 with CMP, the surface of oxide skin(coating) 30 is flushed with the upper surface of described fin 20.
Shown in figure 6, then etch described oxide skin(coating) 30(and comprise described thermal oxide layer 31 and suboxide layer 32), the fin 20 of gauge height.
In the present embodiment, the method etching described oxide skin(coating) 30 adopts wet-etching technology, and the etching agent adopted is the dilute hydrofluoric acid aqueous solution (Dilute HF is called for short DHF).Alternatively, the volumetric concentration of described DHF be 0.1% ~ 1%(namely, 1 part of HF/1000 part water to 1 part HF/100 part water), wet etching temperature is 20 ~ 60 DEG C.
In the present embodiment, oxide skin(coating) 30 etch rate based on density variation (density of described thermal oxide layer 31 is greater than the density of the suboxide layer 32) each several part of oxide skin(coating) 30 each several part has difference (etch rate of described suboxide layer 32 is obviously greater than the etch rate of thermal oxide layer 31), after the described oxide skin(coating) 30 of etching, on the sidewall of described fin 20 in residual fraction oxide skin(coating) 33(figure, dotted line circle irises wipe part).
Then with reference to shown in figure 7, in the oxide skin(coating) 33 remained on described fin 20 sidewall, inject ion, form ion implanted regions.
In the present embodiment, injecting gas ion in the oxide skin(coating) 33 that described fin 20 sidewall is residual, alternatively, described gas ion comprises Nitrogen ion (N), helium ion (He) and argon ion (Ar).
In the present embodiment, the injection technology condition of described gas ion comprises: implant angle is be 10 ~ 80 ° with the angle a of described fin height direction (i.e. vertical direction).The energy of ion implantation is 1 ~ 10Kev, and dosage is 1 × 10 14~ 1 × 10 16cm -2.
It should be noted that in the present embodiment, injecting ion simultaneously in the oxide skin(coating) 33 on the sidewall remaining in described fin 20, the ion of part in the oxide skin(coating) between adjacent described fin 20, can be injected simultaneously, thus form ion implanted regions.The present embodiment by the angle of the described ion implantation of adjustment, thus effectively can adjust the ion implanted regions scope formed at described oxide skin(coating) 30 by ion implantation.Concrete angle needs to determine according to oxide skin(coating) 33 structure remained on described fin 20 sidewall.
In the present embodiment, the spacing between adjacent two fins 20 is 10 ~ 30nm, and alternatively, the angle a of ion implantation is 30 ~ 60 °.
After completing ion implantation technology, continue the remaining oxide skin(coating) 35 of etching.With reference to shown in following table 1,
Shown in chart 1: inject the oxide skin(coating) after N ion, the DHF being 1/300 with volumetric concentration etches the etch rate chart after two minutes.
Shown in upper table 1, the etch rate injecting the sample (sample 1 ~ 7) of the oxide skin(coating) of N ion is obviously greater than the etch rate of the sample of the oxide skin(coating) not injecting N ion.And by shown in sample 1 ~ 7, the N ion concentration in oxide skin(coating) is larger, the etch rate of oxide skin(coating) is larger.
Analyze its reason, after injecting gas ion in oxide skin(coating) 30, gas ion can the binding of oxide effectively in fragment ion injection zone, and can not form new key, thus improves the etch rate of the oxide skin(coating) in ion implanted regions.
By adjusting the angle of ion implantation, and dosage and energy, thus adjustment is at the residual oxide skin(coating) 33 of described fin 20 sidewall, and in Semiconductor substrate 10 other parts oxide skin(coating) in the scope of ion implanted regions that formed.
In the present embodiment, the angle a of ion implantation is 10 ° ~ 80 °, is 30 ° ~ 60 ° further alternatively, thus makes the ion concentration of fin 20 sidewall be greater than the ion concentration at all the other positions.Thus improving the speed removed and remain in fin 20 sidewall oxide layer 33 while, reduce the etching of tunnel oxide layers (oxide skin(coating) namely between each fin 20) as far as possible, because the amount of tunnel oxide layers ion implantation is little, so its etching selection ratio is very high.Shown in figure 8, in the present embodiment, at the oxide skin(coating) 35 guaranteed between fin 20 not by under the condition of excessive removal, effectively improve the speed of the residual oxide skin(coating) 33 removing fin 20 sidewall, thus improve the efficiency except oxide layer 33.
In the present embodiment, after ion implantation technology, wet-etching technology removal is adopted to cover shown in oxide skin(coating) 33(Fig. 7 being injected with ion of described fin 20 sidewall at this).Described wet-etching technology is: employing 0.1% ~ 1% is etching solution for DHF, continues to carry out wet etching 10 ~ 60s at 20 ~ 60 DEG C.
In the present embodiment, the angle of adjustment ion implantation, and dosage adjustable is injected with the oxide layer scope of ion, and the ion concentration in oxide skin(coating), coordinate suitable etch period, effectively removing the residual oxide skin(coating) 33 of fin 20 sidewall simultaneously, the oxide skin(coating) between each fin 20 of excessive removal can be avoided.
Remove remain in described fin 20 sidewall be injected with the oxide skin(coating) of ion after, carry out annealing process, thus remove and remain in described Semiconductor substrate 10, the ion in fin 20 and remaining oxide skin(coating) 35.
After injecting gas ion in oxide skin(coating), cause the fracture of oxide binding, but new key can not be formed, thus in annealing process, adopt suitable high-temperature heating can effectively drive away the gas ion remained in oxide skin(coating) and Semiconductor substrate.
In the present embodiment, the temperature of described annealing process is 30 DEG C ~ 200 DEG C, continues annealing 10 ~ 60s.Under these conditions, under the condition not damaging Semiconductor substrate 10 and oxide skin(coating) 35, effectively remove described Semiconductor substrate 10, the ion in fin 20 and oxide skin(coating) 35.
In the present embodiment, the ion injected in oxide skin(coating) is the gas ions such as He, Ar or N ion.In above-mentioned annealing process, gas ion can overflow fast.Thus avoid the ion that injects in oxide skin(coating) to cause negative effect for the preparation technology of follow-up fin formula field effect transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (10)

1. a formation method for fin formula field effect transistor, is characterized in that: comprising:
Semiconductor substrate is provided;
Etching institute Semiconductor substrate, forms fin;
Form oxide skin(coating) on the semiconductor substrate, and described oxide skin(coating) covers described fin;
Etch described oxide skin(coating), the fin of gauge height, remain portions of oxide layer at the sidewall of the fin of exposed portion;
Ion is injected in the oxide skin(coating) that the sidewall of described fin is residual;
Remove the oxide skin(coating) that fin sidewall injects ion.
2. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, the energy of ion implantation is 1 ~ 10Kev, and dosage is 1 × 10 14~ 1 × 10 16cm -2.
3. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, described ion comprises N, He or Ar.
4. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, the angle of ion implantation is be 10 ~ 80 ° with described fin height direction.
5. the formation method of fin formula field effect transistor as claimed in claim 4, is characterized in that, ion implantation angle is be 30 ~ 60 ° with described fin height direction.
6. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, the technique that etching removes the oxide skin(coating) of fin sidewall injection ion is wet-etching technology.
7. the formation method of fin formula field effect transistor as claimed in claim 6, it is characterized in that, described wet-etching technology comprises: adopt hydrofluoric acid aqueous solution as etching agent, the volumetric concentration of described hydrofluoric acid aqueous solution is 0.1% ~ 1%, and temperature is 20 ~ 60 DEG C.
8. the formation method of fin formula field effect transistor as claimed in claim 7, it is characterized in that, the duration of described wet etching is 10 ~ 60s.
9. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, after removing the oxide skin(coating) of fin sidewall injection ion, carries out annealing process.
10. the formation method of fin formula field effect transistor as claimed in claim 9, it is characterized in that, the temperature of described annealing process is 30 DEG C ~ 200 DEG C, and lasting annealing time is 10 ~ 60s.
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CN107170740A (en) * 2016-03-07 2017-09-15 台湾积体电路制造股份有限公司 Fin field effect transistor
CN107275400A (en) * 2016-04-06 2017-10-20 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107591323A (en) * 2016-07-08 2018-01-16 中芯国际集成电路制造(上海)有限公司 The forming method of isolation structure
CN108431928A (en) * 2015-12-31 2018-08-21 上海凯世通半导体股份有限公司 The doping method of FinFET
CN108878526A (en) * 2017-05-11 2018-11-23 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110323136A (en) * 2018-03-29 2019-10-11 中芯国际集成电路制造(上海)有限公司 A kind of FinFET manufacturing process

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