CN104718619A - 用于两个或更多个裸片的多裸片倒装堆叠 - Google Patents

用于两个或更多个裸片的多裸片倒装堆叠 Download PDF

Info

Publication number
CN104718619A
CN104718619A CN201380051357.6A CN201380051357A CN104718619A CN 104718619 A CN104718619 A CN 104718619A CN 201380051357 A CN201380051357 A CN 201380051357A CN 104718619 A CN104718619 A CN 104718619A
Authority
CN
China
Prior art keywords
opening
microelectronic element
terminal
edge
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201380051357.6A
Other languages
English (en)
Chinese (zh)
Inventor
贝尔加桑·哈巴
韦勒·佐尼
理查德·德威特·克里斯普
伊利亚斯·穆罕默德
弗兰克·兰布雷希特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/741,890 external-priority patent/US9013033B2/en
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of CN104718619A publication Critical patent/CN104718619A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07553—Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/537—Multiple bond wires having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201380051357.6A 2012-08-02 2013-08-01 用于两个或更多个裸片的多裸片倒装堆叠 Pending CN104718619A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201213565613A 2012-08-02 2012-08-02
US13/565,613 2012-08-02
US13/741,890 2013-01-15
US13/741,890 US9013033B2 (en) 2011-04-21 2013-01-15 Multiple die face-down stacking for two or more die
PCT/US2013/053240 WO2014022675A1 (en) 2012-08-02 2013-08-01 Multiple die face-down stacking for two or more die

Publications (1)

Publication Number Publication Date
CN104718619A true CN104718619A (zh) 2015-06-17

Family

ID=50028532

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380051357.6A Pending CN104718619A (zh) 2012-08-02 2013-08-01 用于两个或更多个裸片的多裸片倒装堆叠

Country Status (5)

Country Link
EP (1) EP2880685A1 (https=)
JP (1) JP2015523742A (https=)
KR (1) KR20150040998A (https=)
CN (1) CN104718619A (https=)
WO (1) WO2014022675A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114040579A (zh) * 2021-11-08 2022-02-11 艾科微电子(深圳)有限公司 电子器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050116358A1 (en) * 2003-11-12 2005-06-02 Tessera,Inc. Stacked microelectronic assemblies with central contacts
US20100090326A1 (en) * 2008-10-14 2010-04-15 Samsung Electronics Co., Ltd. Stack package
US20120153435A1 (en) * 2010-12-17 2012-06-21 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174255A (ja) 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
JP2004063767A (ja) * 2002-07-29 2004-02-26 Renesas Technology Corp 半導体装置
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
JP4579258B2 (ja) * 2007-01-18 2010-11-10 力成科技股▲分▼有限公司 Ｂｇａ型パッケージ
JP2008277660A (ja) * 2007-05-02 2008-11-13 Powertech Technology Inc Ｌｇａ半導体実装構造
US8553420B2 (en) * 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050116358A1 (en) * 2003-11-12 2005-06-02 Tessera,Inc. Stacked microelectronic assemblies with central contacts
US20100090326A1 (en) * 2008-10-14 2010-04-15 Samsung Electronics Co., Ltd. Stack package
US20120153435A1 (en) * 2010-12-17 2012-06-21 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114040579A (zh) * 2021-11-08 2022-02-11 艾科微电子(深圳)有限公司 电子器件及其制造方法
CN114040579B (zh) * 2021-11-08 2023-12-22 艾科微电子(深圳)有限公司 电子器件及其制造方法

Also Published As

Publication number Publication date
KR20150040998A (ko) 2015-04-15
WO2014022675A1 (en) 2014-02-06
JP2015523742A (ja) 2015-08-13
EP2880685A1 (en) 2015-06-10

Similar Documents

Publication Publication Date Title
US8338963B2 (en) Multiple die face-down stacking for two or more die
US9437579B2 (en) Multiple die face-down stacking for two or more die
US9281295B2 (en) Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US10468380B2 (en) Stackable microelectronic package structures
US9640515B2 (en) Multiple die stacking for two or more die
US9806017B2 (en) Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US9875955B2 (en) Low cost hybrid high density package
TWI503947B (zh) 在微電子封裝、模組和系統中堆疊兩個或更多個晶粒的複合晶粒
CN104718619A (zh) 用于两个或更多个裸片的多裸片倒装堆叠
TW201428933A (zh) 適用於二個或多個晶粒之多晶粒面朝下堆疊

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150617

WD01 Invention patent application deemed withdrawn after publication