CN104717369B - A kind of centralized ring detecting circuit and its method based on FPGA - Google Patents
A kind of centralized ring detecting circuit and its method based on FPGA Download PDFInfo
- Publication number
- CN104717369B CN104717369B CN201510069417.8A CN201510069417A CN104717369B CN 104717369 B CN104717369 B CN 104717369B CN 201510069417 A CN201510069417 A CN 201510069417A CN 104717369 B CN104717369 B CN 104717369B
- Authority
- CN
- China
- Prior art keywords
- ring
- back tone
- ring back
- fpga
- effective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
Include a processor and a programmable device FPGA the invention provides a kind of centralized ring detecting circuit based on FPGA；Simulation register and ring detection module are provided with the programmable device FPGA；The ring detection module is connected with simulation register, and simulation register is connected by bus with processor；Several DAA equipment is connected by respective FXO interfaces with programmable device FPGA.Present invention also offers a kind of centralized ring detection method based on FPGA, it can realize that the bell signal transmitted to multiple FXO interfaces is handled, improve operating efficiency；Reduce the resource of processor.
Description
Technical field
The present invention relates to the ring detection technique field of FXO interfaces, more particularly to a kind of centralized ring based on FPGA
Detect circuit and its method.
Background technology
FXO interface Self-sound-produced bells are the phenomenons being commonly encountered in regular maintenance.It is multiple to be born in thunderstorm rainy season, it is primarily due to
The moist short circuit of circuit, joint contacts bad, telephone wire partial short-circuit or electric leakage etc., causes line voltage distribution height to change obvious,
FXO interfaces then think have signal to come in, so as to produce false ringing phenomenon.
Existing technology mostly use stabilization or distributed ring detection method, set anti-shaking method due to when
Between how long, influence the ring speed of response.And CPU is given after decentralized method, general use interface interrupt signal wired AND,
CPU needs poll ring detection chip one by one after receiving interruption, if FXO interface quantities are more, can take excessive CPU moneys
Source.
A kind of " device and method of detection ring " is disclosed in the prior art sees Publication No.：1193237, publication date
For：1998-09-16 Chinese patent, a kind of device of detection ring, it includes：One signal adapter, receives ring letter
Number, converted output binary bit bell signal；One microprocessor, receives the binary bit ring letter of the signal adapter output
Number, the ring number that output one is detected, wherein, the microprocessor includes：One signal reader, receives the signal and turns
The binary bit bell signal of parallel operation, sampling one sequence bell signal of output；One smoothing filter, receives the signal reader
Sequence bell signal, remove high-frequency noise interference refers to bell signal to export one；One arithmetic element, calculates the smooth filter
Zero passage points in nearest one period of the reference bell signal of ripple device output and the zero passage in a nearest period
Points；One memory cell, the zero passage stored in nearest one period that the arithmetic element is calculated is counted and nearest one
Zero passage points in period；One logic control element, judges that the zero passage in described nearest one period is counted and nearest
Zero passage points in one period, to export the ring number of a ringing condition mark and the detection.The arrangement achieves
The detection of ring, but the device can not carry out centralized detection to multiple FXO interfaces, therefore, be needed in multiple FXO interfaces
It is also required to take excessive cpu resource when detecting.
The content of the invention
One of the technical problem to be solved in the present invention, is to provide a kind of centralized ring detecting circuit based on FPGA；
The circuit provides a hardware platform for ring detection, and combining existing software by the hardware platform can realize to multiple
The bell signal that FXO interfaces are transmitted is handled, and improves operating efficiency.
What one of problem of the present invention was realized in：A kind of centralized ring detecting circuit based on FPGA, including at one
Manage device and a programmable device FPGA；Simulation register and ring detection module are provided with the programmable device FPGA；Institute
State ring detection module to be connected with simulation register, simulation register is connected by bus with processor；Several DAA equipment
It is connected by respective FXO interfaces with programmable device FPGA；The ring signal wire collection that the FXO interfaces of each DAA equipment are sent out
In send programmable device FPGA to, by ring detection module, while effective ring back tone flag bit of each road FXO interfaces
ring[0:X], ring back tone square-wave cycle ring_hz, effective ring back tone duration cnt_ring [0:X] and ring back tone interval
Time cnt_noring [0:X] record is in simulation register, and when effective ring, programmable device FPGA is exported in one
Collected in the data set that disconnected INT# records programmable device FPGA by bus to processor, processor, reach centralization and pass
Pass the effect of information；Simultaneous processor can by bus set simulate register detection ring back tone cycle ring_set_hz with
And cyclic swing scope ring_set_range.
Further, the processor is CPU or digital signal processor DSP.
Further, the programmable device FPGA uses the IC chip of EP4CE6F17C8N models.
Further, the detection of the ring detection module is specially：Programmable device FPGA is by detecting DAA equipment
The ring bell signals that DAA chips are sent out；The square-wave cycle of ring back tone is detected, ring bell signals continuous at least three are being detected
Individual square-wave cycle is judged as effective ring back tone within a preset range, then, is 1 effective ring back tone mark position, and record this and shake
The tone cycle and interruption is sent to processor, notifier processes device has ring generation, start simultaneously at the effective ring back tone of timing and continue
Time, empty ring back tone interval time；Such as detect the ring back tone cycle not within a preset range and no more than setting maximum when,
Then without operation, ring back tone cycle detection is re-started, original effective ring back tone mark invariant position is kept；If no more than three
Individual square-wave cycle within a preset range or the ring back tone cycle exceed setting maximum, then for do not occur also effective ring back tone or
Effective ring back tone has terminated, and is 0 effective ring back tone mark position, terminates effective ring back tone duration, starts timing ring
Sound interval time；If ring back tone interval time exceedes maximum, it is judged as that ring process has terminated, empties effective ring back tone
Duration, empty ring back tone square-wave cycle record；Simulation register is set inside FPGA simultaneously；Processor is set by bus
Put its square-wave cycle maximum, ring back tone square-wave cycle and preset range；Effective ring back tone duration also can be read simultaneously, has
Imitate ring flag bit, ring back tone interval time.
The second technical problem to be solved by the present invention, is to provide a kind of centralized ring detection method based on FPGA；
It can realize that the bell signal transmitted to multiple FXO interfaces is handled, improve operating efficiency.
What the two of problem of the present invention were realized in：A kind of centralized ring detection method based on FPGA, methods described
One processor and a programmable device FPGA need to be provided；Simulation register and ring inspection are provided with the programmable device FPGA
Survey module；Methods described is specially：
Step 1, several DAA equipment is connected by respective FXO interfaces with programmable device FPGA；
The ring signal wires that step 2, the FXO interfaces of each DAA equipment are sent out, which are concentrated, sends programmable device FPGA to, leads to
Ring detection module is crossed, while effective ring back tone flag bit ring [0 of each road FXO interfaces:X], ring back tone square-wave cycle
Ring_hz, effective ring back tone duration cnt_ring [0:X] and ring back tone interval time cnt_noring [0:X] record
In simulation register,
Step 3, when effective ring, programmable device FPGA exports an interrupt INT # to processor, and processor leads to
Cross and collected in the data set that bus records programmable device FPGA, reach the effect of centralized transmission information；Simultaneous processor
Detection ring back tone the cycle ring_set_hz and cyclic swing scope ring_set_ for simulating register can be set by bus
range。
Further, the processor is CPU or digital signal processor DSP.
Further, the programmable device FPGA uses the IC chip of EP4CE6F17C8N models.
Further, the detection of the ring detection module is specially：Programmable device FPGA is by detecting DAA equipment
The ring bell signals that DAA chips are sent out；The square-wave cycle of ring back tone is detected, ring bell signals continuous at least three are being detected
Individual square-wave cycle is judged as effective ring back tone within a preset range, then, is 1 effective ring back tone mark position, and record this and shake
The tone cycle and interruption is sent to processor, notifier processes device has ring generation, start simultaneously at the effective ring back tone of timing and continue
Time, empty ring back tone interval time；Such as detect the ring back tone cycle not within a preset range and no more than setting maximum when,
Then without operation, ring back tone cycle detection is re-started, original effective ring back tone mark invariant position is kept；If no more than three
Individual square-wave cycle within a preset range or the ring back tone cycle exceed setting maximum, then for do not occur also effective ring back tone or
Effective ring back tone has terminated, and is 0 effective ring back tone mark position, terminates effective ring back tone duration, starts timing ring
Sound interval time；If ring back tone interval time exceedes maximum, it is judged as that ring process has terminated, empties effective ring back tone
Duration, empty ring back tone square-wave cycle record；Simulation register is set inside FPGA simultaneously；Processor is set by bus
Put its square-wave cycle maximum, ring back tone square-wave cycle and preset range；Effective ring back tone duration also can be read simultaneously, has
Imitate ring flag bit, ring back tone interval time.
The advantage of the invention is that：1st, by the centralized ring detection method based on FPGA, it is possible to prevente effectively from processing
Device resource is consumed.
The 2nd, simulation register is set inside FPGA, centralized detection can be reached with so easy and effective that to be communicated with processor,
Centralized configuration, the effect for concentrating transmission information.
3rd, FPGA belongs to hardware language, and speed is fast.Simultaneously by centralized detecting, centralized configuration concentrates transmission information, it is to avoid
The time that poll is wasted one by one when FXO interface quantities are more, efficiency can be effectively improved.
4th, by detecting continuous three square-wave cycles, the impulse disturbances letter for occurring the just cycle once in a while can be effectively prevented from
Number.Three square-wave cycles (example 25hz) only have 120ms simultaneously, can greatly shorten set by stabilization hundreds of milliseconds to 1000 millis
The operating lag of second.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention.
Fig. 2 is schematic flow sheet of the invention.
Fig. 3 is the schematic flow sheet that ring detection module of the present invention is realized.
Embodiment
Refer to shown in Fig. 1 to Fig. 3, a kind of centralized ring detecting circuit based on FPGA, including a processor and one
Programmable device FPGA；Simulation register and ring detection module are provided with the programmable device FPGA；The ring inspection
Survey module to be connected with simulation register, simulation register is connected by bus with processor；Several DAA equipment passes through respective
FXO interfaces be connected with programmable device FPGA；The ring signal wires that the FXO interfaces of each DAA equipment are sent out are concentrated and sent to
Programmable device FPGA, by ring detection module, while effective ring back tone flag bit ring [0 of each road FXO interfaces:x]、
Ring back tone square-wave cycle ring_hz, effective ring back tone duration cnt_ring [0:X] and ring back tone interval time cnt_
noring[0:X] record simulation register in, when effective ring, programmable device FPGA export an interrupt INT # to
Collected in processor, the data set that processor records programmable device FPGA by bus, reach centralized transmission information
Effect；Programmable device FPGA concentrates these record datas and sends processor to by bus, and processor carries out detection process；
Simultaneous processor can set the detection ring back tone cycle ring_set_hz and cyclic swing scope for simulating register by bus
ring_set_range。
Wherein, the processor is CPU or digital signal processor DSP.
The programmable device FPGA uses the IC chip of EP4CE6F17C8N models.
The detection of the ring detection module is specially：Programmable device FPGA is by detecting that the DAA chips of DAA equipment are sent
The ring bell signals gone out；(example 25Hz) square-wave cycle of ring back tone is detected, ring bell signals continuous at least three are being detected
Individual square-wave cycle is judged as effective ring back tone within a preset range, then, is 1 effective ring back tone mark position, and record this and shake
The tone cycle and interruption is sent to processor, notifier processes device has ring generation, start simultaneously at the effective ring back tone of timing and continue
Time, empty ring back tone interval time；Such as detect the ring back tone cycle not within a preset range and no more than setting maximum when,
Then without operation, ring back tone cycle detection is re-started, original effective ring back tone mark invariant position is kept；If no more than three
Individual square-wave cycle within a preset range or the ring back tone cycle exceed setting maximum, then for do not occur also effective ring back tone or
Effective ring back tone has terminated, and is 0 effective ring back tone mark position, terminates effective ring back tone duration, starts timing ring
Sound interval time；If ring back tone interval time exceedes maximum, it is judged as that ring process has terminated, empties effective ring back tone
Duration, empty ring back tone square-wave cycle record；Simulation register is set inside FPGA simultaneously；Processor is set by bus
Put its square-wave cycle maximum, ring back tone square-wave cycle and preset range；Effective ring back tone duration also can be read simultaneously, has
Imitate ring flag bit, ring back tone interval time.
Refer to shown in Fig. 1 to Fig. 3, a kind of centralized ring detection method based on FPGA of the invention, methods described
One processor and a programmable device FPGA need to be provided；Simulation register and ring inspection are provided with the programmable device FPGA
Survey module；Methods described is specially：
Step 1, several DAA equipment is connected by respective FXO interfaces with programmable device FPGA；
The ring signal wires that step 2, the FXO interfaces of each DAA equipment are sent out, which are concentrated, sends programmable device FPGA to, leads to
Ring detection module is crossed, while effective ring back tone flag bit ring [0 of each road FXO interfaces:X], ring back tone square-wave cycle
Ring_hz, effective ring back tone duration cnt_ring [0:X] and ring back tone interval time cnt_noring [0:X] record
In simulation register,
Step 3, when effective ring, programmable device FPGA exports an interrupt INT # to processor, and processor leads to
Cross and collected in the data set that bus records programmable device FPGA, reach the effect of centralized transmission information；Simultaneous processor
Detection ring back tone the cycle ring_set_hz and cyclic swing scope ring_set_ for simulating register can be set by bus
range。
The processor is CPU or digital signal processor DSP.
The programmable device FPGA uses the IC chip of EP4CE6F17C8N models.(Programmable in actual applications
Part FPGA is not limited to the IC chip of EP4CE6F17C8N models) wherein, FPGA uses the IC cores of EP4CE6F17C8N models
Piece, the E9 pins of the IC chip and CPU GPI08 pins are connected, so when effective ring, programmable device FPGA output
Collected in the data set that one interrupt INT # records programmable device FPGA by bus to CPU, CPU, reach centralization and pass
Pass the effect of information.
The detection of the ring detection module is specially：Programmable device FPGA is by detecting that the DAA chips of DAA equipment are sent
The ring bell signals gone out；The square-wave cycle of ring back tone (example 25Hz) is detected, ring bell signals continuous at least three are being detected
Individual square-wave cycle is judged as effective ring back tone within a preset range, then, is 1 effective ring back tone mark position, and record this and shake
The tone cycle and interruption is sent to processor, notifier processes device has ring generation, start simultaneously at the effective ring back tone of timing and continue
Time, empty ring back tone interval time；Such as detect the ring back tone cycle not within a preset range and no more than setting maximum when,
Then without operation, ring back tone cycle detection is re-started, original effective ring back tone mark invariant position is kept；If no more than three
Individual square-wave cycle within a preset range or the ring back tone cycle exceed setting maximum, then for do not occur also effective ring back tone or
Effective ring back tone has terminated, and is 0 effective ring back tone mark position, terminates effective ring back tone duration, starts timing ring
Sound interval time；If ring back tone interval time exceedes maximum, it is judged as that ring process has terminated, empties effective ring back tone
Duration, empty ring back tone square-wave cycle record；Simulation register is set inside FPGA simultaneously；Processor is set by bus
Put its square-wave cycle maximum, ring back tone square-wave cycle and preset range；Effective ring back tone duration also can be read simultaneously, has
Imitate ring flag bit, ring back tone interval time.
In a word, the present invention is concentrated using FPGA and detected into line ringing, effective relatively low processor resource consume.Set simultaneously
FPGA internal simulation memories, concentrate to processor and carry out transmission information, and simultaneous processor can also be concentrated to FPGA and configure phase
Related parameter, is conducive to the speed of response.
The foregoing is only presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with
Modification, should all belong to the covering scope of the present invention.
Claims (8)
1. a kind of centralized ring detecting circuit based on FPGA, it is characterised in that：Including a processor and a programming device
FPGA；Simulation register and ring detection module are provided with the programmable device FPGA；The ring detection module and mould
Intend register connection, simulation register is connected by bus with processor；Several DAA equipment passes through respective FXO interfaces
It is connected with programmable device FPGA；The ring signal wires that the FXO interfaces of each DAA equipment are sent out are concentrated and send programming device to
FPGA, by ring detection module, while effective ring back tone flag bit ring [0 of each road FXO interfaces:X], ring back tone square wave
Cycle ring_hz, effective ring back tone duration cnt_ring [0:X] and ring back tone interval time cnt_noring [0:x]
Record is in simulation register, when effective ring, and programmable device FPGA exports an interrupt INT # to processor, processing
Collected in the data set that device records programmable device FPGA by bus, reach the effect of centralized transmission information；Locate simultaneously
Detection ring back tone the cycle ring_set_hz and cyclic swing scope ring_ for simulating register can be set by bus by managing device
set_range。
2. a kind of centralized ring detecting circuit based on FPGA according to claim 1, it is characterised in that：The processing
Device is CPU or digital signal processor DSP.
3. a kind of centralized ring detecting circuit based on FPGA according to claim 1, it is characterised in that：It is described to compile
Journey device FPGA uses the IC chip of EP4CE6F17C8N models.
4. a kind of centralized ring detecting circuit based on FPGA according to claim 1, it is characterised in that：The ring
The detection of detection module is specially：Programmable device FPGA is by detecting that the ring rings that the DAA chips of DAA equipment are sent out are believed
Number；The square-wave cycle of ring back tone is detected, continuous at least three square-wave cycle of ring bell signals is being detected within a preset range,
Then it is judged as effective ring back tone, is 1 effective ring back tone mark position, and record the ring back tone cycle and sent to processor
Interrupt, notifier processes device has ring generation, starts simultaneously at timing effective ring back tone duration, empty ring back tone interval time；
Such as detect the ring back tone cycle not within a preset range and no more than setting maximum when, then without operation, re-start and shake
Tone cycle detection, keeps original effective ring back tone mark invariant position；If no more than three square-wave cycles within a preset range
Or the ring back tone cycle exceedes the maximum of setting, then has terminated not occur effective ring back tone or effective ring back tone also, having
It is 0 to imitate ring back tone mark position, terminates effective ring back tone duration, starts timing ring back tone interval time；If ring back tone
Interval time exceedes maximum, then is judged as that ring process has terminated, empties effective ring back tone duration, empty ring back tone side
Wave period is recorded；Simulation register is set inside FPGA simultaneously；Processor sets its square-wave cycle maximum by bus, shakes
Tone square-wave cycle and preset range；Also it can be read between effective ring back tone duration, effective ring flag bit, ring back tone simultaneously
Every the time.
5. a kind of centralized ring detection method based on FPGA, it is characterised in that：Methods described need to provide a processor and one
Programmable device FPGA；Simulation register and ring detection module are provided with the programmable device FPGA；Methods described has
Body is：
Step 1, several DAA equipment is connected by respective FXO interfaces with programmable device FPGA；
The ring signal wires that step 2, the FXO interfaces of each DAA equipment are sent out, which are concentrated, sends programmable device FPGA to, by shaking
Bell detection module, while effective ring back tone flag bit ring [0 of each road FXO interfaces:X], ring back tone square-wave cycle ring_
Hz, effective ring back tone duration cnt_ring [0:X] and ring back tone interval time cnt_noring [0:X] record in simulation
In register,
Step 3, when effective ring, programmable device FPGA exports an interrupt INT # to processor, and processor passes through total
Collected in the data set of bundle of lines programmable device FPGA record, reach the effect of centralized transmission information；Simultaneous processor can lead to
Cross detection ring back tone cycle ring_set_hz and cyclic swing scope ring_set_ that bus sets simulation register
range。
6. a kind of centralized ring detection method based on FPGA according to claim 5, it is characterised in that：The processing
Device is CPU or digital signal processor DSP.
7. a kind of centralized ring detection method based on FPGA according to claim 5, it is characterised in that：It is described to compile
Journey device FPGA uses the IC chip of EP4CE6F17C8N models.
8. a kind of centralized ring detection method based on FPGA according to claim 5, it is characterised in that：The ring
The detection of detection module is specially：Programmable device FPGA is by detecting that the ring rings that the DAA chips of DAA equipment are sent out are believed
Number；The square-wave cycle of ring back tone is detected, continuous at least three square-wave cycle of ring bell signals is being detected within a preset range,
Then it is judged as effective ring back tone, is 1 effective ring back tone mark position, and record the ring back tone cycle and sent to processor
Interrupt, notifier processes device has ring generation, starts simultaneously at timing effective ring back tone duration, empty ring back tone interval time；
Such as detect the ring back tone cycle not within a preset range and no more than setting maximum when, then without operation, re-start and shake
Tone cycle detection, keeps original effective ring back tone mark invariant position；If no more than three square-wave cycles within a preset range
Or the ring back tone cycle exceedes the maximum of setting, then has terminated not occur effective ring back tone or effective ring back tone also, having
It is 0 to imitate ring back tone mark position, terminates effective ring back tone duration, starts timing ring back tone interval time；If ring back tone
Interval time exceedes maximum, then is judged as that ring process has terminated, empties effective ring back tone duration, empty ring back tone side
Wave period is recorded；Simulation register is set inside FPGA simultaneously；Processor sets its square-wave cycle maximum by bus, shakes
Tone square-wave cycle and preset range；Also it can be read between effective ring back tone duration, effective ring flag bit, ring back tone simultaneously
Every the time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510069417.8A CN104717369B (en) | 2015-02-10 | 2015-02-10 | A kind of centralized ring detecting circuit and its method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510069417.8A CN104717369B (en) | 2015-02-10 | 2015-02-10 | A kind of centralized ring detecting circuit and its method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104717369A CN104717369A (en) | 2015-06-17 |
| CN104717369B true CN104717369B (en) | 2017-07-28 |
Family
ID=53416301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510069417.8A Active CN104717369B (en) | 2015-02-10 | 2015-02-10 | A kind of centralized ring detecting circuit and its method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104717369B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105430200B (en) * | 2015-10-30 | 2018-08-03 | 广州芯德通信科技股份有限公司 | A kind of bell signal automatic test approach and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1157518A (en) * | 1995-12-26 | 1997-08-20 | 三星电子株式会社 | Ring detecting circuit and method for wireless/wired composite telephone |
| CN1193237A (en) * | 1997-03-07 | 1998-09-16 | 联华电子股份有限公司 | Device for detecting ringing and method therefor |
| CN1582564A (en) * | 2001-08-17 | 2005-02-16 | 印芬龙科技股份有限公司 | Telephone system with adjustable ringer voltage |
| CN201854342U (en) * | 2010-08-27 | 2011-06-01 | 索敬光 | Remote control device based on telephone ringing signals |
-
2015
- 2015-02-10 CN CN201510069417.8A patent/CN104717369B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1157518A (en) * | 1995-12-26 | 1997-08-20 | 三星电子株式会社 | Ring detecting circuit and method for wireless/wired composite telephone |
| CN1193237A (en) * | 1997-03-07 | 1998-09-16 | 联华电子股份有限公司 | Device for detecting ringing and method therefor |
| CN1582564A (en) * | 2001-08-17 | 2005-02-16 | 印芬龙科技股份有限公司 | Telephone system with adjustable ringer voltage |
| CN201854342U (en) * | 2010-08-27 | 2011-06-01 | 索敬光 | Remote control device based on telephone ringing signals |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104717369A (en) | 2015-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103440216B (en) | A kind of by I2C from the chip of equipment debugging MCU and method | |
| CN105357070A (en) | FPGA-based ARINC818 bus analysis and test apparatus | |
| CN105760612B (en) | Detection device, method, system, chip are asserted for chip checking after silicon | |
| CN105388805B (en) | Measurement and Control System based on spi bus | |
| CN104020704A (en) | Mini embedded controller device and method for simulating SPI interface through I/O port | |
| CN101799321A (en) | Intelligent vibration monitor system | |
| CN104200846B (en) | Embedded-type PROM test system and achieving method | |
| CN104717369B (en) | A kind of centralized ring detecting circuit and its method based on FPGA | |
| CN102565683B (en) | Generation and verification method of test vector | |
| CN105760558B (en) | The layout method of multi input look-up table in fpga chip | |
| CN204392386U (en) | A kind of centralized ring detecting circuit based on FPGA | |
| CN103500585B (en) | A kind of control circuit and its control method for being used to control single programmable memory | |
| CN105677474A (en) | Interruption polymerization device and method based on FPGA | |
| CN202855054U (en) | 3G (3rd generation telecommunication) wireless vibration data collection and transmission device | |
| CN203573309U (en) | Testing structure for embedded system memory | |
| CN203747856U (en) | Analog output controller used for Internet of things | |
| CN105740179A (en) | Parallel data acquisition system | |
| CN202205078U (en) | Multi-channel data acquisition equipment | |
| CN203745830U (en) | Digital output controller used for Internet of things | |
| CN102353408B (en) | Output signal detection circuit and detection method of dish-washing machine flowmeter | |
| CN205594621U (en) | A debugging for microcontroller | |
| CN207529165U (en) | A kind of electric network data handles acquisition system | |
| CN105389155A (en) | Method and system for receiving TDM audio data by using SPI interface | |
| CN202548205U (en) | Collecting and synchronizing device for welding current | |
| CN201892555U (en) | Fault remote prognosis system of electromagnetic flowmeter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information |
Inventor after: Gao Jifeng Inventor after: Zhu Yaquan Inventor before: Gao Jifeng |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |