CN105677474A - Interruption polymerization device and method based on FPGA - Google Patents
Interruption polymerization device and method based on FPGA Download PDFInfo
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- CN105677474A CN105677474A CN201610208926.9A CN201610208926A CN105677474A CN 105677474 A CN105677474 A CN 105677474A CN 201610208926 A CN201610208926 A CN 201610208926A CN 105677474 A CN105677474 A CN 105677474A
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- interruption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/48—Indexing scheme relating to G06F9/48
- G06F2209/483—Multiproc
Abstract
The invention provides an interruption polymerization device based on an FPGA (Field Programmable Gate Array). The interruption polymerization device comprises an FPGA unit, wherein the FPGA unit is respectively connected with a CPU and an SLIC chip for managing a plurality of FXS interfaces; the FPGA unit comprises an interruption detection unit and an analog register; the interruption detection unit is used for detecting if the interruption from the SLIC chip is valid at a time interval according to the configured interruption detection parameter; if yes, the value of a zone bit corresponding to the interruption is configured as 1 and written into the analog register; if not, the zone bit corresponding to the interruption in the analog register is reset; the analog register is used for storing the interruption zone bit of the SLIC chip; and the FPGA unit also can be used for receiving the interruption from the SLIC chip and outputting an interruption signal to a CPU when a non-zero zone bit exists in the analog register. The invention also provides an interruption polymerization method based on an FPGA, so as to reduce the waste of resource and time caused by CPU polling one by one and increase the response rate of CPU.
Description
Technical field
The present invention relates to signal processing technology field, particularly relate to a kind of interruption polyplant based on FPGA and method.
Background technology
Two FXS interfaces of each SLIC management of software ic, the inquiry of FXS interface interrupt is function common in daily utilization, such as dislodging machine testing etc. For large capacity equipment, with a lot of FXS interfaces, it is necessary to interrupt pin is more, it may appear that the problem that CPU pin is not enough.
Existing technology gives during CPU, CPU receive to have no progeny after being generally adopted interface interrupt signal " line with " needs interrupt source SLIC chip one by one, if FXS interface quantity is many, too much cpu resource can be taken, and poll is consuming time too much one by one, affect ageing, greatly reduce the CPU speed of response.
Summary of the invention
One of the technical problem to be solved in the present invention, is in that to provide a kind of interruption polyplant based on FPGA, it is achieved interrupt centralized detecting, reduces resource and waste of time that CPU poll one by one causes, is greatly improved the CPU speed of response.
One of the technical problem to be solved in the present invention is achieved in that a kind of interruption polyplant based on FPGA, and including FPGA unit, described FPGA unit is connected with the SLIC chip of a CPU and a plurality of management FXS interface respectively;
Described FPGA unit includes an interruption detection unit and a simulation depositor;
Whether the described detection unit that interrupts is for effective from the interruption of SLIC chip at interval of time detecting according to the interruption detection parameter in configuration, if, then the described value interrupting corresponding flag bit is set to 1 and writes in simulation depositor, otherwise, the flag bit that in described simulation depositor, this interruption is corresponding is reset;
Described simulation depositor is for storing the interrupt flag bit of described SLIC chip;
Described FPGA unit is additionally operable to receive from the interruption of SLIC chip and for exporting interrupt signal when simulating in depositor the flag bit that there is non-zero to CPU.
Further, the described detection unit that interrupts is additionally operable to interrupt stabilization filtration.
Further, described detection parameter of interrupting is the parameter pre-set in FPGA unit configuration, it is possible to modified by the CPU parameter transmitted.
Further, described detection parameter of interrupting includes detection interruption duration and middle power down bit virtual value.
Further, described FPGA unit is connected with CPU by bus, described bus by chip select CS#, write enable WE#, reading enable RE#, address AD D, data DATA and interrupt INT # and form.
The two of the technical problem to be solved in the present invention, are in that to provide a kind of interruption polymerization based on FPGA, it is achieved interrupt centralized detecting, reduce resource and waste of time that CPU poll one by one causes, are greatly improved the CPU speed of response.
The two of the technical problem to be solved in the present invention are achieved in that a kind of interruption polymerization based on FPGA, need to provide one with interrupting detection unit and the FPGA unit of simulation depositor, and described method comprises the steps:
Step 1, described FPGA unit are connected with the SLIC chip of a CPU and a plurality of management FXS interface respectively;
Whether step 2, described interruption detection unit be effective from the interruption of SLIC chip at interval of time detecting according to the interruption detection parameter in configuration, if, then the described value interrupting corresponding flag bit is set to 1 and writes in simulation depositor, otherwise, the flag bit that in described simulation depositor, this interruption is corresponding is reset;
Step 3, described FPGA unit judge the flag bit that whether there is non-zero in simulation depositor, if so, then export interrupt signal to described CPU, enter step 4; Otherwise, step 2 is jumped to;
Step 4, described CPU obtain the flag bit of all non-zeros in simulation depositor from FPGA unit after receiving interrupt signal, and do respective handling according to described flag bit.
Further, described step 2 judging, interrupting also carrying out interrupting stabilization whether effectively before filters.
Further, described detection parameter of interrupting is the parameter pre-set in FPGA unit configuration, it is possible to modified by the CPU parameter transmitted.
Further, described detection parameter of interrupting includes detection interruption duration and middle power down bit virtual value.
Further, described FPGA unit is connected with CPU by bus, described bus by chip select CS#, write enable WE#, reading enable RE#, address AD D, data DATA and interrupt INT # and form.
Present invention have the advantage that
1, connect CPU and SLIC chip by one with the FPGA unit interrupting detection unit and simulation depositor, to interrupting detecting and record, it is not necessary to take the too many pin of CPU, effectively reduce cpu resource consume;
2, FPGA belongs to hardware language, and speed is fast; Simultaneously by centralized detecting and centralized configuration, concentrate transmission information, it is achieved interrupt polymerization, CPU need not to interrupting carrying out poll one by one, just can directly obtain interrupting information, reduce the time spent by FXS quantity CPU of many times poll one by one, be greatly improved the speed of response;
3, simulation depositor is set inside FPGA unit, it is possible to communicate with CPU simply and effectively, reaches to interrupt the effect of polymerization;
4, interrupt signal is filtered screening by FPGA unit, it is possible to be prevented effectively from interruption erroneous judgement.
Accompanying drawing explanation
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is a kind of interruption polyplant principle schematic based on FPGA of the present invention.
Fig. 2 is that a kind of interruption polymerization based on FPGA of the present invention performs flow chart.
Fig. 3 is a kind of interruption overhaul flow chart interrupting polymerization based on FPGA of the present invention.
Detailed description of the invention
As shown in Figure 1, a kind of interruption polyplant based on FPGA of the present invention, including FPGA unit 1, described FPGA unit 1 is connected with the SLIC chip 3 of a CPU2 and a plurality of management FXS interface (not shown) respectively, described FPGA unit 1 is connected with CPU2 by bus, described bus by chip select CS#, write enable WE#, reading enable RE#, address AD D, data DATA and interrupt INT # and form;
Described FPGA unit 1 includes interruption detection unit 11 and a simulation depositor 12;
Whether the described detection unit 11 that interrupts is for effective from the interruption of SLIC chip 3 at interval of time detecting according to the interruption detection parameter in configuration, if, then the described value interrupting corresponding flag bit is set to 1 and writes in simulation depositor, otherwise, the flag bit that in described simulation depositor, this interruption is corresponding is reset; Described detection parameter of interrupting is the parameter pre-set in FPGA unit 1 configuration, and can be modified by the CPU2 parameter transmitted, when detection parameter is interrupted in needs amendment, by CPU2, parameter can be passed to FPGA unit to modify, otherwise directly use the parameter pre-set, thus effectively controlling detection, described interruption detects parameter and includes detection interruption duration (such as 10ms) and middle power down bit virtual value (such as arranging low level for effective middle power down bit); Described interruption detects unit 11 and is additionally operable to interrupt stabilization filtration, namely carries out stabilization detection before underway disconnected effective judgement, thus avoidance breakout erroneous judgement, the accuracy of judgement is interrupted in raising;
Described simulation depositor 12 is for storing the interrupt flag bit of described SLIC chip 3;
Described FPGA unit 1 is additionally operable to receive from the interruption of SLIC chip 3 and for exporting interrupt signal when simulating in depositor the flag bit that there is non-zero to CPU2.
The operation principle of described device is:
The interrupt INT signal that the SLIC chip of management FXS interface is sent is concentrated and is sent FPGA unit to, the interruption detection module of FPGA unit carries out stabilization at interval of the time and interrupts effectively detection, filter invalid interrupt signal, interruption effective marker position INT [0:X] on each road is recorded in described simulation depositor simultaneously, it is set to 1 by the value effectively interrupting corresponding flag bit and recorded in simulation depositor, interrupt invalid then respective flag place value being reset, when occurring effectively interrupting, namely simulation depositor occur when the flag bit interrupted is 1, FPGA unit one interrupt INT # of output is to CPU, then CPU is by the simulation depositor recorded data of bus inquiry FPGA unit, thus which FXS interface interrupt directly judges is, just the FXS interface interrupted can be interrupted concrete inquiry, without poll of taking time, thus being substantially reduced the efficiency of CPU, and CPU is not directly connected with SLIC, but it is directly connected to a FPGA unit, connect SLIC chip by PFGA unit and concentrate acquisition FXS interface interrupt, decrease the demand of CPU pin number.
As shown in Figures 2 and 3, a kind of interruption polymerization based on FPGA, one need to be provided with interrupting detection unit and the FPGA unit of simulation depositor, described method comprises the steps:
Step 1, described FPGA unit are connected with the SLIC chip of a CPU and a plurality of management FXS interface respectively, described FPGA unit is connected with CPU by bus, described bus by chip select CS#, write enable WE#, reading enable RE#, address AD D, data DATA and interrupt INT # and form;
Whether step 2, described interruption detection unit be effective from the interruption of SLIC at interval of time detecting according to the interruption detection parameter in configuration, if, then the described value interrupting corresponding flag bit is set to 1 and writes in simulation depositor, otherwise, the flag bit that in described simulation depositor, this interruption is corresponding is reset; Described detection parameter of interrupting is the parameter pre-set in FPGA unit configuration, and can be modified by the CPU parameter transmitted, when detection parameter is interrupted in needs amendment, by CPU, parameter can be passed to FPGA unit to modify, otherwise directly use the parameter pre-set, thus effectively controlling detection, described interruption detects parameter and includes detection interruption duration (such as 10ms) and middle power down bit virtual value (such as arranging low level for effective middle power down bit); Before judging whether effectively to interrupt, interrupt detection unit also carry out interrupting stabilization and filter, thus avoidance breakout erroneous judgement, improve the accuracy interrupting judging;
Step 3, described FPGA unit judge the flag bit that whether there is non-zero in simulation depositor, if so, then export interrupt signal to described CPU, enter step 4; Otherwise, step 2 is jumped to;
Step 4, described CPU obtain the flag bit of all non-zeros in simulation depositor from FPGA unit after receiving interrupt signal, and do respective handling according to described flag bit.
The present invention connects CPU and SLIC chip by one with the FPGA unit interrupting detection unit and simulation depositor, to interrupting detecting and record, it is not necessary to take the too many pin of CPU, effectively reduces cpu resource consume; FPGA belongs to hardware language, speed is fast, simultaneously by centralized detecting and centralized configuration, concentrate transmission information, realizing interrupting polymerization, CPU need not to interrupting carrying out poll one by one, so that it may directly obtains interrupting information, reduce the time spent by FXS quantity CPU of many times poll one by one, be greatly improved the speed of response; Simulation depositor is set inside FPGA unit, it is possible to communicate with CPU simply and effectively, reaches to interrupt the effect of polymerization; Interrupt signal is filtered screening by FPGA unit, it is possible to is prevented effectively from interruption erroneous judgement, improves interrupt response efficiency.
Although the foregoing describing the specific embodiment of the present invention; but those familiar with the art is to be understood that; we are merely exemplary described specific embodiment; rather than for the restriction to the scope of the present invention; those of ordinary skill in the art, in the equivalent modification made according to the spirit of the present invention and change, should be encompassed in the scope of the claimed protection of the present invention.
Claims (10)
1. the interruption polyplant based on FPGA, it is characterised in that: including FPGA unit, described FPGA unit is connected with the SLIC chip of a CPU and a plurality of management FXS interface respectively;
Described FPGA unit includes an interruption detection unit and a simulation depositor;
Whether the described detection unit that interrupts is for effective from the interruption of SLIC chip at interval of time detecting according to the interruption detection parameter in configuration, if, then the described value interrupting corresponding flag bit is set to 1 and writes in simulation depositor, otherwise, the flag bit that in described simulation depositor, this interruption is corresponding is reset;
Described simulation depositor is for storing the interrupt flag bit of described SLIC chip;
Described FPGA unit is additionally operable to receive from the interruption of SLIC chip and for exporting interrupt signal when simulating in depositor the flag bit that there is non-zero to CPU.
2. a kind of interruption polyplant based on FPGA according to claim 1, it is characterised in that: the described detection unit that interrupts is additionally operable to interrupt stabilization filtration.
3. a kind of interruption polyplant based on FPGA according to claim 1, it is characterised in that: described detection parameter of interrupting is the parameter pre-set in FPGA unit configuration, and the parameter transmitted by CPU is modified.
4. a kind of interruption polyplant based on FPGA according to claim 2, it is characterised in that: described detection parameter of interrupting includes detection interruption duration and middle power down bit virtual value.
5. a kind of interruption polyplant based on FPGA according to claim 1, it is characterized in that: described FPGA unit is connected with CPU by bus, described bus by chip select CS#, write enable WE#, reading enable RE#, address AD D, data DATA and interrupt INT # and form.
6. the interruption polymerization based on FPGA, it is characterised in that: need to providing one with interrupting detection unit and the FPGA unit of simulation depositor, described method comprises the steps:
Step 1, described FPGA unit are connected with the SLIC chip of a CPU and a plurality of management FXS interface respectively;
Whether step 2, described interruption detection unit be effective from the interruption of SLIC chip at interval of time detecting according to the interruption detection parameter in configuration, if, then the described value interrupting corresponding flag bit is set to 1 and writes in simulation depositor, otherwise, the flag bit that in described simulation depositor, this interruption is corresponding is reset;
Step 3, described FPGA unit judge the flag bit that whether there is non-zero in simulation depositor, if so, then export interrupt signal to described CPU, enter step 4; Otherwise, step 2 is jumped to;
Step 4, described CPU obtain the flag bit of all non-zeros in simulation depositor from FPGA unit after receiving interrupt signal, and do respective handling according to described flag bit.
7. a kind of interruption polymerization based on FPGA according to claim 6, it is characterised in that: described step 2 judging, interrupting also carrying out interrupting stabilization whether effectively before filters.
8. a kind of interruption polymerization based on FPGA according to claim 6, it is characterised in that: described detection parameter of interrupting is the parameter pre-set in FPGA unit configuration, and the parameter transmitted by CPU is modified.
9. a kind of interruption polymerization based on FPGA according to claim 7, it is characterised in that: described detection parameter of interrupting includes detection interruption duration and middle power down bit virtual value.
10. a kind of interruption polymerization based on FPGA according to claim 6, it is characterized in that: described FPGA unit is connected with CPU by bus, described bus by chip select CS#, write enable WE#, reading enable RE#, address AD D, data DATA and interrupt INT # and form.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610208926.9A CN105677474A (en) | 2016-04-06 | 2016-04-06 | Interruption polymerization device and method based on FPGA |
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| CN201610208926.9A CN105677474A (en) | 2016-04-06 | 2016-04-06 | Interruption polymerization device and method based on FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108549578A (en) * | 2017-12-25 | 2018-09-18 | 贵阳忆芯科技有限公司 | A kind of interruption polyplant and its method |
| CN112988228A (en) * | 2019-12-18 | 2021-06-18 | 珠海全志科技股份有限公司 | Control method and architecture for processor interrupt |
| CN113778684A (en) * | 2021-09-15 | 2021-12-10 | 中国电子科技集团公司第三十四研究所 | Multi-information-source-oriented FPGA and CPU data synchronization device and method |
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Patent Citations (6)
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| CN101937364A (en) * | 2009-06-30 | 2011-01-05 | 华为技术有限公司 | Interrupt synthesizing method and device |
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| CN108549578A (en) * | 2017-12-25 | 2018-09-18 | 贵阳忆芯科技有限公司 | A kind of interruption polyplant and its method |
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| CN113778684A (en) * | 2021-09-15 | 2021-12-10 | 中国电子科技集团公司第三十四研究所 | Multi-information-source-oriented FPGA and CPU data synchronization device and method |
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Application publication date: 20160615 |