CN104717369A - Centralized ringing detection circuit and method thereof based on FPGA - Google Patents
Centralized ringing detection circuit and method thereof based on FPGA Download PDFInfo
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- CN104717369A CN104717369A CN201510069417.8A CN201510069417A CN104717369A CN 104717369 A CN104717369 A CN 104717369A CN 201510069417 A CN201510069417 A CN 201510069417A CN 104717369 A CN104717369 A CN 104717369A
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Abstract
The invention provides a centralized ringing detection circuit based on FPGA, and the circuit comprises a processor and a programmable device FPGA; a simulation register and a ringing detection module are arranged in the programmable device FPGA; the ringing detection module is connected with the simulation register, and the simulation register is connected with the processor through a bus; multiple DAA devices are connected with the programmable device FPGA through FXO ports of the multiple DAA devices respectively. The invention further provides a centralized ringing detection method based on the FPGA, the processing to ringing signals transmitted from the multiple FXO ports can be achieved, the working efficiency is improved, and the resources of the processor are reduced.
Description
Technical field
The present invention relates to the ring detection technique field of FXO interface, particularly a kind of centralized ring detecting circuit based on FPGA and method thereof.
Background technology
FXO interface Self-sound-produced bell is the phenomenon often run in regular maintenance.Multiplely be born in thunderstorm rainy season, mainly because the moist short circuit of circuit, joint contact is bad, telephone wire partial short-circuit or electric leakage etc., and cause the change of line voltage distribution height obviously, FXO interface then thinks have signal to come in, thus produces false ringing phenomenon.
Existing technology uses stabilization or distributed ring detection method mostly, arrange anti-shaking method due to the time how long, affect the ring speed of response.And decentralized method, give CPU after the wired AND of general employing interface interrupt signal, having no progeny during CPU receives needs poll ring detection chip one by one, if FXO interface quantity is many, can take too much cpu resource.
Disclose one " device and method of detection ring " in prior art and see that publication number is: 1193237, publication date is: the Chinese patent of 1998-09-16, a kind of device detecting ring, and it comprises: a signal converter, accept a bell signal, export binary bit bell signal through conversion; One microprocessor, accepts the binary bit bell signal that described signal converter exports, and exports a ring number detected, wherein, described microprocessor comprises: a signal reader, accepts the binary bit bell signal of described signal converter, sampling output one sequence bell signal; One smoothing filter, accepts the sequence bell signal of described signal reader, removes high-frequency noise interference to export one with reference to bell signal; One arithmetic element, the zero passage calculated in the nearest secondary time period of reference the bell signal that described smoothing filter exports is counted and zero passage in the nearest time period is counted; One memory cell, the zero passage stored in nearest time time period that described arithmetic element calculates is counted and zero passage in the nearest time period is counted; One logic control element, the zero passage judging in described nearest time time period is counted and zero passage in the nearest time period is counted, to export the ring number of a ringing condition mark and described detection.The arrangement achieves the detection of ring, but this device can not carry out centralized detection to multiple FXO interfaces, therefore, need also to need to take too much cpu resource when detecting at multiple FXO interface.
Summary of the invention
One of the technical problem to be solved in the present invention, is to provide a kind of centralized ring detecting circuit based on FPGA; This circuit is that ring detection provides a hardware platform, and the bell signal that can be realized multiple FXO interface transmits in conjunction with existing software by this hardware platform is processed, and improves operating efficiency.
One of problem of the present invention is achieved in that a kind of centralized ring detecting circuit based on FPGA, comprises a processor and a programmable device FPGA, simulation register and ring detection module is provided with in described programmable device FPGA, described ring detection module is connected with simulation register, and simulation register is connected with processor by bus, several DAA equipment is connected with programmable device FPGA by respective FXO interface, the ring holding wire that the FXO interface of each DAA equipment is sent is concentrated and is sent programmable device FPGA to, by ring detection module, simultaneously effective ring back tone flag bit ring [0:x] of each road FXO interface, ring back tone square-wave cycle ring_hz, effective ring back tone duration cnt_ring [0:x] and ring back tone cnt_noring interval time [0:x] are recorded in simulation register, when effective ring, programmable device FPGA exports an interrupt INT # to processor, processor is collected the data centralization of programmable device FPGA record by bus, arrive the effect of centralized transmission of information, simultaneous processor arranges detection ring back tone cycle ring_set_hz and the cyclic swing scope ring_set_range of simulation register by bus.
Further, described processor is CPU or digital signal processor DSP.
Further, described programmable device FPGA adopts the IC chip of EP4CE6F17C8N model.
Further, the detection of described ring detection module is specially: the ring bell signal that programmable device FPGA is sent by the DAA chip detecting DAA equipment; Detect the square-wave cycle of ring back tone, detecting that continuous at least three square-wave cycle of ring bell signal are in preset range, then be judged as effective ring back tone, be 1 effective ring back tone mark position, and record this ring back tone cycle and send interruption to processor, notification processor has ring to produce, and starts timing effective ring back tone duration simultaneously, empties ring back tone interval time; As detected the ring back tone cycle not in preset range, then not operating, re-starting ring back tone cycle detection, keep original effective ring back tone flag bit constant; If be no more than three square-wave cycle in preset range or the ring back tone cycle exceed the maximum of setting, then for also not occurring that effective ring back tone or effective ring back tone have terminated, be 0 effective ring back tone mark position, terminate effective ring back tone duration, start timing ring back tone interval time; If ring back tone exceedes maximum interval time, ring process one end, empties effective ring back tone duration, empties ring back tone square-wave cycle record; Simulation register is set in FPGA inside simultaneously; Processor arranges its square-wave cycle maximum by bus, ring back tone square-wave cycle and preset range; Simultaneously also can read effective ring back tone duration, effective ring flag bit, ring back tone interval time.
The technical problem to be solved in the present invention two, is to provide a kind of centralized ring detection method based on FPGA; The bell signal that can realize multiple FXO interface transmits processes, and improves operating efficiency.
Two of problem of the present invention is achieved in that a kind of centralized ring detection method based on FPGA, and described method need provide a processor and a programmable device FPGA; Simulation register and ring detection module is provided with in described programmable device FPGA; Described method is specially:
Step 1, several DAA equipment to be connected with programmable device FPGA by respective FXO interface;
The ring holding wire that the FXO interface of step 2, each DAA equipment is sent is concentrated and is sent programmable device FPGA to, by ring detection module, effective ring back tone flag bit ring [0:x] of each road FXO interface, ring back tone square-wave cycle ring_hz, effectively ring back tone duration cnt_ring [0:x] and ring back tone cnt_noring interval time [0:x] are recorded in simulation register simultaneously
Step 3, when effective ring, programmable device FPGA exports an interrupt INT # to processor, and processor is collected the data centralization of programmable device FPGA record by bus, arrives the effect of centralized transmission of information; Simultaneous processor arranges detection ring back tone cycle ring_set_hz and the cyclic swing scope ring_set_range of simulation register by bus.
Further, described processor is CPU or digital signal processor DSP.
Further, described programmable device FPGA adopts the IC chip of EP4CE6F17C8N model.
Further, the detection of described ring detection module is specially: the ring bell signal that programmable device FPGA is sent by the DAA chip detecting DAA equipment; Detect the square-wave cycle of ring back tone, detecting that continuous at least three square-wave cycle of ring bell signal are in preset range, then be judged as effective ring back tone, be 1 effective ring back tone mark position, and record this ring back tone cycle and send interruption to processor, notification processor has ring to produce, and starts timing effective ring back tone duration simultaneously, empties ring back tone interval time; As detected the ring back tone cycle not in preset range, then not operating, re-starting ring back tone cycle detection, keep original effective ring back tone flag bit constant; If be no more than three square-wave cycle in preset range or the ring back tone cycle exceed the maximum of setting, then for also not occurring that effective ring back tone or effective ring back tone have terminated, be 0 effective ring back tone mark position, terminate effective ring back tone duration, start timing ring back tone interval time; If ring back tone exceedes maximum interval time, ring process one end, empties effective ring back tone duration, empties ring back tone square-wave cycle record; Simulation register is set in FPGA inside simultaneously; Processor arranges its square-wave cycle maximum by bus, ring back tone square-wave cycle and preset range; Simultaneously also can read effective ring back tone duration, effective ring flag bit, ring back tone interval time.
The invention has the advantages that: 1, by the centralized ring detection method based on FPGA, can effectively avoid processor resource to consume.
2, simulation register is set in FPGA inside, can simply effective must with processor communication, reach centralized detection, centralized configuration, concentrate the effect of transmission of information.
3, FPGA belongs to hardware language, and speed is fast.Simultaneously by centralized detecting, centralized configuration, concentrates transmission of information, avoid FXO interface quantity many time time of wasting of poll one by one, can effectively raise the efficiency.
4, by detecting continuous three square-wave cycle, the pulse interference signal occurring the just cycle once in a while can effectively be avoided.Simultaneously three square-wave cycle (routine 25hz) only have 120ms, greatly can shorten hundreds of millisecond set by stabilization to the operating lag of 1000 milliseconds.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Fig. 2 is schematic flow sheet of the present invention.
Fig. 3 is the schematic flow sheet that ring detection module of the present invention realizes.
Embodiment
Refer to shown in Fig. 1 to Fig. 3, a kind of centralized ring detecting circuit based on FPGA, comprises a processor and a programmable device FPGA, simulation register and ring detection module is provided with in described programmable device FPGA, described ring detection module is connected with simulation register, and simulation register is connected with processor by bus, several DAA equipment is connected with programmable device FPGA by respective FXO interface, the ring holding wire that the FXO interface of each DAA equipment is sent is concentrated and is sent programmable device FPGA to, by ring detection module, simultaneously effective ring back tone flag bit ring [0:x] of each road FXO interface, ring back tone square-wave cycle ring_hz, effective ring back tone duration cnt_ring [0:x] and ring back tone cnt_noring interval time [0:x] are recorded in simulation register, when effective ring, programmable device FPGA exports an interrupt INT # to processor, processor is collected the data centralization of programmable device FPGA record by bus, arrive the effect of centralized transmission of information, programmable device FPGA is concentrated these record data and is sent processor to by bus, and processor carries out check processing, simultaneous processor arranges detection ring back tone cycle ring_set_hz and the cyclic swing scope ring_set_range of simulation register by bus.
Wherein, described processor is CPU or digital signal processor DSP.
Described programmable device FPGA adopts the IC chip of EP4CE6F17C8N model.
The detection of described ring detection module is specially: the ring bell signal that programmable device FPGA is sent by the DAA chip detecting DAA equipment; Detect (routine 25Hz) square-wave cycle of ring back tone, detecting that continuous at least three square-wave cycle of ring bell signal are in preset range, then be judged as effective ring back tone, be 1 effective ring back tone mark position, and record this ring back tone cycle and send interruption to processor, notification processor has ring to produce, and starts timing effective ring back tone duration simultaneously, empties ring back tone interval time; As detected the ring back tone cycle not in preset range, then not operating, re-starting ring back tone cycle detection, keep original effective ring back tone flag bit constant; If be no more than three square-wave cycle in preset range or the ring back tone cycle exceed the maximum of setting, then for also not occurring that effective ring back tone or effective ring back tone have terminated, be 0 effective ring back tone mark position, terminate effective ring back tone duration, start timing ring back tone interval time; If ring back tone exceedes maximum interval time, ring process one end, empties effective ring back tone duration, empties ring back tone square-wave cycle record; Simulation register is set in FPGA inside simultaneously; Processor arranges its square-wave cycle maximum by bus, ring back tone square-wave cycle and preset range; Simultaneously also can read effective ring back tone duration, effective ring flag bit, ring back tone interval time.
Refer to a kind of centralized ring detection method based on FPGA of the present invention shown in Fig. 1 to Fig. 3, described method need provide a processor and a programmable device FPGA; Simulation register and ring detection module is provided with in described programmable device FPGA; Described method is specially:
Step 1, several DAA equipment to be connected with programmable device FPGA by respective FXO interface;
The ring holding wire that the FXO interface of step 2, each DAA equipment is sent is concentrated and is sent programmable device FPGA to, by ring detection module, effective ring back tone flag bit ring [0:x] of each road FXO interface, ring back tone square-wave cycle ring_hz, effectively ring back tone duration cnt_ring [0:x] and ring back tone cnt_noring interval time [0:x] are recorded in simulation register simultaneously
Step 3, when effective ring, programmable device FPGA exports an interrupt INT # to processor, and processor is collected the data centralization of programmable device FPGA record by bus, arrives the effect of centralized transmission of information; Simultaneous processor arranges detection ring back tone cycle ring_set_hz and the cyclic swing scope ring_set_range of simulation register by bus.
Described processor is CPU or digital signal processor DSP.
Described programmable device FPGA adopts the IC chip of EP4CE6F17C8N model.(programmable device FPGA is not defined as the IC chip of EP4CE6F17C8N model in actual applications) wherein, FPGA adopts the IC chip of EP4CE6F17C8N model, the E9 pin of this IC chip is connected with the GPI08 pin of CPU, like this when effective ring, programmable device FPGA exports an interrupt INT # to CPU, CPU is collected the data centralization of programmable device FPGA record by bus, arrives the effect of centralized transmission of information.
The detection of described ring detection module is specially: the ring bell signal that programmable device FPGA is sent by the DAA chip detecting DAA equipment; Detect the square-wave cycle of ring back tone (routine 25Hz), detecting that continuous at least three square-wave cycle of ring bell signal are in preset range, then be judged as effective ring back tone, be 1 effective ring back tone mark position, and record this ring back tone cycle and send interruption to processor, notification processor has ring to produce, and starts timing effective ring back tone duration simultaneously, empties ring back tone interval time; As detected the ring back tone cycle not in preset range, then not operating, re-starting ring back tone cycle detection, keep original effective ring back tone flag bit constant; If be no more than three square-wave cycle in preset range or the ring back tone cycle exceed the maximum of setting, then for also not occurring that effective ring back tone or effective ring back tone have terminated, be 0 effective ring back tone mark position, terminate effective ring back tone duration, start timing ring back tone interval time; If ring back tone exceedes maximum interval time, ring process one end, empties effective ring back tone duration, empties ring back tone square-wave cycle record; Simulation register is set in FPGA inside simultaneously; Processor arranges its square-wave cycle maximum by bus, ring back tone square-wave cycle and preset range; Simultaneously also can read effective ring back tone duration, effective ring flag bit, ring back tone interval time.
In a word, the present invention uses FPGA to concentrate to carry out ring detection, the reason device resource consume of effective lower.Arrange FPGA internal simulation memory simultaneously, concentrate and carry out transmission of information to processor, simultaneous processor also can be concentrated and configure relevant parameter to FPGA, is conducive to the speed of response.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (8)
1. based on a centralized ring detecting circuit of FPGA, it is characterized in that: comprise a processor and a programmable device FPGA, simulation register and ring detection module is provided with in described programmable device FPGA, described ring detection module is connected with simulation register, and simulation register is connected with processor by bus, several DAA equipment is connected with programmable device FPGA by respective FXO interface, the ring holding wire that the FXO interface of each DAA equipment is sent is concentrated and is sent programmable device FPGA to, by ring detection module, simultaneously effective ring back tone flag bit ring [0:x] of each road FXO interface, ring back tone square-wave cycle ring_hz, effective ring back tone duration cnt_ring [0:x] and ring back tone cnt_noring interval time [0:x] are recorded in simulation register, when effective ring, programmable device FPGA exports an interrupt INT # to processor, processor is collected the data centralization of programmable device FPGA record by bus, arrive the effect of centralized transmission of information, simultaneous processor arranges detection ring back tone cycle ring_set_hz and the cyclic swing scope ring_set_range of simulation register by bus.
2. a kind of centralized ring detecting circuit based on FPGA according to claim 1, is characterized in that: described processor is CPU or digital signal processor DSP.
3. a kind of centralized ring detecting circuit based on FPGA according to claim 1, is characterized in that: described programmable device FPGA adopts the IC chip of EP4CE6F 17C8N model.
4. a kind of centralized ring detecting circuit based on FPGA according to claim 1, is characterized in that: the detection of described ring detection module is specially: the ring bell signal that programmable device FPGA is sent by the DAA chip detecting DAA equipment; Detect the square-wave cycle of ring back tone, detecting that continuous at least three square-wave cycle of ring bell signal are in preset range, then be judged as effective ring back tone, be 1 effective ring back tone mark position, and record this ring back tone cycle and send interruption to processor, notification processor has ring to produce, and starts timing effective ring back tone duration simultaneously, empties ring back tone interval time; As detected the ring back tone cycle not in preset range, then not operating, re-starting ring back tone cycle detection, keep original effective ring back tone flag bit constant; If be no more than three square-wave cycle in preset range or the ring back tone cycle exceed the maximum of setting, then for also not occurring that effective ring back tone or effective ring back tone have terminated, be 0 effective ring back tone mark position, terminate effective ring back tone duration, start timing ring back tone interval time; If ring back tone exceedes maximum interval time, ring process one end, empties effective ring back tone duration, empties ring back tone square-wave cycle record; Simulation register is set in FPGA inside simultaneously; Processor arranges its square-wave cycle maximum by bus, ring back tone square-wave cycle and preset range; Simultaneously also can read effective ring back tone duration, effective ring flag bit, ring back tone interval time.
5. based on a centralized ring detection method of FPGA, it is characterized in that: described method need provide a processor and a programmable device FPGA; Simulation register and ring detection module is provided with in described programmable device FPGA; Described method is specially:
Step 1, several DAA equipment to be connected with programmable device FPGA by respective FXO interface;
The ring holding wire that the FXO interface of step 2, each DAA equipment is sent is concentrated and is sent programmable device FPGA to, by ring detection module, effective ring back tone flag bit ring [0:x] of each road FXO interface, ring back tone square-wave cycle ring_hz, effectively ring back tone duration cnt_ring [0:x] and ring back tone cnt_noring interval time [0:x] are recorded in simulation register simultaneously
Step 3, when effective ring, programmable device FPGA exports an interrupt INT # to processor, and processor is collected the data centralization of programmable device FPGA record by bus, arrives the effect of centralized transmission of information; Simultaneous processor arranges detection ring back tone cycle ring_set_hz and the cyclic swing scope ring_set_range of simulation register by bus.
6. a kind of centralized ring detection method based on FPGA according to claim 5, is characterized in that: described processor is CPU or digital signal processor DSP.
7. a kind of centralized ring detection method based on FPGA according to claim 5, is characterized in that: described programmable device FPGA adopts the IC chip of EP4CE6F 17C8N model.
8. a kind of centralized ring detection method based on FPGA according to claim 5, is characterized in that: the detection of described ring detection module is specially: the ring bell signal that programmable device FPGA is sent by the DAA chip detecting DAA equipment; Detect the square-wave cycle of ring back tone, detecting that continuous at least three square-wave cycle of ring bell signal are in preset range, then be judged as effective ring back tone, be 1 effective ring back tone mark position, and record this ring back tone cycle and send interruption to processor, notification processor has ring to produce, and starts timing effective ring back tone duration simultaneously, empties ring back tone interval time; As detected the ring back tone cycle not in preset range, then not operating, re-starting ring back tone cycle detection, keep original effective ring back tone flag bit constant; If be no more than three square-wave cycle in preset range or the ring back tone cycle exceed the maximum of setting, then for also not occurring that effective ring back tone or effective ring back tone have terminated, be 0 effective ring back tone mark position, terminate effective ring back tone duration, start timing ring back tone interval time; If ring back tone exceedes maximum interval time, ring process one end, empties effective ring back tone duration, empties ring back tone square-wave cycle record; Simulation register is set in FPGA inside simultaneously; Processor arranges its square-wave cycle maximum by bus, ring back tone square-wave cycle and preset range; Simultaneously also can read effective ring back tone duration, effective ring flag bit, ring back tone interval time.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105430200A (en) * | 2015-10-30 | 2016-03-23 | 广州市芯德电子技术有限公司 | Automatic ringing signal test system, method and device |
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| CN1157518A (en) * | 1995-12-26 | 1997-08-20 | 三星电子株式会社 | Ring detecting circuit and method for wireless/wired composite telephone |
| CN1193237A (en) * | 1997-03-07 | 1998-09-16 | 联华电子股份有限公司 | Device for detecting ringing and method therefor |
| CN1582564A (en) * | 2001-08-17 | 2005-02-16 | 印芬龙科技股份有限公司 | Telephone system with adjustable ringer voltage |
| CN201854342U (en) * | 2010-08-27 | 2011-06-01 | 索敬光 | Remote control device based on telephone ringing signals |
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2015
- 2015-02-10 CN CN201510069417.8A patent/CN104717369B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1157518A (en) * | 1995-12-26 | 1997-08-20 | 三星电子株式会社 | Ring detecting circuit and method for wireless/wired composite telephone |
| CN1193237A (en) * | 1997-03-07 | 1998-09-16 | 联华电子股份有限公司 | Device for detecting ringing and method therefor |
| CN1582564A (en) * | 2001-08-17 | 2005-02-16 | 印芬龙科技股份有限公司 | Telephone system with adjustable ringer voltage |
| CN201854342U (en) * | 2010-08-27 | 2011-06-01 | 索敬光 | Remote control device based on telephone ringing signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105430200A (en) * | 2015-10-30 | 2016-03-23 | 广州市芯德电子技术有限公司 | Automatic ringing signal test system, method and device |
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