CN104716141B - Low N-type buries the structure and manufacturing method of the mask read-only memory of source and drain resistance - Google Patents
Low N-type buries the structure and manufacturing method of the mask read-only memory of source and drain resistance Download PDFInfo
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- CN104716141B CN104716141B CN201310689304.9A CN201310689304A CN104716141B CN 104716141 B CN104716141 B CN 104716141B CN 201310689304 A CN201310689304 A CN 201310689304A CN 104716141 B CN104716141 B CN 104716141B
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Abstract
The invention discloses the manufacturing method that a kind of low N-type buries the mask read-only memory of source and drain resistance, step includes：1）Shallow isolation trench is formed, p-well injection is carried out；2）It is coated with the photoresist that the first N-type buries source and drain, the distance between photoresist is less than target size, and exposure carries out arsenic ion or phosphonium ion injection, forms the first N-type and bury source and drain；3）Part photoresist is removed, the distance between photoresist is made to be equal to target size；4）Arsenic ion injection is carried out, formation buries the second N-type that source and drain is connected with the first N-type and buries source and drain；5）Form grid oxygen, polysilicon gate and gate isolation side wall.The invention also discloses the structures of the mask read-only memory made in aforementioned manners.For the present invention using the method injected twice, the N-type for forming special T-shaped structure buries source and drain, in the case where holding source and drain width is constant, length of effective channel is unaffected, the depth of source and drain is increased, to reduce the source and drain resistance of mask read-only memory.
Description
Technical field
The present invention relates to IC manufacturing field, the structure more particularly to mask read-only memory and its manufacturer
Method.
Background technology
Read-only memory（Read-Only Memory）It is a kind of memory that can only read data.The number of this memory
It is written according to when production.In the fabrication process, by data with a special light shield（mask）Burning in circuit, so
Sometimes referred to as it is " mask read-only memory "（mask ROM）.Actually it like CD CDs principle, in the light of semiconductor
It is written with data mode during carving technology.
The data of this mask read-only memory cannot be changed after write, so data can not possibly lose, and
And its manufacturing cost is very low, therefore, in the equipment for not needing data update, Mask ROM are by very extensive use.
But this mask read-only memory is also obviously in technologic disadvantage.As shown in Figure 1, in order to
High device density is realized as far as possible, and the grid and source and drain of device are all strips, spaced one by one.Grid and source
It is mutually perpendicular between drain electrode.This structure feature is limited can not use current deep submicron process in conventional technique manufacture
In the silicon metallizing process that generally uses reduce the dead resistance of device, the no short circuit it will cause between adjacent source and drain.Cause
The resistance and source and drain resistance of this device are very big, hundreds of times bigger than the dead resistance of usual conventional CMOS devices.Together
When grid and source and drain be all strip, current path is not only narrow but also long, and which greatly limits the readings of mask read-only memory
Electric current, while circuit is also restrained in terms of reading signal speed（RC retardation ratio is big）.
Invention content
One of the technical problem to be solved in the present invention is to provide the mask read-only memory that a kind of low N-type buries source and drain resistance
Manufacturing method, it can reduce the source and drain resistance of mask read-only memory.
In order to solve the above technical problems, the low N-type of the present invention buries the manufacturer of the mask read-only memory of source and drain resistance
Method, step include：
1）Shallow isolation trench is formed on silicon substrate active area with prior art, and carries out p-well injection；
2）It is coated with the first N-type and the distance between buries the photoresist of source and drain, and make photoresist and be less than target size, exposure carries out arsenic
Ion or phosphonium ion injection, form the first N-type and bury source and drain；
3）Part photoresist is removed, the distance between photoresist is made to be equal to target size；
4）Arsenic ion injection is carried out, formation buries the second N-type that source and drain is connected with the first N-type and buries source and drain；
5）Grid oxygen, polysilicon gate and gate isolation side wall are formed with prior art, completes the system of mask read-only memory
Make.
The step 4）Step 2 described in the energy ratio of injection）The energy of injection is low.
The second technical problem to be solved by the present invention is to provide the light shield that the low N-type manufactured in aforementioned manners buries source and drain resistance
The structure of formula read-only memory.The N-type of the mask read-only memory buries source and drain in the T-shaped structure of section along grid direction,
The first N-type including being connected with each other buries source and drain and the second N-type buries source and drain.
First N-type buries source and drain, and than the second N-type to bury source and drain deep and narrow.
For the present invention using the method injected twice, the N-type for forming special T-shaped structure buries source and drain, is keeping source and drain width
In the case that constant, length of effective channel is unaffected, the depth of source and drain is increased, to reduce mask read-only memory
Source and drain resistance.
Description of the drawings
Fig. 1 is traditional mask read-only memory vertical view.
Fig. 2 is the sectional view that traditional mask read-only memory buries source and drain direction along N-type.
Fig. 3 is sectional view of traditional mask read-only memory along grid direction.
Fig. 4~Fig. 9 is the manufacturing process flow schematic diagram of the mask read-only memory of the embodiment of the present invention.Wherein, Fig. 9
It is sectional view of the mask read-only memory produced by the present invention along grid direction.
Specific implementation mode
There is more specific understanding for technology contents, feature and effect to the present invention, in conjunction with attached drawing, details are as follows：
The low N-type of the present invention buries the manufacturing method of the mask read-only memory of source and drain resistance, and specific process step is such as
Under：
Step 1, shallow isolation trench is formed on the active area of silicon substrate, mask read-only memory region and periphery is isolated
Circuit, as shown in Figure 4.
Step 2, p-well injection is carried out in the active area of mask read-only memory, the active area in p-well is formed, such as Fig. 5 institutes
Show（B figures are the vertical view after the completion of this step）.
Step 3, to be formed the first N-type bury other than the region of source and drain place coating the first photoresist, the first photoresist
The distance between i.e. critical size（Critical Dimension）Less than target size, then exposure carries out first time energy
Larger high dose arsenic ion or phosphonium ion injection（63~116keV of Implantation Energy, implantation dosage 3.3E14~5.7E15/
cm2）, deeper N-doped zone is formed, i.e. the first N-type buries source and drain, as shown in Figure 6.
Step 4, oxygen is led to the first photoresist, carries out partial oxidation and removes photoresist（trimming）, the second photoresist is formed, is such as schemed
Shown in 7.The distance between second photoresist is that critical size is equal to target size.Dotted line in Fig. 7 is original first photoresist
Coating range.
Step 5, second of energy ratio high dose arsenic ion implanting low for the first time is carried out（21~62keV of Implantation Energy, note
Enter 4.3E14~6.7E15/cm of dosage2）, formed shallower but bury the second wide N-type of source and drain than the first N-type and bury source and drain, such as Fig. 8
It is shown.First N-type, which buries source and drain and buries source and drain with the second N-type, to be connected, and ultimately forms the T shape source and drain of mask read-only memory.
Since the N-type that the N-type of the T-shaped structure buries the width of source and drain and conventional mask read-only memory buries the width of source and drain
Unanimously, the distance between source and drain is that the length of effective channel of mask read-only memory still remains unchanged, therefore will not lead to device
Part short circuit or leakage current increase.Simultaneously as when not having metal silicide, the size of the N-type source and drain resistance of device is main
Depending on the width and depth of source and drain, in the case where the width of source and drain remains unchanged, the intensification of source and drain depth greatly reduces
The dead resistance of source and drain thereby reduces the RC retardation ratio of circuit, improves reading electric current and the reading of mask read-only memory
Speed.
Step 6, grid oxygen oxidation is carried out；Grid polycrystalline silicon is deposited, and etches the polysilicon for forming mask read-only memory
Grid；Deposition thickness isSilica dioxide medium layer, and return carve form gate isolation side wall.It is finally formed
The structure of mask read-only memory is as shown in Figure 9.
Claims (5)
1. low N-type buries the manufacturing method of the mask read-only memory of source and drain resistance, which is characterized in that step includes：
1) shallow isolation trench is formed on silicon substrate active area with prior art, and carry out p-well injection；
2) the first N-type of coating, which the distance between buries the photoresist of source and drain, and makes photoresist, is less than target size, and exposure carries out arsenic ion
Or phosphonium ion injection, it forms the first N-type and buries source and drain；Implantation dosage is 3.3E14~5.7E15/cm2；
3) part photoresist is removed, the distance between photoresist is made to be equal to target size；
4) arsenic ion injection is carried out, formation buries the second N-type that source and drain is connected with the first N-type and buries source and drain；Implantation dosage is 4.3E14
~6.7E15/cm2；
5) grid oxygen, polysilicon gate and gate isolation side wall are formed with prior art, completes the making of mask read-only memory.
2. according to the method described in claim 1, it is characterized in that, step 2), Implantation Energy are 63~116keV.
3. according to the method described in claim 1, it is characterized in that, step 3), part photoresist is removed using the method for oxidation.
4. according to the method described in claim 1, it is characterized in that, the energy of the energy ratio step 2) injection of step 4) injection
Low, the second N-type buries source and drain, and than the first N-type to bury source and drain shallow and wide.
5. according to the method described in claim 4, it is characterized in that, step 4), Implantation Energy are 21~62keV.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689304.9A CN104716141B (en) | 2013-12-16 | 2013-12-16 | Low N-type buries the structure and manufacturing method of the mask read-only memory of source and drain resistance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689304.9A CN104716141B (en) | 2013-12-16 | 2013-12-16 | Low N-type buries the structure and manufacturing method of the mask read-only memory of source and drain resistance |
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| CN104716141A CN104716141A (en) | 2015-06-17 |
| CN104716141B true CN104716141B (en) | 2018-08-21 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423324A (en) * | 2001-12-05 | 2003-06-11 | 联华电子股份有限公司 | Method for making concealed potential source line of cover curtain type read-only memory |
| CN1466220A (en) * | 2002-07-03 | 2004-01-07 | �����ɷ� | Embedded bit line structure and mfg. method thereof |
| CN1472796A (en) * | 2002-08-02 | 2004-02-04 | 上海宏力半导体制造有限公司 | Method for forming metal silicide in shielded read-only memory |
| US7087488B2 (en) * | 2004-07-16 | 2006-08-08 | United Microelectronics Corp. | Method for fabricating a mask ROM |
-
2013
- 2013-12-16 CN CN201310689304.9A patent/CN104716141B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423324A (en) * | 2001-12-05 | 2003-06-11 | 联华电子股份有限公司 | Method for making concealed potential source line of cover curtain type read-only memory |
| CN1466220A (en) * | 2002-07-03 | 2004-01-07 | �����ɷ� | Embedded bit line structure and mfg. method thereof |
| CN1472796A (en) * | 2002-08-02 | 2004-02-04 | 上海宏力半导体制造有限公司 | Method for forming metal silicide in shielded read-only memory |
| US7087488B2 (en) * | 2004-07-16 | 2006-08-08 | United Microelectronics Corp. | Method for fabricating a mask ROM |
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| CN104716141A (en) | 2015-06-17 |
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