CN103715146B - The manufacture method of flash memory - Google Patents
The manufacture method of flash memory Download PDFInfo
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- CN103715146B CN103715146B CN201210378841.7A CN201210378841A CN103715146B CN 103715146 B CN103715146 B CN 103715146B CN 201210378841 A CN201210378841 A CN 201210378841A CN 103715146 B CN103715146 B CN 103715146B
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- layer
- isolation structure
- remove
- patterned mask
- flash memory
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
Abstract
A kind of manufacture method of flash memory.Substrate is provided, substrate is formed in patterned mask layer, and substrate and is formed with isolation structure, wherein the end face of isolation structure and the end face copline of patterned mask layer.Performing etching technique, etching technics includes: remove partially patterned mask layer；And remove the portions of isolation structure of the corner of adjacent pattern mask layer, so that the width of the top section of isolation structure is less than the width of base section.Repeat etching technics at least one times.Remove patterned mask layer.Substrate is formed the first dielectric layer.First dielectric layer is formed the first conductor layer.Remove part the first conductor layer and portions of isolation structure.First conductor layer with isolation structure form the second dielectric layer.Second dielectric layer is formed the second conductor layer.
Description
Technical field
The invention relates to the manufacture method of a kind of electronic component, and in particular to a kind of flash memory
Manufacture method.
Background technology
Flash memory (Flash Memory) is that a kind of consumption electric power that need not just can preserve the non-volatile of data
Property storage arrangement, it can the most repeatedly be deleted or write.Additionally, deposit compared to other
Reservoir device, flash memory has relatively low reading delay, dynamic shock resistance, write mass data
Time there is significant speed advantage and there is preferable cost structure, the most become non-volatile solid
State stores the technology the most widely adopted, such as, can be applicable to notebook computer, numeral walkman, numeral
In the Related products such as camera, mobile phone, game host.
Figure 1A to Fig. 1 C is the Making programme profile of existing flash element.First, refer to
Figure 1A, forms multiple isolation structure of shallow trench 102 in substrate 100, to define action zone 105.
Then, refer to Figure 1B, the substrate 100 of action zone 105 sequentially forms tunneling dielectric
Layer 104 and polysilicon layer 106.Along with the micro of technique, the width of action zone 105 reduces the most therewith.
Therefore, after forming polysilicon layer 106 with depositing operation, polysilicon layer 106 often produces
Hole (seam) 110.Then, remove part isolation structure of shallow trench 102, to expose polysilicon
The partial sidewall of layer 106.Afterwards, dielectric layer 108 between grid is formed on the substrate 100.Due to polycrystalline
Having hole 110 in silicon layer 106, therefore when forming dielectric layer 108 between grid, dielectric material will be
Hole 110 is piled up.
Then, refer to Fig. 1 C, form polysilicon layer 112 on the substrate 100.Afterwards, figure is carried out
Case metallization processes, to define a plurality of wordline.Fig. 2 is to carry out the vertical view after the step described in Fig. 1 C
Schematic diagram, wherein Fig. 1 C is the profile of I-I ' hatching line along Fig. 2.As in figure 2 it is shown, by polysilicon
After layer 112 and film pattern below, define a plurality of wordline 216.
But, there is dielectric material, therefore by polysilicon layer 112 pattern owing to hole 110 being piled up
After change, the substrate 100 between wordline 216 can produce residual structural 218 (dielectric material and/
Or polycrystalline silicon material, this polycrystalline silicon material branch in the middle part of follow-up thermal process is oxidized to oxidation
Thing).Consequently, it is possible to after forming contact hole on follow-up substrate 100 between wordline 216,
These residual structural 218 can cause contact hole electrical on problem, and then affect element efficiency.
Summary of the invention
In view of this, the present invention proposes the manufacture method of a kind of flash memory, can avoid as floating grid
Conductor layer produces hole.
The present invention provides the manufacture method of a kind of flash memory.Substrate is provided, substrate is formed patterning and covers
Mold layer, and substrate are formed isolation structure.The end face of isolation structure and the end face of patterned mask layer
Copline.Performing etching technique, etching technics includes: remove partially patterned mask layer；Remove neighbour
The portions of isolation structure of the corner of nearly patterned mask layer, so that the width of the top section of isolation structure
Degree is less than the width of base section.Repeat etching technics at least one times.Remove patterned mask layer.?
The first dielectric layer is formed on substrate.First dielectric layer is formed the first conductor layer.Remove part first
Conductor layer and portions of isolation structure.First conductor layer with isolation structure form the second dielectric layer.?
The second conductor layer is formed on second dielectric layer.
In one embodiment of this invention, the forming method of the first above-mentioned conductor layer is e.g. first at lining
Forming conductor material layer, conductor material layer covers isolation structure at the end.Then, carry out flatening process,
Remove segment conductor material layer and remove the top section of isolation structure.
In one embodiment of this invention, the above-mentioned method removing partially patterned mask layer is e.g.
Hot phosphoric acid is used to carry out wet etching.
In one embodiment of this invention, the thickness that in above-mentioned etching technics, patterned mask layer is removed
Degree such as betweenExtremelyBetween.
In one embodiment of this invention, the portion of the above-mentioned corner removing adjacent pattern mask layer
The method dividing isolation structure e.g. uses the Fluohydric acid. of dilution to carry out wet etching.
In one embodiment of this invention, the thickness example that in above-mentioned etching technics, isolation structure is removed
As betweenExtremelyBetween.
In one embodiment of this invention, the above-mentioned forming method stating isolation structure is e.g. first to scheme
Case mask layer is mask, removes section substrate, to form raceway groove.Then, substrate is formed every
From material layer, and fill up raceway groove.Afterwards, carry out flatening process, remove the isolated material outside raceway groove
Layer.
In one embodiment of this invention, after carrying out flatening process and performing etching technique
Before, it is also possible to remove portions of isolation structure.
In one embodiment of this invention, after removing patterned mask layer and formation first Jie
Before electric layer, it is also possible to carry out oxidation technology, to form sacrificial oxide layer on substrate.Then, move
Except sacrificial oxide layer.
In one embodiment of this invention, the above-mentioned method removing sacrificial oxide layer e.g. uses dilute
The Fluohydric acid. released carries out wet etching.
Based on above-mentioned, by carrying out the etching technics of more than twice, (this etching technics includes one to the present invention
Secondary patterned mask layer etching processing and an isolation structure etching processing) so that adjacent isolation junction
There is between the top section of structure relatively wide distance, thus leading as floating grid can be avoided the formation of
During body layer, this conductor layer produces hole.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and join
Close appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 C is the Making programme profile according to the flash memory depicted in prior art, its
Middle Fig. 1 C is the profile depicted in I-I ' line according to Fig. 2.
Fig. 2 is the schematic top plan view carrying out the flash memory after the step described in Fig. 1 C.
Fig. 3 A to Fig. 3 H is the Making programme profile according to the flash memory depicted in the embodiment of the present invention.
[main element symbol description]
100,300: substrate；
102,304: isolation structure；
104: tunnel dielectric layer；
105,305: action zone；
106,112: polysilicon layer；
108: dielectric layer between grid；
110: hole；
216: wordline；
218: residual structural；
216: wordline；
218: residual structural；
302: patterned mask layer；
303: raceway groove；
304a: top section；
306: the first dielectric layers；
307: conductor material layer；
308: the first conductor layers；
310: the second dielectric layers；
312: the second conductor layers；
D1, d2, d3: width；
I-I ': hatching.
Detailed description of the invention
Fig. 3 A to Fig. 3 H is the Making programme profile according to the flash memory depicted in the embodiment of the present invention.
First, refer to Fig. 3 A, it is provided that substrate 300.Substrate 300 e.g. silicon substrate.Then,
Substrate 300 is formed patterned mask layer 302.The material of patterned mask layer 302 for example, nitrogen
Compound.Incidentally, one layer of oxide can be initially formed as cushion before forming mask layer 302
(not illustrating), so as to reducing the stress between mask layer 302 and substrate 300.Then, with patterning
Mask layer 302 is mask, performs etching process, to form raceway groove 303 in substrate 300.Then,
Substrate 300 is formed spacer material layer, and fills up raceway groove 303.The material of spacer material layer is such as
It it is oxide.Afterwards, carry out flatening process (for example, chemical mechanical milling tech), remove ditch
Spacer material layer outside road 303, to form isolation structure 304.After carrying out above-mentioned flatening process,
The end face of isolation structure 304 is copline with the end face of patterned mask layer 302.Adjacent isolation junction
Action zone 305 is defined between structure 304.Action zone 305 has width d1.
Then, refer to Fig. 3 B, remove the oxide remained on action zone 305.Remove residual
Oxide method e.g. with dilution Fluohydric acid. carry out wet etching.Special one is mentioned that,
Owing to the material of isolation structure 304 is oxide, therefore during above-mentioned wet etching, except
Remove outside the oxide remained on action zone 305, also together with time remove portions of isolation structure 304,
Make the surface less than patterned mask layer 302, the surface of isolation structure 304.
Then, carrying out the etching technics of the present invention, this etching technics includes that a patterned mask layer is carved
Erosion processes and an isolation structure etching processing, below will elaborate it.First, refer to
Fig. 3 C, carries out patterned mask layer etching processing, removes the patterned mask layer 302 of part so that
The surface of patterned mask layer 302 is less than the surface of isolation structure 304, to expose isolation structure 304
Partial sidewall.In this step, e.g. use hot phosphoric acid to carry out wet etching, and removed
Patterned mask layer 302 thickness such as betweenExtremelyBetween.Then, refer to figure
3D, carries out isolation structure etching processing, removes the part of the corner of adjacent pattern mask layer 302
Isolation structure 304, so that the width of the top section 304a of isolation structure 304 is less than base section
Width.In the present embodiment, top section 304a is the part through isolation structure etching processing,
And base section is the part without isolation structure etching processing.In this step, e.g. use
The Fluohydric acid. of dilution carries out wet etching, and the thickness of the isolation structure 304 removed is aboutExtremelyBetween.After the etching technics (step described in Fig. 3 C to Fig. 3 D) of the present invention,
Width d2 between the top section 304a of adjacent isolation structure 304 can have more than action zone 305
There is width d1.
Then, refer to Fig. 3 E, repeat above-mentioned etching technics once, the most once pattern
Mask layer etching processing and an isolation structure etching processing, make the top of adjacent isolation structure 304
Width d3 between part 304a is more than the width d2 in Fig. 3 D.In the present embodiment, it is repeated
Secondarily etched technique (includes at a patterned mask layer etching processing and an isolation structure etching
Reason), but the present invention is not limited to this, in other embodiments, it is possible to repeat three times or three times
Above etching technics, so that having institute between the top section 304a of adjacent isolation structure 304
The width needed.
Then, refer to Fig. 3 F, remove patterned mask layer 302.Remove patterned mask layer 302
Method e.g. carry out wet etching with hot phosphoric acid.Will be patterned into after mask layer 302 removes completely,
Ion implanting step can be carried out, to form well region (not illustrating) in substrate 300.Then, select
Property ground on substrate 300 formed sacrificial oxide layer (not illustrating).The forming method example of sacrificial oxide layer
Thermal oxidation method in this way.Sacrificial oxide layer can make substrate impaired in above-mentioned ion implanting step 300 turns
Become oxide layer.Then, sacrificial oxide layer is removed.After sacrificial oxide layer, substrate 300 i.e. will not
There is the part damaged in ion implanting step.
Continuing referring to Fig. 3 F, on substrate, 300 form the first dielectric layer 306.First dielectric layer 306
For the material as the tunnel dielectric layer in flash memory.The material of the first dielectric layer 306 e.g. aoxidizes
Thing, and its forming method for example, thermal oxidation method.Then, the first dielectric layer 306 forms conductor
Material layer 307.The material of conductor material layer 307 for example, polysilicon.In the present embodiment, due to
There is between the top section 304a of adjacent isolation structure 304 bigger width d3, therefore in shape
Can avoid causing hole formation in conductor material layer because spreadability is bad when becoming conductor material layer 307
In 307.
Then, refer to Fig. 3 G, substrate 300 is carried out planarization process, to remove segment conductor
Material layer 307 and remove the top section 304a of isolation structure 304, forms the first conductor whereby
Layer 308.First conductor layer 308 is for as the floating grid in flash memory.Special one is mentioned that,
After removing the top section 304a of isolation structure 304, adjacent conductor layer 308 can be avoided excessively
Close to and cause follow-up formed flash memory operation time produce interference (disturb) problem.
Then, refer to Fig. 3 H, remove portions of isolation structure 304, make the surface of isolation structure 304
The low surface at the first conductor layer 308, to expose the sidewall of part the first conductor layer 308.So
One, the faying surface between floating grid and the control gate in follow-up formed flash memory can be increased
Long-pending to improve gate coupling ratio (gate coupling ratio, GCR).Then, shape on substrate 300
Become the second dielectric layer 310.The material of the second dielectric layer 310 such as oxide/nitride/oxide is constituted
Composite bed.Then, the second dielectric layer 310 forms the second conductor layer 312.Second conductor layer
The material of 312 e.g. polysilicon.Second conductor layer 312 is used for the control gate as flash memory and word
The material of line.Then, Patternized technique is carried out, to define wordline and grid structure.Afterwards,
It is doped technique, forms the doped region of the source/drain regions as flash memory.Above-mentioned Patternized technique
It is well known to those skilled in the art with doping process, at this NES.In the present embodiment,
Owing to conductor material layer 307 not having hole, therefore do not have when forming the second dielectric layer 312
Dielectric material is inserted the phenomenon in hole and is occurred.Consequently, it is possible to after defining wordline, adjacent
Do not have dielectric material or conductor material residual between wordline, can avoid at follow-up lining between wordline
Formed at the end 300 cause after contact hole contact hole electrical on problem.
Although the present invention is disclosed above with embodiment, but it is not intended to limit the present invention, any
Those of ordinary skill in art, without departing from the spirit and scope of the present invention, when making
The change of part and modification, therefore protection scope of the present invention is when being as the criterion depending on as defined in claim.
Claims (10)
1. the manufacture method of a flash memory, it is characterised in that including:
There is provided substrate, described substrate is formed in patterned mask layer, and described substrate be formed every
End face copline from structure, the end face of wherein said isolation structure and described patterned mask layer；
Performing etching technique, described etching technics includes:
Remove the described patterned mask layer of part；And
After removing the described patterned mask layer of part, remove neighbouring described patterned mask layer
The described isolation structure of part of corner so that the width of the top section of described isolation structure
Width less than base section；
Repeat described etching technics at least one times；
Remove described patterned mask layer；
Form the first dielectric layer over the substrate；
Described first dielectric layer is formed the first conductor layer；
Remove the described first conductor layer of part and the described isolation structure of part；
Described first conductor layer with described isolation structure form the second dielectric layer；And
Described second dielectric layer is formed the second conductor layer.
The manufacture method of flash memory the most according to claim 1, it is characterised in that described first
The forming method of conductor layer includes:
Forming conductor material layer over the substrate, described conductor material layer covers described isolation structure；
And
Carry out flatening process, remove the described conductor material layer of part and remove described isolation structure
Described top section.
The manufacture method of flash memory the most according to claim 1, it is characterised in that remove part
The method of described patterned mask layer includes using hot phosphoric acid to carry out wet etching.
The manufacture method of flash memory the most according to claim 1, it is characterised in that at described quarter
The thickness that patterned mask layer described in etching technique is removed betweenExtremelyBetween.
The manufacture method of flash memory the most according to claim 1, it is characterised in that remove neighbouring
The method of the described isolation structure of part of the corner of described patterned mask layer includes using dilution
Fluohydric acid. carries out wet etching.
The manufacture method of flash memory the most according to claim 1, it is characterised in that at described quarter
The thickness that isolation structure described in etching technique is removed betweenExtremelyBetween.
The manufacture method of flash memory the most according to claim 1, it is characterised in that described isolation
The forming method of structure includes:
With described patterned mask layer as mask, remove the described substrate of part, to form raceway groove；
Form spacer material layer over the substrate, and fill up described raceway groove；And
Carry out flatening process, remove the described spacer material layer outside described raceway groove.
The manufacture method of flash memory the most according to claim 7, it is characterised in that carrying out institute
After stating flatening process and before carrying out described etching technics, also include removing part described every
From structure.
The manufacture method of flash memory the most according to claim 1, it is characterised in that removing
After stating patterned mask layer and before forming described first dielectric layer, also include:
Carry out oxidation technology, to form sacrificial oxide layer over the substrate；And
Remove described sacrificial oxide layer.
The manufacture method of flash memory the most according to claim 9, it is characterised in that remove described
The method of sacrificial oxide layer includes that the Fluohydric acid. using dilution carries out wet etching.
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| CN201210378841.7A CN103715146B (en) | 2012-10-09 | 2012-10-09 | The manufacture method of flash memory |
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| CN1881534A (en) * | 2005-06-13 | 2006-12-20 | 海力士半导体有限公司 | Method of manufacturing a floating gate of a flash memory device |
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| KR100539275B1 (en) * | 2004-07-12 | 2005-12-27 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
| KR20090078165A (en) * | 2008-01-14 | 2009-07-17 | 주식회사 하이닉스반도체 | Method of forming flash memory device |
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| CN1881534A (en) * | 2005-06-13 | 2006-12-20 | 海力士半导体有限公司 | Method of manufacturing a floating gate of a flash memory device |
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