CN104733393A - Structure and manufacturing method of photomask type read-only memory - Google Patents
Structure and manufacturing method of photomask type read-only memory Download PDFInfo
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- CN104733393A CN104733393A CN201310717885.2A CN201310717885A CN104733393A CN 104733393 A CN104733393 A CN 104733393A CN 201310717885 A CN201310717885 A CN 201310717885A CN 104733393 A CN104733393 A CN 104733393A
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Abstract
The invention discloses a manufacturing method of a photomask type read-only memory. The manufacturing method comprises the steps that (1) a shallow isolating groove is formed in an active region of a silicon substrate through an existing technology, and P well injection is conducted; (2) light resistance of N-type embedded sources and drains is coated, exposure is conducted, arsenic ion injection or phosphorus ion injection are conducted, and the N-type embedded sources and drains are formed; (3) photoresist is removed, gate oxide, a polysilicon gate and a grid electrode isolation side wall are formed through the existing technology; (4) doping injection of P-type ions is conducted on the polysilicon gate. The invention further discloses a structure of the photomask type read-only memory manufactured through the method, wherein the doping type of the polysilicon gate of the photomask type read-only memory is a P type. Due to the fact that the traditional N type of the polysilicon gate of the photomask type read-only memory is replaced with the P type, the doping type of the gate is made to coincide with the doping type of a channel, the difference of the vacuum level of the groove and the vacuum level of the gate is reduced, so that under the situation that the doping concentration of the groove does not need to be increased, the threshold voltage of the photomask type read-only memory is improved, and the electric leakage of a device is restrained.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to structure and the manufacture method thereof of mask read-only memory.
Background technology
Read-only memory (Read-Only Memory) is a kind of memory that can only read data.The data of this memory write when producing.In the fabrication process, by data with special light shield (mask) burning in circuit, so be sometimes also called " mask read-only memory " (mask ROM).In fact it is the spitting image of the principle of CD CD, in the photo-etching technological process of semiconductor, be written with data mode.
The data of this mask read-only memory can not be changed after write, so data can not be lost, and its manufacturing cost is very low, and therefore, do not needing in the equipment of Data Update, Mask ROM is by use widely.
But this mask read-only memory is also obviously in technologic shortcoming.As shown in Figure 2,3, the device cell of mask read-only memory is a N-type MOSFET (nmos device), and raceway groove is the trap of P type, and source and drain and polysilicon gate are N-type doping, and P type raceway groove and N-type grid vacuum level differ greatly (see figure 4).In order to realize high device density as far as possible, the grid of device and source and drain are all strips, spaced one by one, mutually vertical between grid and source-drain electrode, the distance between the source and drain representing channel length always can do little just do little, as shown in Figure 1.But its problem brought is exactly cause the electric leakage of device to increase.First, raceway groove is short, causes the Punchthrough electric current of device to increase.In order to overcome the punchthrough current of device, general needs improve the threshold voltage of device by increasing channel dopant concentration, to suppress the generation of Punchthrough.But channel doping is too dense also can cause the electric leakage of the PN junction of source and drain and trap to increase, and device electric breakdown strength diminishes.
Summary of the invention
One of the technical problem to be solved in the present invention is to provide a kind of manufacture method of mask read-only memory, and it can suppress the electric leakage of high density mask read-only memory.
For solving the problems of the technologies described above, the manufacture method of mask read-only memory of the present invention, step comprises:
1) on silicon substrate active area, form shallow isolation trench by existing technique, and carry out the injection of P trap;
2) be coated with the photoresistance that N-type buries source and drain, exposure, carry out arsenic ion or phosphonium ion injection, form N-type and bury source and drain;
3) remove photoresist, form grid oxygen, polysilicon gate and gate isolation side wall by existing technique;
4) polysilicon gate is carried out to the doping injection of P type ion.
Two of the technical problem to be solved in the present invention is to provide the structure of the mask read-only memory manufactured with said method.The doping type of the polysilicon gate of this mask read-only memory is identical with the doping type of the raceway groove of this mask read-only memory.
Described polysilicon gate is P-type polysilicon gate pole very.
The present invention is by replacing to P type by the polysilicon gate of mask read-only memory by traditional N-type, make grid doping type consistent with channel dopant type, thus reduce the difference of the vacuum level of raceway groove and grid, when not needing to improve channel dopant concentration, improve the threshold voltage of mask read-only memory, inhibit the channel surface transoid of raceway groove when device turns off (grid voltage is 0 volt), reduce the electric leakage of device.
Accompanying drawing explanation
Fig. 1 is the vertical view of traditional mask read-only memory.
Fig. 2 is traditional mask read-only memory buries source and drain direction profile along N-type.
Fig. 3 is the profile of traditional mask read-only memory along grid direction.
Fig. 4 is longitudinal energy band diagram of traditional mask read-only memory.
Fig. 5 ~ Fig. 9 is the manufacturing process flow schematic diagram of the mask read-only memory of the embodiment of the present invention.Wherein, Fig. 9 is the profile of mask read-only memory along grid direction of embodiment of the present invention manufacture.
Figure 10 is longitudinal energy band diagram of the mask read-only memory of Fig. 9.
Embodiment
Understand more specifically for having technology contents of the present invention, feature and effect, now by reference to the accompanying drawings, details are as follows:
The manufacture method of mask read-only memory of the present invention, its concrete technology step is as follows:
Step 1, the active area of silicon substrate forms shallow isolation trench, to isolate mask read-only memory region and peripheral circuit, as shown in Figure 5.
Step 2, carries out the injection of P trap in the active area of mask read-only memory, form the active area in P trap, as shown in Figure 6 (B figure is the vertical view after this step completes).
Step 3, form N-type and burying the coating of the place beyond the region of source and drain photoresist, exposure, then carries out the less high dose arsenic ion of energy or phosphonium ion injects that (Implantation Energy is 40 ~ 90keV, and implantation dosage is 5.1e14 ~ 4.3e15/cm
2, implant angle is 0 degree of inclination), form N-type and bury source and drain, as shown in Figure 7.
Step 4, removing photoresist, carries out the oxidation of grid oxygen by existing technique; Deposit grid polycrystalline silicon, and etching forms polysilicon gate; Deposition thickness is
silica dioxide medium layer, and return to carve and form gate isolation side wall.
Step 5, is injected by the P type source and drain of peripheral logic device PMOS and (injects boron ion, Implantation Energy 5 ~ 15keV, implantation dosage 6e14 ~ 6.1e15/cm
2) realize the doping of polysilicon gate, namely when the source and drain of carrying out PMOS is injected, also doping injection is carried out to the polysilicon gate of mask read-only memory, as shown in Figure 8 simultaneously.As shown in Figure 9, this mask read-only memory has P-type polysilicon gate pole to the structure of the mask read-only memory of final formation, and P type raceway groove is with P-type grid electrode because doping type is consistent, and therefore both vacuum level difference is very little, as shown in Figure 10.
Claims (7)
1. the manufacture method of mask read-only memory, is characterized in that, step comprises:
1) on silicon substrate active area, form shallow isolation trench by existing technique, and carry out the injection of P trap;
2) be coated with the photoresistance that N-type buries source and drain, exposure, carry out arsenic ion or phosphonium ion injection, form N-type and bury source and drain;
3) remove photoresist, form grid oxygen, polysilicon gate and gate isolation side wall by existing technique;
4) polysilicon gate is carried out to the doping injection of P type ion.
2. method according to claim 1, is characterized in that, step 2), Implantation Energy is 40 ~ 90keV, and implantation dosage is 5.1e14 ~ 4.3e15/cm
2.
3. method according to claim 1, is characterized in that, step 2), implant angle is 0 degree of inclination.
4. method according to claim 1, is characterized in that, step 4), injects by the P type source and drain of peripheral logic device PMOS the doping realizing polysilicon gate.
5. method according to claim 4, is characterized in that, step 4), injects boron ion, Implantation Energy 5 ~ 15keV, implantation dosage 6e14 ~ 6.1e15/cm
2.
6. the structure of mask read-only memory, is characterized in that, the doping type of the polysilicon gate of this mask read-only memory is identical with the doping type of the raceway groove of this mask read-only memory.
7. the structure of mask read-only memory according to claim 6, is characterized in that, described polysilicon gate is P-type polysilicon gate pole very.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310717885.2A CN104733393A (en) | 2013-12-23 | 2013-12-23 | Structure and manufacturing method of photomask type read-only memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310717885.2A CN104733393A (en) | 2013-12-23 | 2013-12-23 | Structure and manufacturing method of photomask type read-only memory |
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| CN104733393A true CN104733393A (en) | 2015-06-24 |
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| CN201310717885.2A Pending CN104733393A (en) | 2013-12-23 | 2013-12-23 | Structure and manufacturing method of photomask type read-only memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110147560A (en) * | 2018-02-12 | 2019-08-20 | 熠芯(珠海)微电子研究院有限公司 | Realize the low power consumption method of more size circuits |
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| KR100835426B1 (en) * | 2006-12-28 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Method for the fabrication of nor type logic compatible flat cell mask rom |
| CN103000671A (en) * | 2011-09-16 | 2013-03-27 | 中国科学院微电子研究所 | MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof |
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|---|---|---|---|---|
| TW462083B (en) * | 2000-12-04 | 2001-11-01 | Macronix Int Co Ltd | Method for manufacturing salicide metal of embedded virtual-ground memory |
| CN1423324A (en) * | 2001-12-05 | 2003-06-11 | 联华电子股份有限公司 | Method for making concealed potential source line of cover curtain type read-only memory |
| CN1728394A (en) * | 2004-07-14 | 2006-02-01 | 精工电子有限公司 | Semiconductor integrated circuit device |
| CN1855395A (en) * | 2005-04-20 | 2006-11-01 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics |
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| CN103000671A (en) * | 2011-09-16 | 2013-03-27 | 中国科学院微电子研究所 | MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110147560A (en) * | 2018-02-12 | 2019-08-20 | 熠芯(珠海)微电子研究院有限公司 | Realize the low power consumption method of more size circuits |
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