CN104702552B - BPSK subcarrier correlation demodulation bit boundaries determine circuit and method - Google Patents
BPSK subcarrier correlation demodulation bit boundaries determine circuit and method Download PDFInfo
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- CN104702552B CN104702552B CN201310652435.XA CN201310652435A CN104702552B CN 104702552 B CN104702552 B CN 104702552B CN 201310652435 A CN201310652435 A CN 201310652435A CN 104702552 B CN104702552 B CN 104702552B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
- H04L27/2278—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using correlation techniques, e.g. for spread spectrum signals
Abstract
The invention discloses a kind of BPSK subcarriers correlation demodulation bit boundaries to determine circuit, including a BPSK subcarrier rising edge counters, one first comparison module, one BPSK subcarrier high level statistical counters, one second comparison module, one BPSK subcarrier low and high level counters, a flip bit sideband signal generation module for the first time.The invention also discloses a kind of BPSK subcarriers correlation demodulation bit boundaries to determine method, and the low and high level for aligning the monocycle BPSK subcarrier during synchronizing carries out counting statistics respectively；Assembly average, the calculating reference value of the low and high level as the monocycle subcarrier during bit synchronization are used after the completion of statistics；The calculating reference value of the low and high level is turned over into offset plus height, threshold value is turned over as high for the first time and low turns over threshold value；The low and high level statistical value of BPSK subcarriers is turned over threshold value with height to compare, obtains bit boundary locking signal and bit boundary marking signal.The present invention can improve the success rate of the point detection of overturning for the first time.
Description
Technical field
The present invention relates to digital correlation demodulation circuit fields, as defined in a kind of 14443 agreements of ISO/IEC
BPSK (two-phase PSK) subcarrier correlation demodulation bit boundary under 847k baud rates determines circuit.The invention further relates to one kind
BPSK subcarrier correlation demodulation bit boundaries determine method.
Background technology
According to BPSK code streams as defined in ISO/IEC14443 agreements (hereinafter referred to as " agreement "), under 847k baud rates, often
A subcarrier all represents a bit period.
It is provided according to agreement, the card of either typeA (type A) or typeB (type B), which return to BPSK codings, one
The fixed bit synchronization phase will not have phase bit flipping during synchronization, therefore according to the subcarrier rising edge to be demodulated of contraposition sync period
It is detected, starting point of the rational rising edge as reference subcarrier can be selected, generate reference subcarrier.
It is provided according to agreement, the data of sync period in place are considered 1 ' b1, and i.e. saltus step is 1 ' b0 after overturning for the first time.For
847k baud rates, since 1 subcarrier corresponds to 1 bit period, the determination of the first time overturning point of data phase is extremely important.
The phase of the position and reference subcarrier of overturning for the first time is that high level overturning or low level overturning are determined by first time overturning
It is fixed.
In conjunction with shown in Fig. 1, so-called high level overturning is that the high level lasting time of the point of overturning for the first time is equal to 1 period,
I.e. height turns over；Similarly, so-called low level overturning refers to that the low duration of the point of overturning for the first time is equal to 1 period, i.e., low
It turns over.It is to determine that every frame data are that height opens when being demodulated to the subcarrier under 847k baud rates with the mode of digital correlation
Begin or low opens the beginning.
It is on the basis of the rising edge according to the reference subcarrier of bit synchronization phase due to the generation of reference signal, height is turned over to be turned over low
Practical bit boundary have half of subcarrier cycle phase potential difference.Therefore subsequently to BPSK subcarriers under 847k baud rates into line number
When word correlation demodulation, if cannot be accurately obtained the height overturn for the first time turn over or it is low turn over situation, cannot when just will appear demodulation
Determination goes to judge correlated results at the time of being with the rising edge of reference subcarrier or decline edge.Therefore point is overturn for the first time
Determination is very crucial to the digital correlation demodulation of BPSK subcarriers under 847k baud rates.
Invention content
The technical problem to be solved in the present invention is to provide a kind of BPSK subcarriers correlation demodulation bit boundaries to determine circuit, can
Improve the success rate of the point detection of overturning for the first time；For this purpose, to also provide a kind of BPSK subcarriers correlation demodulation bit boundary true by the present invention
Determine method.
In order to solve the above technical problems, the BPSK subcarrier correlation demodulation bit boundaries of the present invention determine circuit, including：
One BPSK subcarrier rising edge counters, for simulating the BPSK after receiving circuit is opened during counting bit synchronization
Subcarrier signal number；
One first comparison module is connected with the BPSK subcarriers rising edge counter, for limiting BPSK subcarriers
The count range of high level statistical counter；
One BPSK subcarrier high level statistical counters, are connected with first comparison module, according to the counting of restriction
Range starts after unstable several BPSK subcarriers periods and counts, the BPSK for counting continuous multiple bit synchronization phases
System clock number between subcarrier high period, and obtain the average system clock number of monocycle high level；According to high electricity
Flat average system clock number calculates monocycle low level average system clock number；
One second comparison module is connected with the BPSK subcarriers high level statistical counter, by the high level
Average system clock number turns over offset plus height, obtains height and turns over threshold value；The low level average system clock number is added
Upper low offset of turning over obtains low turning over threshold value；
One BPSK subcarrier low and high level counters, high level and low level for counting each period BPSK subcarriers
System clock number, in the rising edge or failing edge clear 0 of BPSK subcarriers；
One flip bit sideband signal generation module for the first time, the mould compared with the BPSK subcarriers rising edge counter, second
Block is connected with BPSK subcarrier low and high level counters, the high level that the BPSK subcarriers low and high level counter is exported
System clock number statistical value turns over threshold value with height and is compared, or the BPSK subcarriers low and high level counter is exported
Low level system clock number statistical value is compared with low threshold value of turning over, and obtains court verdict, and once obtain court verdict
I.e. locking decision is as a result, carry-out bit edge locking signal and boundary marker signal；
The BPSK subcarriers are the BPSK subcarriers under 847k baud rates as defined in 14443 agreements of ISO/IEC.
The BPSK subcarriers correlation demodulation bit boundary determines method, includes the following steps：
Step 1 starts counting after unstable several BPSK subcarriers periods, for counting continuous multiple bit synchronizations
System clock number between the BPSK subcarrier high periods of phase；
Step 2, with the BPSK subcarrier number of cycles of statistical value divided by statistics, the height in as 1 BPSK subcarrier period
The average system clock number of level；
According to the average system clock number of the high level for 1 BPSK subcarrier for having counted completion, 1 is calculated
The low level average system clock number of BPSK subcarriers；
The average system clock number of the high level is turned over offset by step 3 plus height, is obtained height and is turned over threshold value；By institute
Low level average system clock number is stated to obtain low turning over threshold value plus low offset of turning over；
High level systems clock number statistical value is turned over threshold value with height and compares by step 4, or by low level system clock
Number statistical value is turned over low compared with threshold value, obtains bit boundary locking signal and bit boundary marking signal.
The present invention can be after receiving circuit opening, for the communication feature received every time, with the mode meter of statistical counter
Calculate the distortion situation of this communication；When carrying out threshold value judgement, by the statistical average thus according to statistical counter after average
Value is plus the offset being arranged, the case where distortion for BPSK subcarrier duty ratios, such as high level in the monocycle during bit synchronization
Time has been embodied in more than low level time among the assembly average of statistical counter, therefore judges the point of overturning for the first time
Threshold value is the threshold value closer to actual characteristic, improves the success rate of the point detection of overturning for the first time.
In addition, resetted in BPSK subcarriers edge to be detected by 1 BPSK subcarrier low and high level counter
Mode has simplified design.
Description of the drawings
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings：
Fig. 1 is that height turns over and turns over definition schematic diagram with low；
Fig. 2 is that BPSK subcarrier correlation demodulation bit boundaries determine schematic block circuit diagram；
Fig. 3 is BPSK subcarrier low and high level counter principle block diagrams；
Fig. 4 is that height turns over threshold value generation logical schematic.
Specific implementation mode
Shown in Figure 2, in the following embodiments, the BPSK subcarriers correlation demodulation bit boundary determines circuit, packet
It includes：One BPSK subcarrier rising edge counters, one first comparison module, a BPSK subcarrier high level statistical counters, one
Two comparison modules, a BPSK subcarrier low and high level counters, a flip bit sideband signal generation module for the first time.The BPSK pairs
Carrier wave refers to the BPSK subcarriers under 847k baud rates as defined in 14443 agreements of ISO/IEC.
The BPSK subcarriers rising edge counter is to be counted to the rising edge of the BPSK subcarriers of input, is used for
The BPSK subcarrier signal numbers after receiving circuit is opened are simulated during counting bit synchronization.
First comparison module, by the count threshold of the count value and setting of the BPSK subcarriers rising edge counter
It compares, generates count enable signal, when the count value of the BPSK subcarriers rising edge counter is more than or equal to count threshold
When the count enable signal it is effective, the count range for limiting the BPSK subcarriers high level statistical counter.That is,
It is not that horse back just carries out the statistics of BPSK subcarrier high level, but waits for several unstable BPSK pairs after reception starts
(the several unstable BPSK subcarriers started are abandoned after carrier cycle), start to carry out the high level of BPSK subcarriers continuous
Statistics.
The BPSK subcarriers high level statistical counter, after count enable signal is enabled, i.e., unstable several
The BPSK subcarrier periods start counting later, and between the BPSK subcarrier high periods for counting continuous multiple bit synchronization phases is
System clock number；By taking 4 BPSK subcarrier periods as an example, in the system clock for completing 4 BPSK subcarrier period high level
Stop counting after number statistics, that is, locks statistical value.Then, with statistical value divided by the BPSK subcarrier number of cycles of statistics, as 1
Average system clock number (or " average time ") H_duty_cnt [5 of the high level in a BPSK subcarriers period:2].It is single
Position is counting clock (i.e. 13.56MHz system clocks).
According to the average system clock number H_duty_cnt of the high level for 1 BPSK subcarrier for having counted completion
[5:2], you can to calculate the low level average system clock number 16-H_duty_cnt [5 of 1 BPSK subcarrier:2].
Second comparison module, by the average system clock number H_duty_cnt [5 of the high level:2] height is added
Turn over offset high_shift [3:0], obtain height and turn over threshold value high_threshold [3:0]；By the low level average
Clock number of uniting 16-H_duty_cnt [5:2] offset low_shift [3 is turned over plus low:0] it obtains low turning over threshold value low_
threshold[3:0]。
In conjunction with shown in Fig. 4, according to agreement, in the ideal case, when a high level continue for 16 system clocks, recognize
To be a high tumble (abbreviation height turns over)；With should a low level continue for 16 system clocks when, it is believed that be primary low turn over
Turn (referred to as low to turn over).Assuming that the monocyclic high level time counted is H_duty_cnt [5:2]=9 (ideal value 8), then
If adjudicating a high tumble, offset high_shift [3 should be turned over plus a height:0], i.e. 9+high_shift [3:0],
For being compared with the count value of low and high level counter, how much be as the occurrence that the offset measures should be according to simulation electricity
The characteristics of road, sets, and ideal value should be 16- high and turn over ideal value=16-8=8 system clock.It is recommended that value is compared with ideal value
Surplus is reserved, generally sets 4-6, the low threshold calculations turned over are similarly.
The BPSK subcarriers low and high level counter, the high level for counting each period BPSK subcarriers and low electricity
Flat system clock number, in the rising edge or failing edge clear 0 of BPSK subcarriers.
The sideband signal generation module of flip bit for the first time, the height that the BPSK subcarriers low and high level counter is exported
Level system clock number statistical value turns over threshold value with height and is compared, or the BPSK subcarriers low and high level counter is defeated
The low level system clock number statistical value gone out is compared with low threshold value of turning over, and obtains court verdict, and once adjudicated
As a result it is locking decision as a result, carry-out bit edge locking signal and boundary marker signal.It is overturn when the first time of BPSK subcarriers
Point is that high level is overturn, then the flip bit sideband signal generation module for the first time sets 1, otherwise sets to 0.
Referring to Fig. 2, flip bit sideband signal generation module for the first time described in the input of BPSK subcarriers, according to BPSK subcarriers
Height come indicate current count be high level count or low level count.The count value of BPSK subcarrier rising edge counters is defeated
Enter the flip bit sideband signal generation module for the first time, equal to the several unstable BPSK subcarriers for shielding beginning, i.e. BPSK
After the count value of subcarrier rising edge counter is greater than or equal to count threshold, the sideband signal generation module of flip bit for the first time
Just start to work.
Fig. 3 is the one example structure block diagram of BPSK subcarriers low and high level counter, including：First d type flip flop
DCF1, the second d type flip flop DCF2, a phase inverter NOT, an XOR gate Xor and a counter.
The counting of the input end of clock and counter of the first d type flip flop DCF1 and the second d type flip flop DCF2 inputs
Hold input system clock Sys_clk.The ends data input pin D of the first d type flip flop DCF1 input BPSK subcarrier signals,
The ends output end Q are connected with an input terminal at the ends data input pin D of the second d type flip flop DCF2 and XOR gate Xor, and the 2nd D is touched
The ends output end Q of hair device DCF2 are connected with another input terminal of the XOR gate Xor.The output end of the XOR gate Xor with
The clear terminal of counter is connected.The input terminal of the phase inverter inputs the signal of flip bit edge locking for the first time, and output end is made
It is connected with the Enable Pin of the counter to count Enable Pin.Start in reception, bit boundary locking signal is 1 ' b0, and counting makes
It can open, after edge locking signal circuit detects boundary, bit boundary locking signal becomes 1 ' b1, and counter makes later
It can become 1 ' b0, stop counting.
Due to being BPSK subcarrier low and high level counters, result and the height of the counter turn over threshold value or low turn over threshold value ratio
After relatively, if it find that more than or equal to height turn over threshold value or it is low turn over threshold value, can't judge that height is turned over or low turned over, it is necessary to according to
The polarity number of the upper one BPSK subcarrier serial signals clapped is turned over adjudicating height or low is turned over.Such as, it is assumed that BPSK subcarrier height
The statistical result of level counter is 15, and height turns over threshold value high_threshold [3:0]=14, low to turn over threshold value low_
threshold[3:0]=14, if upper one claps BPSK subcarriers as height, boundary marker signal h_l_sel is 1 ' b1, is indicated
High tumble；If instead under similarity condition, the upper one BPSK subcarriers clapped are low level, then boundary marker signal h_l_sel is
1 ' b0 indicates low overturning.Bit boundary locking signal h_l_lock saltus steps simultaneously are 1 ' b1, and bit boundary is locked after the shutdown of BPSK subcarriers
Determine signal h_l_lock to reset.
The BPSK subcarriers correlation demodulation bit boundary determines method, includes the following steps：
The low and high level of monocycle BPSK subcarrier during step 1, contraposition are synchronous carries out counting statistics respectively；With 4
For the cumulative statistics amount of BPSK subcarriers, BPSK subcarrier high level statistical counters are 6bits；
Assembly average is used after the completion of step 2, statistics, that is, moves to left the BPSK subcarrier high level statistical counters of 2bits
Value as the monocycle BPSK subcarrier during bit synchronization low and high level calculating reference value；
The calculating reference value of the high level is turned over offset by step 3 plus height, and low level calculating reference value is plus low
Offset is turned over to turn over threshold value respectively as high for the first time and low turn over threshold value；
High level statistical value and the height of BPSK subcarriers are turned over threshold value and compare by step 4, and low level statistical value turns over threshold with low
Value compares, and obtains bit boundary locking signal and bit boundary marking signal.
Statistics and calculating of the present invention by the low and high level to BPSK subcarriers, can be according to practical BPSK subcarriers
The rule of low and high level detects high tumble or low overturning in an adaptive way.
Above by specific implementation mode, invention is explained in detail, but these are not constituted to the present invention's
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of BPSK subcarriers correlation demodulation bit boundary determines circuit, which is characterized in that including：
One BPSK subcarrier rising edge counters are carried for simulating the BPSK pairs after receiving circuit is opened during counting bit synchronization
Wave signal number；
One first comparison module is connected with the BPSK subcarriers rising edge counter, for limiting the high electricity of BPSK subcarriers
The count range of flat statistical counter；
One BPSK subcarrier high level statistical counters, are connected with first comparison module, according to the count range of restriction,
Start after unstable several BPSK subcarriers periods and counts, the BPSK subcarriers for counting continuous multiple bit synchronization phases
System clock number between high period, and obtain the average system clock number of monocycle high level；According to the flat of high level
Equal system clock number calculates monocycle low level average system clock number；
One second comparison module is connected with the BPSK subcarriers high level statistical counter, by being averaged for the high level
System clock number turns over offset plus height, obtains height and turns over threshold value；By the low level average system clock number plus low
Offset is turned over to obtain low turning over threshold value；
One BPSK subcarrier low and high level counters, the high level for counting each period BPSK subcarriers and low level system
System clock number, in the rising edge or failing edge clear 0 of BPSK subcarriers；
One flip bit sideband signal generation module for the first time, with the BPSK subcarriers rising edge counter, the second comparison module and
BPSK subcarrier low and high level counters are connected, the high level systems that the BPSK subcarriers low and high level counter is exported
Clock number statistical value turns over threshold value with height and is compared, or the low electricity that the BPSK subcarriers low and high level counter is exported
Flat system clock number statistical value is compared with low threshold value of turning over, and obtains court verdict, and is once obtained court verdict and locked
Determine court verdict, carry-out bit edge locking signal and boundary marker signal；
The BPSK subcarriers are the BPSK subcarriers under 847k baud rates as defined in 14443 agreements of ISO/IEC.
2. circuit as described in claim 1, it is characterised in that：The BPSK subcarriers low and high level counter, including：First
D type flip flop, the second d type flip flop, a phase inverter, an XOR gate and a counter；
When the counting input end input system of the input end of clock and counter of first d type flip flop and the second d type flip flop
Clock；The ends data input pin D of first d type flip flop input BPSK subcarrier signals, the ends output end Q and the second d type flip flop
The ends data input pin D be connected with an input terminal of XOR gate, the ends output end Q of the second d type flip flop and the XOR gate
Another input terminal is connected；The output end of the XOR gate is connected with the clear terminal of counter；The input terminal of the phase inverter
The signal of flip bit edge locking for the first time is inputted, output end is connected as Enable Pin is counted with the Enable Pin of the counter；
Start in reception, bit boundary locking signal is 1 ' b0, count it is enabled open, edge locking signal circuit detect boundary it
Afterwards, bit boundary locking signal becomes 1 ' b1, and the enabled of counter becomes 1 ' b0 later, stops counting.
3. circuit as claimed in claim 1 or 2, it is characterised in that：The sideband signal generation module of flip bit for the first time, right
The high level systems clock number statistical value of BPSK subcarrier low and high level counters output turns over threshold value comparison or right with height
BPSK subcarrier low and high level counters output low level system clock number statistical value with it is low turn over threshold value comparison after, if hair
Now threshold value is turned over more than or equal to height or low turn over threshold value, it is necessary to which the polarity numbers of the BPSK subcarrier serial signals clapped according to upper one is sentenced
It is certainly that height is turned over or low turned over；If upper one claps BPSK subcarriers as height, boundary marker signal h_l_sel is 1 ' b1, indicates high
Overturning；If instead under similarity condition, the upper one BPSK subcarriers clapped are low level, then boundary marker signal h_l_sel is 1 '
B0 indicates low overturning；Bit boundary locking signal h_l_lock saltus steps simultaneously are 1 ' b1, and bit boundary locks after the shutdown of BPSK subcarriers
Signal h_l_lock is reset.
4. circuit as claimed in claim 3, it is characterised in that：The sideband signal generation module of flip bit for the first time, according to defeated
The height of the BPSK subcarriers entered come judge current count be high level count or low level count；And in the BPSK pairs
After the count value of carrier wave rising edge counter is greater than or equal to count threshold, just start to work.
5. a kind of BPSK subcarriers correlation demodulation bit boundary determines method, which is characterized in that include the following steps：
Step 1 starts counting after unstable several BPSK subcarriers periods, for counting continuous multiple bit synchronization phases
System clock number between BPSK subcarrier high periods；
Step 2, with the BPSK subcarrier number of cycles of statistical value divided by statistics, the high level in as 1 BPSK subcarrier period
Average system clock number；
According to the average system clock number of the high level for 1 BPSK subcarrier for having counted completion, 1 BPSK pair is calculated
The low level average system clock number of carrier wave；
The average system clock number of the high level is turned over offset by step 3 plus height, is obtained height and is turned over threshold value；It will be described low
The average system clock number of level obtains low turning over threshold value plus low offset of turning over；
High level systems clock number statistical value is turned over threshold value with height and compares by step 4, or by low level system clock number
Statistical value is turned over low compared with threshold value, obtains bit boundary locking signal and bit boundary marking signal；
The BPSK subcarriers are the BPSK subcarriers under 847k baud rates as defined in 14443 agreements of ISO/IEC.
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| CN1822181A (en) * | 2005-12-16 | 2006-08-23 | 清华大学 | Code modulation method and device, demodulation method and device |
| CN102752249A (en) * | 2011-04-20 | 2012-10-24 | 上海炬力集成电路设计有限公司 | Signal detection device and method |
| CN102810148A (en) * | 2012-08-13 | 2012-12-05 | 沃谱瑞科技(北京)有限责任公司 | Decoding circuit of non-contact communication integrated circuit |
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| US9184771B2 (en) * | 2011-10-12 | 2015-11-10 | Optis Cellular Technology, Llc | Digital down conversion and demodulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1822181A (en) * | 2005-12-16 | 2006-08-23 | 清华大学 | Code modulation method and device, demodulation method and device |
| CN102752249A (en) * | 2011-04-20 | 2012-10-24 | 上海炬力集成电路设计有限公司 | Signal detection device and method |
| CN102810148A (en) * | 2012-08-13 | 2012-12-05 | 沃谱瑞科技(北京)有限责任公司 | Decoding circuit of non-contact communication integrated circuit |
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