CN105119863A - BPSK subcarrier demodulation preprocessing circuit and method thereof - Google Patents
BPSK subcarrier demodulation preprocessing circuit and method thereof Download PDFInfo
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- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
- H04L27/2278—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using correlation techniques, e.g. for spread spectrum signals
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Abstract
The invention provides a BPSK subcarrier demodulation preprocessing circuit and a method thereof. The BPSK subcarrier demodulation preprocessing circuit comprises a BPSK subcarrier high and low level counter, and a BPSK subcarrier rising edge counter, a first comparison module, a BPSK subcarrier high level statistical counter, a second comparison module and a first time flipping bit boundary signal generation circuit, which are connected in sequence; and the BPSK subcarrier high and low level counter is connected with the first time flipping bit boundary signal generation circuit. The circuit can determine a threshold of a first time flipping point which is closer to an actual feature to improve the detection success rate of the first time flipping point; and in addition, since one BPSK subcarrier high and low level counter resets at a BPSK subcarrier edge to be detected, the design is simplified.
Description
Technical field
The present invention relates to a kind of circuit of digital correlation demodulation circuit, specifically relate to a kind of BPSK subcarrier demodulation pre-process circuit and method.
Background technology
Specify according to ISO/IEC14443 agreement (hereinafter referred to as " agreement "), transmitting terminal returns BPSK (two-phase PSK) coding certain bit synchronization phase, phase overturn is not had between sync period, therefore detect according to the subcarrier rising edge to be demodulated of contraposition sync period, the starting point of rational rising edge as reference subcarrier can be selected, produce reference subcarrier.
Specify according to agreement, during bit synchronization, data think 1, be 0 after first time upset, and for 847k baud rate, due to corresponding 1 bit period of 1 subcarrier, therefore the determination of the 1st overturn point of data phase is extremely important, and the different of the position of first time upset and the phase place of reference subcarrier are that high level overturns or low level overturns and determines by overturning for the first time.
According to agreement regulation, the data of sync period in place think 1 ' b1, and after first time upset, namely saltus step is 1 ' b0.For 847k baud rate, due to corresponding 1 bit period of 1 subcarrier, therefore the data phase first time overturn point determination extremely important.The phase place of the position that first time overturns and reference subcarrier is that high level overturns or low level overturns decision by first time upset.
Shown in composition graphs 1, the upset of so-called high level, be first time the high level lasting time of overturn point equal 1 cycle, namely highly to turn over; In like manner, the upset of so-called low level, refers to that the low duration of first time overturn point equals 1 cycle, namely lowly turns over.When demodulation being carried out to the subcarrier under 847k baud rate by the mode of digital correlation, be to determine that every frame data are that height opens and begins or lowly open the beginning.
Generation due to reference signal is benchmark according to the rising edge of the reference subcarrier of bit synchronization phase, and height turns over and there is half subcarrier periodic phase difference on low actual bit border of turning over.Therefore, follow-up to when under 847k baud rate, BPSK subcarrier carries out digital correlation demodulation, if the height that can accurately do not overturn first turns over or lowly turns over situation, can not determine when just there will be demodulation and go to judge correlated results with the rising edge of reference subcarrier or the moment on decline edge.
To sum up, the determination of overturn point is very crucial to the digital correlation demodulation of BPSK subcarrier under 847k baud rate first.The invention provides a kind of BPSK subcarrier correlation demodulation bit boundary determination circuit, the success rate that overturn point first detects can be improved.
Summary of the invention
For overcoming above-mentioned the deficiencies in the prior art, the invention provides a kind of BPSK subcarrier demodulation pre-process circuit and BPSK subcarrier demodulation bit boundary defining method.
Realizing the solution that above-mentioned purpose adopts is:
A kind of BPSK subcarrier demodulation pre-process circuit, described circuit comprises: BPSK subcarrier low and high level counter and the BPSK subcarrier rising edge counter connected successively, the first comparison module, BPSK subcarrier high level statistical counter, the second comparison module and the circuit of flip bit sideband signal generation first; Described in described BPSK subcarrier low and high level counter connects, flip bit sideband signal produces circuit first;
Described BPSK subcarrier rising edge counter, described BPSK subcarrier high level statistical counter and described BPSK subcarrier low and high level counter receive BPSK subcarrier signal respectively, described second comparison module receives height and turns over threshold shift, produces circuit carry-out bit edge locking signal and boundary marker signal by described decoding pre-process circuit by the described sideband signal of flip bit first.
Preferably, described BPSK subcarrier low and high level counter, for adding up the high level of each cycle BPSK subcarrier and low level system clock number, at rising edge or the trailing edge clear 0 of described BPSK subcarrier.
Preferably, described BPSK subcarrier low and high level counter, comprising: the first d type flip flop, the second d type flip flop, inverter, XOR gate sum counter;
The input end of clock of described first d type flip flop and described second d type flip flop and the counting input end receiving system clock of described counter;
The data input pin of described first d type flip flop receives BPSK subcarrier signal, and output connects the data input pin of described second d type flip flop and the input of described XOR gate; The output of described second d type flip flop connects another input phase of described XOR gate;
The output of described XOR gate connects described counter; The input of described inverter receives the signal of flip bit edge locking first, and its output connects the Enable Pin of described counter as counting Enable Pin.
Preferably, described BPSK subcarrier rising edge statistical circuit, for adding up the signal number of described BPSK subcarrier between bit sync period.
Preferably, described first comparison module, for limiting the count range of described BPSK subcarrier high level statistical counter.
Preferably, described BPSK subcarrier high level statistical counter, according to the count range limited, counting is started after several BPSK subcarrier cycles of instability, for add up continuous multiple bit synchronization phase BPSK subcarrier high period between system clock number, and obtain the average system clock number of monocycle high level; Monocycle low level average system clock number is calculated according to the average system clock number of high level.
Preferably, by the average system clock number of described high level, described second comparison module, adds that height turns over threshold shift, obtains height and turn over threshold value; Described low level average system clock number is added low side-play amount of turning over obtains lowly turning over threshold value.
Preferably, the described sideband signal of flip bit first generation module, the high level systems clock number statistical value export described BPSK subcarrier low and high level counter and height turn over threshold value and compare, or the low level system clock number statistical value of described BPSK subcarrier low and high level counter output and low threshold value of turning over are compared, obtain court verdict and lock described court verdict, carry-out bit edge locking signal and boundary marker signal.
A kind of BPSK subcarrier demodulation preprocess method, comprises the following steps:
The low and high level of the BPSK subcarrier after analog-to-digital conversion between I, employing local clock contraposition sync period carries out counting statistics respectively;
II, add up the computing reference value of rear acquisition assembly average as the low and high level of the monocycle BPSK subcarrier during bit synchronization;
III, the computing reference value of described high level is added that height turns over side-play amount and turns over threshold value as high first, low level computing reference value is added low side-play amount of turning over turns over threshold value as low first;
IV, the high level statistical value of BPSK subcarrier turned over threshold value with described height compared with, low level statistical value lowly turns over compared with threshold value with described, obtains bit boundary locking signal and bit boundary marking signal.
Compared with immediate prior art, the present invention has following beneficial effect:
The present invention can after receiving circuit be opened, and for each communication feature received, the BPSK subcarrier duty ratio in the bit synchronization phase as shown in Figure 5 has the situation of distortion, calculates the distortion situation of this communication by the mode of statistical counter; When carrying out threshold value judgement, due to be average according to statistical counter after assembly average add the side-play amount of setting, for the situation of BPSK subcarrier duty ratio distortion, as high level time in the monocycle during bit synchronization to be embodied among the assembly average of statistical counter more than low level time, therefore judge that the threshold value of first time overturn point is the threshold value closer to actual characteristic, improve the success rate that overturn point first detects.
In addition, the mode resetted in BPSK subcarrier edge to be detected by a BPSK subcarrier low and high level counter, has simplified design.
Accompanying drawing explanation
Fig. 1 is that height turns over and lowly turns over definition schematic diagram;
Fig. 2 is BPSK subcarrier demodulation pre-process circuit theory diagram in the present embodiment;
Fig. 3 is BPSK subcarrier low and high level counter principle block diagram in the present embodiment;
Fig. 4 is that in the present embodiment, height turns over threshold value generation logical schematic;
Fig. 5 is the BPSK subcarrier duty ratio distortion schematic diagram of a kind of bit synchronization phase.
Embodiment
Below with reference to accompanying drawings exemplary embodiment of the present disclosure is described in more detail.Although show exemplary embodiment of the present disclosure in accompanying drawing, but be to be understood that, can realize in a variety of manners the disclosure and not should limit by the embodiment set forth here, other embodiments can comprise structure, logic, electric, process and other change.Embodiment only represents possible change.On the contrary, provide these embodiments to be in order to more thoroughly the disclosure can be understood, and complete for the scope of the present disclosure can be conveyed to those skilled in the art.Herein, these embodiments of the present invention can be represented with term " invention " individually or always, this is only used to conveniently, and if in fact disclose the invention more than, be not the scope that will limit this application is automatically any single invention or inventive concept.
Fig. 2 is BPSK subcarrier demodulation pre-process circuit theory diagram; In the present embodiment, a kind of BPSK subcarrier demodulation pre-process circuit is provided, BPSK subcarrier correlation demodulation bit boundary can be determined, improve the success rate that overturn point first detects.
This circuit comprises: BPSK subcarrier low and high level counter, BPSK subcarrier rising edge counter, the first comparison module, BPSK subcarrier high level statistical counter, the second comparison module and the circuit of flip bit sideband signal generation first.
BPSK subcarrier rising edge counter, the first comparison module, BPSK subcarrier high level statistical counter, the second comparison module are connected successively with the circuit of flip bit sideband signal generation first, and BPSK subcarrier low and high level counter connects flip bit sideband signal first and produces circuit.
BPSK subcarrier rising edge counter, BPSK subcarrier high level statistical counter and BPSK subcarrier low and high level counter receive BPSK subcarrier signal respectively.Second comparison module receives height and turns over threshold shift.
Circuit carry-out bit edge locking signal and boundary marker signal is produced by flip bit sideband signal first by stating decoding pre-process circuit.
Above-mentioned component units is further illustrated respectively:
BPSK subcarrier low and high level counter, for adding up the high level of each cycle BPSK subcarrier and low level system clock number, at rising edge or the trailing edge clear 0 of described BPSK subcarrier.
BPSK subcarrier rising edge statistical circuit counts the rising edge of the BPSK subcarrier of input.For adding up the signal number of described BPSK subcarrier between bit sync period;
First comparison module, for the count value according to described BPSK subcarrier rising edge counter, limits the count range of described BPSK subcarrier high level statistical counter.That is, after reception starts, be not the statistics of at once just carrying out BPSK subcarrier high level, but after the BPSK subcarrier cycle waiting for several instability, start to add up continuously the high level of BPSK subcarrier.
BPSK subcarrier high level statistical counter, according to the count range limited, counting is started after several BPSK subcarrier cycles of instability, for add up continuous multiple bit synchronization phase BPSK subcarrier high period between system clock number, and obtain the average system clock number of monocycle high level.
For 4 BPSK subcarrier cycles, after completing the system clock number statistics of 4 BPSK subcarrier cycle high level, stop counting, namely lock statistical value.Then, by the BPSK subcarrier number of cycles of statistical value divided by statistics, be average system clock number (or claiming " the average time ") H_duty_cnt [5:2] of the high level in 1 BPSK subcarrier cycle.Unit is counting clock (i.e. 13.56MHz system clock).
According to the average system clock number H_duty_cnt [5:2] of the high level of 1 the BPSK subcarrier added up, the low level average system clock number 16-H_duty_cnt [5:2] of 1 BPSK subcarrier namely can be calculated.
By the average system clock number H_duty_cnt [5:2] of described high level, second comparison module, adds that height turns over threshold shift high_shift [3:0], obtain height and turn over threshold value high_threshold [3:0]; Described low level average system clock number 16-H_duty_cnt [5:2] is added the low side-play amount low_shift [3:0] that turns over obtains lowly turning over threshold value low_threshold [3:0].
As shown in Figure 4, Fig. 4 produces logical schematic for height turns over threshold value; According to agreement, in the ideal case, when a high level continue for 16 system clocks, a high tumble is thought; With should a low level continue for 16 system clocks time, think once low upset.The monocyclic high level time that as if statistics goes out is H_duty_cnt [5:2]=9 (ideal value is 8), if then adjudicate a high tumble, should add that one is highly turned over side-play amount high_shift [3:0], i.e. 9+high_shift [3:0], be used for comparing with the count value of low and high level counter, the occurrence measured as this skew is how much should set according to the feature of analog circuit, and ideal value should be that 16-is high turns over ideal value=16-8=8 system clock.Suggestion value reserves surplus compared with ideal value, generally sets 4-6; Lowly turn over threshold value calculation method and height to turn over threshold value identical.
Flip bit sideband signal generation module first, the high level systems clock number statistical value export described BPSK subcarrier low and high level counter and height turn over threshold value and compare, or the low level system clock number statistical value of described BPSK subcarrier low and high level counter output and low threshold value of turning over are compared, obtain court verdict and lock described court verdict, carry-out bit edge locking signal and boundary marker signal.
The invention provides a kind of BPSK subcarrier low and high level counter, as shown in Figure 3, Fig. 3 is BPSK subcarrier low and high level counter principle block diagram in the present embodiment; BPSK subcarrier low and high level counter in the present embodiment, for adding up the high level of each cycle BPSK subcarrier and low level system clock number, at rising edge or the trailing edge clear 0 of described BPSK subcarrier.
This BPSK subcarrier low and high level counter comprises: the first d type flip flop DCF1, the second d type flip flop DCF2, inverter NOT, XOR gate Xor sum counter.
The input end of clock of the first d type flip flop DCF1 and the second d type flip flop DCF2 and the counting input end input system clock Sys_clk of counter.
The data input pin D termination of the first d type flip flop DCF1 receives the BPSK subcarrier signal of input, and its output Q end is held with the data input pin D of the second d type flip flop DCF2 and is connected with an input of XOR gate Xor.
The output Q end of the second d type flip flop DCF2 is connected with another input of described XOR gate Xor.
The input of XOR gate Xor receives the signal of the first d type flip flop DCF1 output and the signal of the second d type flip flop DCF2 output, and its output is connected with counter.
The input of inverter NOT receives the edge locking of the flip bit first signal of input, and its output is connected with the Enable Pin of described counter as counting Enable Pin.
Result and the height of BPSK subcarrier low and high level counter turn over threshold value or lowly turn over after threshold value compares, be more than or equal to height if find turn over threshold value or lowly turn over threshold value, can't judge that height turns over or lowly to turn over, the polarity number of the BPSK subcarrier serial signal must clapped according to upper is adjudicated height and is turned over or lowly to turn over.
Turn over threshold value if counter results is more than or equal to height or lowly turns over threshold value, and the upper one BPSK subcarrier clapped is high level, it is 1 ' b1 that height turns over marking signal, be then defined as high tumble; If otherwise the upper one BPSK subcarrier clapped is low level, it is 1 ' b0 that height turns over marking signal, be then expressed as low upset.
Turn over threshold value if counter results is less than height or lowly turns over threshold value, then representing that signal is without upset.
The statistics supposing BPSK subcarrier low and high level counter is 15, and height turns over threshold value high_threshold [3:0]=14, lowly turn over threshold value low_threshold [3:0]=14, if a upper bat BPSK subcarrier is high level, then height turns over marking signal h_l_sel is 1 ' b1, represents high tumble.If instead under similarity condition, the upper one BPSK subcarrier clapped is low level, and it is 1 ' b0 that height turns over marking signal h_l_sel, represents low upset.Meanwhile, height looks through and surveys locking signal h_l_lock saltus step is that 1 ' b1, BPSK subcarrier closes h_l_lock clearing of having no progeny.
Present invention also offers a kind of BPSK subcarrier correlation demodulation bit boundary defining method, comprise the following steps:
Step 1, utilization BPSK subcarrier low and high level counter, adopt the low and high level of the monocycle BPSK subcarrier after analog-to-digital conversion between local clock contraposition sync period to carry out counting statistics respectively; For the cumulative statistics amount of 4 BPSK subcarriers, BPSK subcarrier high level statistical counter is 6bits;
Step 2, added up rear assembly average, the value of the BPSK subcarrier high level statistical counter of the 2bits that namely moves to left is as the computing reference value of the low and high level of the monocycle BPSK subcarrier during bit synchronization;
Step 3, by the second comparison module, the computing reference value of described high level is added that height turns over side-play amount, low level computing reference value adds that low side-play amount of turning over is turned over threshold value respectively as high first and lowly turn over threshold value;
Step 4, by flip bit sideband signal generation module first, compared with the high level systems clock number statistical value of BPSK subcarrier is turned over threshold value with height, or low level system clock number statistical value is turned over compared with threshold value with low, obtains bit boundary locking signal and bit boundary marking signal.
The present invention, by the statistics of the low and high level of BPSK subcarrier and calculating, according to the rule of the low and high level of actual BPSK subcarrier, can detect high tumble or low upset in an adaptive way.
Finally should be noted that: above embodiment is only for illustration of the technical scheme of the application but not the restriction to its protection range; although with reference to above-described embodiment to present application has been detailed description; those of ordinary skill in the field are to be understood that: those skilled in the art still can carry out all changes, amendment or equivalent replacement to the embodiment of application after reading the application; but these change, revise or be equal to replacement, all applying within the claims awaited the reply.
Claims (9)
1. a BPSK subcarrier demodulation pre-process circuit, is characterized in that: described circuit comprises: BPSK subcarrier low and high level counter and the BPSK subcarrier rising edge counter connected successively, the first comparison module, BPSK subcarrier high level statistical counter, the second comparison module and the circuit of flip bit sideband signal generation first; Described in described BPSK subcarrier low and high level counter connects, flip bit sideband signal produces circuit first;
Described BPSK subcarrier rising edge counter, described BPSK subcarrier high level statistical counter and described BPSK subcarrier low and high level counter receive BPSK subcarrier signal respectively, described second comparison module receives height and turns over threshold shift, produces circuit carry-out bit edge locking signal and boundary marker signal by described decoding pre-process circuit by the described sideband signal of flip bit first.
2. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 1, it is characterized in that: described BPSK subcarrier low and high level counter, for adding up the high level of each cycle BPSK subcarrier and low level system clock number, at rising edge or the trailing edge clear 0 of described BPSK subcarrier.
3. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 2, is characterized in that: described BPSK subcarrier low and high level counter, comprising: the first d type flip flop, the second d type flip flop, inverter, XOR gate sum counter;
The input end of clock of described first d type flip flop and described second d type flip flop and the counting input end receiving system clock of described counter;
The data input pin of described first d type flip flop receives BPSK subcarrier signal, and output connects the data input pin of described second d type flip flop and the input of described XOR gate; The output of described second d type flip flop connects another input phase of described XOR gate;
The output of described XOR gate connects described counter; The input of described inverter receives the signal of flip bit edge locking first, and its output connects the Enable Pin of described counter as counting Enable Pin.
4. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 1, is characterized in that: described BPSK subcarrier rising edge statistical circuit, for adding up the signal number of described BPSK subcarrier between bit sync period.
5. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 1, is characterized in that: described first comparison module, for limiting the count range of described BPSK subcarrier high level statistical counter.
6. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 1, it is characterized in that: described BPSK subcarrier high level statistical counter, according to the count range limited, counting is started after several BPSK subcarrier cycles of instability, for add up continuous multiple bit synchronization phase BPSK subcarrier high period between system clock number, and obtain the average system clock number of monocycle high level; Monocycle low level average system clock number is calculated according to the average system clock number of high level.
7. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 1, is characterized in that: described second comparison module, the average system clock number of described high level is added that height turns over threshold shift, obtains height and turn over threshold value; Described low level average system clock number is added low side-play amount of turning over obtains lowly turning over threshold value.
8. a kind of BPSK subcarrier demodulation pre-process circuit as claimed in claim 1, it is characterized in that: the described sideband signal of flip bit first generation module, the high level systems clock number statistical value export described BPSK subcarrier low and high level counter and height turn over threshold value and compare, or the low level system clock number statistical value of described BPSK subcarrier low and high level counter output and low threshold value of turning over are compared, obtain court verdict and lock described court verdict, carry-out bit edge locking signal and boundary marker signal.
9. a BPSK subcarrier demodulation pre-process circuit, is characterized in that, comprise the steps:
The low and high level of the BPSK subcarrier after analog-to-digital conversion between I, employing local clock contraposition sync period carries out counting statistics respectively;
II, add up the computing reference value of rear acquisition assembly average as the low and high level of the monocycle BPSK subcarrier during bit synchronization;
III, the computing reference value of described high level is added that height turns over side-play amount and turns over threshold value as high first, low level computing reference value is added low side-play amount of turning over turns over threshold value as low first;
IV, the high level statistical value of BPSK subcarrier turned over threshold value with described height compared with, low level statistical value lowly turns over compared with threshold value with described, obtains bit boundary locking signal and bit boundary marking signal.
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| CN103647738A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | 14443 interface BPSK subcarrier demodulation circuit |
| CN104639483A (en) * | 2013-11-11 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Digital correlation demodulation circuit based on 14443-BPSK (binary phase shift keying) subcarriers |
| CN104702552A (en) * | 2013-12-05 | 2015-06-10 | 上海华虹集成电路有限责任公司 | BPSK (Binary Phase Shift Keying) subcarrier related demodulation bit boundary determination circuit and method |
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- 2015-08-27 CN CN201510536391.3A patent/CN105119863A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639483A (en) * | 2013-11-11 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Digital correlation demodulation circuit based on 14443-BPSK (binary phase shift keying) subcarriers |
| CN103647738A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | 14443 interface BPSK subcarrier demodulation circuit |
| CN104702552A (en) * | 2013-12-05 | 2015-06-10 | 上海华虹集成电路有限责任公司 | BPSK (Binary Phase Shift Keying) subcarrier related demodulation bit boundary determination circuit and method |
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