CN103647738A - 14443 interface BPSK subcarrier demodulation circuit - Google Patents
14443 interface BPSK subcarrier demodulation circuit Download PDFInfo
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- CN103647738A CN103647738A CN201310636706.2A CN201310636706A CN103647738A CN 103647738 A CN103647738 A CN 103647738A CN 201310636706 A CN201310636706 A CN 201310636706A CN 103647738 A CN103647738 A CN 103647738A
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Abstract
The invention provides a BPSK subcarrier demodulation circuit of a 14443 interface PCD-end physical layer receiver. The circuit is mainly composed of an analog-to-digital converter, a subcarrier and bit synchronization circuit, a matching accumulator and a decision device. According to the circuit, the analog-to-digital converter is adopted for sampling a subcarrier signal, the amplitude information of the signal is retained, and the anti-interference ability of the circuit and the communication stability are improved through the use of a matching accumulation method in a digital domain.
Description
Technical field:
The BPSK subcarrier demodulation techniques that the present invention relates to 14443 interface PCD end physical layer receivers, can be used for non-contact reader chip Type A212Kbps～848Kbps and Type B receiver.
Background technology:
In contactless smart card field, communication system is divided into read write line (PCD) and card (PICC) two parts.The physical layer signal that PICC end returns by load-modulate, Noise and Interference is inevitably introduced in meeting, after these signals are through carrier wave demodulation, the amplification frequently of PCD end-fire, noise can be introduced to the subcarrier demodulator circuit of next stage.Conventionally the mode that the demodulation of subcarrier adopts is directly with comparator, to be quantified as logical one or 0 signal to numeric field demodulation.
Subcarrier signal directly carries out demodulation at numeric field after comparator quantizes, the small interference of amplitude will be quantified as the low and high level identical with useful signal, and the variation of subcarrier signal width will cause being difficult to identify useful signal and interference from level width, improved demodulation difficulty, reduced the antijamming capability receiving, thereby cause communication easily to make mistakes, communication efficiency reduces.
The present invention adopts analog to digital converter to sample to subcarrier signal, has retained the amplitude information of signal, and mates in numeric field utilization the antijamming capability that cumulative method has improved circuit, has improved communication stability.
Summary of the invention:
The invention provides a kind of 14443 interface BPSK subcarrier demodulator circuits based on analog to digital converter, circuit primary structure comprises: analog to digital converter, subcarrier with bit synchronization circuit, mate accumulator, decision device four parts.It is characterized in that, the mode that circuit is realized demodulation is as follows: analog to digital converter is converted to long number code value by the modulating subcarrier signal of simulation, and outputs it to subcarrier with bit synchronization circuit and mate accumulator; Subcarrier and bit synchronization circuit produce subcarrier synchronizing signal and position lattice signal according to the long number code value of analog to digital converter output, and output it to coupling accumulator; Mate accumulator according to mating cumulative to the long number code value of analog to digital converter output in each lattice interval of subcarrier and bit synchronization circuit output subcarrier synchronizing signal and position lattice signal, end in each lattice interval resets to mating cumulative result, and the cumulative result of coupling is exported to decision device; The numerical value of decision device before ending place in each lattice interval resets to coupling accumulator is once adjudicated, and when the result after judgement is remained to next court verdict and generates.The result of decision device judgement is the data after demodulation.
Its advantage of circuit disclosed in this invention is, analog signal is converted to the digital code value relevant to analogue signal amplitude by analog to digital converter, and not directly with comparator, be quantified as numeral 1 or 0 signal, the amplitude information that has retained signal, make the useful signal that interference that amplitude is less and amplitude are larger be easier to distinguish, avoid list identification signal the deration of signal, improved the probability of success of communication.
It is also advantageous in that circuit disclosed in this invention, described subcarrier and bit synchronization circuit can produce and subcarrier synchronizing signal and the position lattice signal inputting modulating subcarrier signal and synchronize, thereby the action of mating accumulator and decision device is synchronizeed with input signal, increase to greatest extent the discrimination of data 1 signal and data 0 signal, reduce the error rate.
It is also advantageous in that circuit disclosed in this invention, by the cumulative action of coupling of coupling accumulator, the amplitude of useful signal can add up in the same direction, and because interference has randomness, the cumulative direction of its amplitude also has randomness, thereby make useful signal and disturb the accumulation result producing to be easy to distinguish, reduced the error rate.
Described subcarrier and bit synchronization circuit is characterized in that, its clock source comes from local clock, and producing subcarrier synchronizing signal and position lattice signal according to the feature of long number code value corresponding to the modulating subcarrier signal of input, the subcarrier synchronizing signal producing and position lattice signal are all synchronizeed with modulating subcarrier signal.
Described coupling accumulator, it is characterized in that according to the logical value of subcarrier synchronizing signal, the long number code value corresponding to modulating subcarrier signal of input being mated and being added up in each lattice interval, and reset to mating cumulative result at the end in each lattice interval.
Described decision device, is characterized in that the numerical value that the ending in each lattice interval is in before coupling accumulator is resetted once adjudicates, and when the result after judgement is once remained to next court verdict and generates.
Accompanying drawing explanation:
Fig. 1 represents the 14443 interface BPSK subcarrier demodulator circuit structures based on analog to digital converter
Fig. 2 represents waveform or the time dependent schematic diagram of code value of a kind of embodiment of the present invention
Embodiment:
Below in conjunction with accompanying drawing, introduce the embodiment of circuit working.
A kind of 14443 interface BPSK subcarrier demodulator circuits comprise: analog to digital converter, subcarrier with bit synchronization circuit, mate accumulator, decision device; Wherein: analog to digital converter is converted to long number code value by the modulating subcarrier signal of simulation, and output it to subcarrier and bit synchronization circuit and mate accumulator; Subcarrier and bit synchronization circuit produce subcarrier synchronizing signal and position lattice signal according to the long number code value of analog to digital converter output, and output it to coupling accumulator; Mate accumulator according to mating cumulative to the long number code value of analog to digital converter output in each lattice interval of subcarrier and bit synchronization circuit output subcarrier synchronizing signal and position lattice signal, end in each lattice interval resets to mating cumulative result, and the cumulative result of coupling is exported to decision device; The numerical value of decision device before ending place in each lattice interval resets to coupling accumulator is once adjudicated, and when the result after judgement is remained to next court verdict and generates.
In Fig. 2, represent to have seven charts of voltage or code value temporal evolution relation.The analog-modulated subcarrier signal voltage of first graphical presentation input analog-to-digital converter over time; The digital code value size of second graphical presentation analog to digital converter output over time; The subcarrier synchronizing signal of the 3rd graphical presentation subcarrier and bit synchronization circuit output over time; The position lattice signal of the 4th graphical presentation subcarrier and bit synchronization circuit output over time; The code value of the 5th graphical presentation coupling accumulator output over time; The 6th graphical presentation decision device output signal over time, is also the demodulating data of circuit output simultaneously.
Specific works process is as follows: the dc point of subcarrier signal is as the mid point R of analog to digital converter working range and output code value, and establishing the code value of any time subcarrier signal after analog to digital converter is changed is M; Data-signal has multiply periodic unmodulated subcarrier signal as lead code before arriving, circuit can be determined according to the moment that crosses mid point code value R of signal the phase place of subcarrier synchronizing signal, by the method for multicycle average calculating operation, the monocyclic interference of maskable, makes the synchronism of subcarrier synchronizing signal and modulating subcarrier signal more desirable; The generation of bit synchronization signal, according to the wave character of first phase place variation place (time difference that crosses mid point as signal for twice increases), produces a lattice signal; In coupling accumulator lattice interval range in place, the code value of the sampled signal of input is carried out to accumulating operation, establishing its initial value is Q
0, the value after adding up for the n time is Q
n, operation rule is Q between the low period of subcarrier synchronizing signal
n+1=Q
n+ (R-M), Q between the high period of subcarrier synchronizing signal
n+1=Q
n+ (M-R), when each lattice finishes to Q
nvalue resets to Q
0; Decision circuit is at Q
nvalue resets front according to judgement standard Q
0to Q
nvalue is adjudicated, if Q
n> Q
0, export 1, on the contrary output 0, and when court verdict remains to next court verdict generation, the result of terminal decision device output is the data of this circuit demodulation output.
Should be understood that, the present embodiment is used for illustrative purposes only, but not limitation of the present invention.Those skilled in the art can design plurality of optional execution mode not departing under the scope of the invention condition being defined by the following claims, and therefore all technical schemes that are equal to also should belong to category of the present invention.The discrete component of mentioning or module are not got rid of and are had a plurality of this elements or module.
Claims (9)
1. 14443 interface BPSK subcarrier demodulator circuits, is characterized in that comprising: analog to digital converter, subcarrier with bit synchronization circuit, mate accumulator, decision device; Wherein: analog to digital converter is converted to long number code value by the modulating subcarrier signal of simulation, and output it to subcarrier and bit synchronization circuit and mate accumulator; Subcarrier and bit synchronization circuit produce subcarrier synchronizing signal and position lattice signal according to the long number code value of analog to digital converter output, and output it to coupling accumulator; Mate accumulator according to mating cumulative to the long number code value of analog to digital converter output in each lattice interval of subcarrier and bit synchronization circuit output subcarrier synchronizing signal and position lattice signal, end in each lattice interval resets to mating cumulative result, and the cumulative result of coupling is exported to decision device; The numerical value of decision device before ending place in each lattice interval resets to coupling accumulator is once adjudicated, and when the result after judgement is remained to next court verdict and generates.
2. circuit as claimed in claim 1, is characterized in that described analog to digital converter samples to BPSK subcarrier signal, is quantified as long number code value.
3. circuit as claimed in claim 1, is characterized in that described subcarrier and bit synchronization circuit clock source come from local clock.
4. circuit as claimed in claim 1, is characterized in that described subcarrier produces subcarrier synchronizing signal and position lattice signal with bit synchronization circuit according to the feature of long number code value corresponding to the modulating subcarrier signal of input.
5. the circuit as described in claim 1 or 4, is characterized in that subcarrier synchronizing signal and a position lattice signal that described subcarrier produces with bit synchronization circuit all synchronize with modulating subcarrier signal.
6. circuit as claimed in claim 1, is characterized in that described coupling accumulator mates cumulative according to the logical value of subcarrier synchronizing signal in each lattice interval to the long number code value corresponding to modulating subcarrier signal of input.
7. the circuit as described in claim 1 or 6, is characterized in that described coupling accumulator resets to mating cumulative result at the end in each lattice interval.
8. circuit as claimed in claim 1, is characterized in that the numerical value that the ending of described decision device in each lattice interval is in before coupling accumulator is resetted once adjudicates.
9. the circuit as described in claim 1 or 8, while is characterized in that result after described decision device is once adjudicated remains to next court verdict and generates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310636706.2A CN103647738A (en) | 2013-12-03 | 2013-12-03 | 14443 interface BPSK subcarrier demodulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310636706.2A CN103647738A (en) | 2013-12-03 | 2013-12-03 | 14443 interface BPSK subcarrier demodulation circuit |
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| Publication Number | Publication Date |
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| CN103647738A true CN103647738A (en) | 2014-03-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310636706.2A Pending CN103647738A (en) | 2013-12-03 | 2013-12-03 | 14443 interface BPSK subcarrier demodulation circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105119863A (en) * | 2015-08-27 | 2015-12-02 | 赵爽 | BPSK subcarrier demodulation preprocessing circuit and method thereof |
| CN107404452A (en) * | 2016-05-18 | 2017-11-28 | 上海复旦微电子集团股份有限公司 | BPSK demodulation methods and device, receiver |
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| JP2001126413A (en) * | 1999-11-01 | 2001-05-11 | Ricoh Co Ltd | Demodulation circuit and information recording and reproducing device using the circuit |
| CN1401177A (en) * | 2000-12-13 | 2003-03-05 | 三菱电机株式会社 | Receiver |
| US20050169404A1 (en) * | 2003-03-07 | 2005-08-04 | Akira Yamamoto | Demodulator and address information extractor |
| CN1833277A (en) * | 2003-09-02 | 2006-09-13 | 株式会社理光 | Wobble signal demodulating circuit and optical disc |
| CN101267242A (en) * | 2008-05-04 | 2008-09-17 | 浙江大学 | A remote sensing data receiver for satellite territorial station |
| CN101420399A (en) * | 2008-12-12 | 2009-04-29 | 中国电子科技集团公司第七研究所 | Receiver, BPSK demodulation circuit and BPSK demodulation method |
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2013
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001126413A (en) * | 1999-11-01 | 2001-05-11 | Ricoh Co Ltd | Demodulation circuit and information recording and reproducing device using the circuit |
| CN1401177A (en) * | 2000-12-13 | 2003-03-05 | 三菱电机株式会社 | Receiver |
| US20050169404A1 (en) * | 2003-03-07 | 2005-08-04 | Akira Yamamoto | Demodulator and address information extractor |
| CN1833277A (en) * | 2003-09-02 | 2006-09-13 | 株式会社理光 | Wobble signal demodulating circuit and optical disc |
| CN101267242A (en) * | 2008-05-04 | 2008-09-17 | 浙江大学 | A remote sensing data receiver for satellite territorial station |
| CN101420399A (en) * | 2008-12-12 | 2009-04-29 | 中国电子科技集团公司第七研究所 | Receiver, BPSK demodulation circuit and BPSK demodulation method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105119863A (en) * | 2015-08-27 | 2015-12-02 | 赵爽 | BPSK subcarrier demodulation preprocessing circuit and method thereof |
| CN107404452A (en) * | 2016-05-18 | 2017-11-28 | 上海复旦微电子集团股份有限公司 | BPSK demodulation methods and device, receiver |
| CN107404452B (en) * | 2016-05-18 | 2020-09-22 | 上海复旦微电子集团股份有限公司 | BPSK demodulation method and device, and receiver |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Applicant after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Applicant before: Beijing CEC Huada Electronic Design Co., Ltd. |
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