CN104701235B - A kind of forming method of shallow trench - Google Patents
A kind of forming method of shallow trench Download PDFInfo
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- CN104701235B CN104701235B CN201310647706.2A CN201310647706A CN104701235B CN 104701235 B CN104701235 B CN 104701235B CN 201310647706 A CN201310647706 A CN 201310647706A CN 104701235 B CN104701235 B CN 104701235B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
A kind of forming method of shallow trench, including the following steps: provide semiconductor substrate, the semiconductor substrate surface is sequentially formed with N tunic layer from the bottom up, and N is positive integer；Successively step etching corresponding film layer from top to bottom, until shallow trench is formed in the semiconductor substrate, wherein wafer is rotated horizontally predetermined angular before every step etching.Constantly rotating wafer angle keeps finally formed shallow trench consistent in the depth of different location, ensure that the yields of semiconductor devices the present invention before next step etches to alleviate the etch amount difference of different location.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of forming methods of shallow trench.
Background technique
With the reduction of integrated circuit dimensions, the device for constituting circuit must be placed more densely packed, with adapt to can on chip
The confined space.Since current research is dedicated to the density of active device on the unit area for increasing semiconductor substrate, institute
Become more important with being effectively dielectrically separated between circuit.
Shallow trench isolation (STI) technology possesses multinomial technique and electrically isolates advantage, including can reduce and occupy wafer table
The area in face increases the integrated level of device simultaneously, keeps surface flatness and the erosion of less channel width etc..Therefore, element at present
Such as the active area isolation layer of MOS circuit has mostly used greatly shallow ditch groove separation process to make.The specific process steps are as follows:
With reference to Fig. 1, pad oxide 102 is formed on a semiconductor substrate 100, and the method for forming pad oxide 102 is hot oxygen
Change method, the material of pad oxide 102 are specially silica；It is formed on pad oxide 102 with Low Pressure Chemical Vapor Deposition
Corrosion barrier layer 104, for protecting following pad oxide 102 from corrosion during subsequent etching, wherein corrosion stops
The material of layer 104 is silicon nitride etc.；Then, amorphous carbon layer 106 is formed on corrosion barrier layer 104, in subsequent ashing
The film layer of protection below when photoresist layer and anti-reflecting layer；Bottom anti-reflection layer 108 is formed on amorphous carbon layer 106, is used
To protect lower face mask layer to influence in photoetching process from light；Photoresist layer is formed in bottom anti-reflection layer 108 with spin-coating method
110；Through overexposure, developing process, the first opening 111 corresponding with subsequent shallow trench is formed on photoresist layer.
As shown in Fig. 2, being mask with the photoresist layer 110 in Fig. 1, via the first opening, etching bottom anti-reflecting layer 108
With amorphous carbon layer 106 to corrosion barrier layer 104 is exposed, the second opening 112 is formed；Ashing method removes photoresist layer.
As shown in figure 3, in Fig. 2 bottom anti-reflection layer 108 and amorphous carbon layer 106 be exposure mask, along second opening carve
Corrosion barrier layer 104 and pad oxide 102 are lost to semiconductor substrate 100 is exposed, and form third opening 113；Ashing method removes bottom
Portion's anti-reflecting layer and amorphous carbon layer.
As shown in figure 4, being exposure mask with corrosion barrier layer 104 and pad oxide 102, along third opening etch semiconductor substrates
100, form shallow trench 115；Full megohmite insulant is filled into shallow trench, is formed shallow trench isolation (not shown), adjacent shallow trench
Region between isolation is active area.
But the shallow trench that the prior art is formed can be very big in different location depth disparity, in turn results in yields reduction.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of shallow trench, prevents finally formed shallow trench in difference
Depth difference can be very big.
To solve the above problems, the present invention provides a kind of forming method of shallow trench, a kind of forming method of shallow trench, packet
It includes the following steps: semiconductor substrate is provided, the semiconductor substrate surface is sequentially formed with N tunic layer from the bottom up, and N is positive whole
Number；Successively step etching corresponding film layer from top to bottom, until shallow trench is formed in the semiconductor substrate, wherein before every step etching
Wafer is rotated horizontally into predetermined angular.
Optionally, before forming shallow trench, offer control wafer is further comprised the steps of:；It is sequentially formed from the bottom up in control wafer
There is N tunic layer；Successively step etching corresponding film layer from top to bottom, until forming shallow trench in the semiconductor substrate；Pass through measurement
Determine maximum degree of asymmetry between different location shallow trench.
Optionally, the predetermined angular rotated before every step etching is identical or different.
Optionally, when the predetermined angular rotated before every step etching is identical, predetermined angular is equal to maximum degree of asymmetry
Divided by etch step number.
Optionally, when the predetermined angular difference rotated before the every step etching, logical before every step etching rotation determines angle
Summation is equal to maximum degree of asymmetry.
Optionally, the maximum degree of asymmetry range is 1 °~360 °.
Optionally, described rotate horizontally is that level rotates clockwise or level rotates counterclockwise.
Optionally, the N tunic layer is two layers of film layer, is divided into positioned at the pad oxide of semiconductor substrate surface and positioned at pad
Corrosion barrier layer in oxide layer.
Optionally, optionally, the N tunic layer be trilamellar membrane layer, be divided into the pad oxide positioned at semiconductor substrate surface,
Corrosion barrier layer on pad oxide and the amorphous carbon layer on corrosion barrier layer.
Optionally, the N tunic layer is four tunic layers, is divided into the pad oxide positioned at semiconductor substrate surface, is located at pad
Corrosion barrier layer in oxide layer, the amorphous carbon layer on corrosion barrier layer and the bottom anti-reflective on amorphous carbon layer
Penetrate layer.
The present invention also provides a kind of forming methods of shallow trench, including the following steps: semiconductor substrate is provided, it is described partly to lead
Body substrate surface is sequentially formed with N tunic layer from the bottom up, and N is positive integer；Successively step etching corresponding film layer from top to bottom, directly
To shallow trench is formed in the semiconductor substrate, wafer is rotated horizontally and the matched angle of maximum degree of asymmetry before any step etching
Degree.
Optionally, before forming shallow trench, offer control wafer is further comprised the steps of:；It is sequentially formed from the bottom up in control wafer
There is N tunic layer；Successively step etching corresponding film layer from top to bottom, until forming shallow trench in the semiconductor substrate；Pass through measurement
Determine maximum degree of asymmetry between different location shallow trench.
Optionally, the maximum degree of asymmetry range is 1 °~360 °.
Optionally, described rotate horizontally is that level rotates clockwise or level rotates counterclockwise.
Optionally, the N tunic layer is two layers of film layer, is divided into positioned at the pad oxide of semiconductor substrate surface and positioned at pad
Corrosion barrier layer in oxide layer.
Optionally, the N tunic layer is trilamellar membrane layer, is divided into the pad oxide positioned at semiconductor substrate surface, is located at pad
Corrosion barrier layer in oxide layer and the amorphous carbon layer on corrosion barrier layer.
Optionally, the N tunic layer is four tunic layers, is divided into the pad oxide positioned at semiconductor substrate surface, is located at pad
Corrosion barrier layer in oxide layer, the amorphous carbon layer on corrosion barrier layer and the bottom anti-reflective on amorphous carbon layer
Penetrate layer.
Compared with prior art, technical solution of the present invention has the advantage that successively step etching is corresponding from top to bottom
Film layer, until shallow trench is formed in the semiconductor substrate, wherein wafer is rotated horizontally predetermined angular before every step etching.When
When primary etching, different location just has etching difference；When second of etching, wafer rotation predetermined angular is performed etching, is made
Be etched when etching first time the small region of depth in current etching by more etching removals a bit, and when etching first time
The big region of the depth that is etched is in current etching by etching off after a little while except a bit；And so on, constantly before next step etches
Rotating wafer angle makes finally formed shallow trench in the depth one of different location to alleviate the etch amount difference of different location
It causes, ensure that the yields of semiconductor devices.
In addition, successively step etching corresponding film layer from top to bottom, until shallow trench is formed in the semiconductor substrate, any
Wafer is rotated horizontally and the matched angle of maximum degree of asymmetry before step etching.When etching first time, different location can be generated
Etching difference；By wafer horizontal rotation and the matched angle of maximum degree of asymmetry before any step etching, then perform etching again,
To alleviate the etch amount difference of different location, keeps finally formed shallow trench consistent in the depth of different location, ensure that and partly lead
The yields of body device.
Detailed description of the invention
Fig. 1 to Fig. 4 is the technical process schematic diagram that the prior art forms fleet plough groove isolation structure；
Fig. 5 to Figure 11 is the technical process schematic diagram that one embodiment of the invention forms fleet plough groove isolation structure；
Figure 12 to Figure 16 is the technical process schematic diagram that another embodiment of the present invention forms fleet plough groove isolation structure；
Figure 17 to Figure 21 is the technical process schematic diagram that yet another embodiment of the invention forms fleet plough groove isolation structure.
Specific embodiment
It is existing formed shallow trench isolation to separate active area during, can due to reaction chamber chamber piasma be distributed
The slight difference of subtle asymmetry or etch rate is carved after will cause same processing step in wafer different location film layer
The amount meeting difference of erosion, and if forming shallow trench needs multistep etching technics, it accumulates, makes finally formed shallow by difference
Groove can be very big in different location depth disparity, in turn results in yields reduction.
The present invention carries out the level angle of wafer before every step etching during forming shallow trench to solve this problem
Adjustment keeps the angle of final adjustment consistent with maximum degree of asymmetry, to alleviate the inhomogenous of etch amount, makes finally formed shallow ridges
Slot is consistent in the depth of different location, ensure that the yields of semiconductor devices.Or by wafer level before any step etching
Rotation and the matched angle of maximum degree of asymmetry, go to the strong position of subsequent etching amount for the weak region of etch amount, are effectively relieved
As etching technics defect and caused by the different problem of shallow groove depths.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Specific embodiments of the present invention will be described in detail with reference to the accompanying drawing.
It is formed before shallow ditch groove structure in following the first two embodiments, is required to first determine that different location is shallow on wafer
Maximum degree of asymmetry between groove, the specific method is as follows:
Formed before shallow ditch groove structure in following embodiments, be required to first determine on wafer different location shallow trench it
Between maximum degree of asymmetry, the specific method is as follows:
During any batch processes, there is a control wafer to ensure that the process flow provides control wafer；Shallow trench every
From in structure-forming process, pad oxide, corrosion barrier layer, amorphous carbon layer, bottom are sequentially formed from the bottom up in control wafer
Anti-reflecting layer and photoresist layer；By common process (i.e. the process of the prior art) successively step etching corresponding membrane from top to bottom
Layer, until forming shallow trench in the semiconductor substrate；By measuring the degree of asymmetry determined between different location shallow trench, with true
Fixed maximum degree of asymmetry X.
Subsequent rotation angle is determined according to maximum degree of asymmetry X and etch step number: rotation angle, θ=maximum is asymmetric
Spend X/ etch step number.The maximum degree of asymmetry is usually to combine the maximum difference of the shallow groove depths of different location according to warp
It tests and is judged.
Assuming that maximum degree of asymmetry is 180 degree, etch step is 10 steps, can choose every step etching rotation same angular
Degree, i.e., the angle, θ of wafer rotation is 18 degree before every step etches.Every step etching different rotation angle can also be chosen, as long as finally
The angle of wafer rotation is equal to maximum degree of asymmetry.
And if maximum degree of asymmetry is 90 degree, etch step is 10 steps, can choose every step etching rotation same angular
Degree, i.e., the angle, θ of wafer rotation is 10 degree before every step etches.Every step etching different rotation angle can also be chosen, as long as finally
The angle of wafer rotation is equal to maximum degree of asymmetry.
Then using maximum degree of asymmetry as 180 degree, etch step is one embodiment of the invention of lower mask body Fig. 5 to Figure 11
3 steps, then for the identical angle, θ of wafer rotation is 60 degree before every step etching.
Fig. 5 to Figure 11 is the technical process schematic diagram that one embodiment of the invention forms fleet plough groove isolation structure.
With reference to Fig. 5, semiconductor substrate 200 is provided, the semiconductor substrate 200 can be silicon, germanium or silicon-on-insulator etc.
Semiconductor material；Pad oxide 202 is formed on semiconductor substrate 200；Corrosion barrier layer 204 is formed on pad oxide 202,
For protecting following pad oxide 202 from corrosion in subsequent etch process；Then, it is formed on corrosion barrier layer 204
Amorphous carbon layer 206, for the film layer of protection below in subsequent ashing photoresist layer and anti-reflecting layer；In amorphous carbon layer
Bottom anti-reflection layer 208 is formed on 206, to protect lower face mask layer to influence in photoetching process from light；With spin-coating method the bottom of at
Photoresist layer 210 is formed on portion's anti-reflecting layer 208；Through overexposure, developing process, formed and subsequent shallow trench on photoresist layer
Corresponding first opening 211.
In the present embodiment, the method for forming pad oxide 202 is thermal oxidation method, and the material of pad oxide 202 is specially oxygen
SiClx.
In the present embodiment, the method for forming corrosion barrier layer 204 is Low Pressure Chemical Vapor Deposition or plasmaassisted
Chemical vapour deposition technique, the material of corrosion barrier layer 204 are silicon nitride.
In the present embodiment, the method for forming amorphous carbon layer 206 is chemical vapour deposition technique.
It is placed in reaction chamber as shown in fig. 6, rotating wafer to first position, in the wafer substrate 200 under
It is supreme to be formed with pad oxide 202, corrosion barrier layer 204, amorphous carbon layer 206, bottom anti-reflection layer 208 and photoresist layer
210。
In the present embodiment, it is θ that the position when first position and control wafer are placed, which has rotated clockwise angle,1, the θ1=
60 degree.
As shown in fig. 7, being exposure mask with the photoresist layer 208 in Fig. 5, via the first opening 211, etching bottom anti-reflecting layer
208 and amorphous carbon layer 206 to expose corrosion barrier layer 204, formed second opening 212；Ashing method or the removal of wet etching method
Photoresist layer in Fig. 5.
As shown in figure 8, rotating wafer level from first position to the second position, the second position and first position it
Between angle be θ1(θ1=60 degree), at this point, the film layer in the wafer substrate 200 from the bottom to top is pad oxide 202, corrosion
Barrier layer 204, amorphous carbon layer 206 and bottom anti-reflection layer 208.
As shown in figure 9, in Fig. 7 bottom anti-reflection layer 208 and amorphous carbon layer 206 be exposure mask, along second opening carve
Corrosion barrier layer 204 and pad oxide 202 are lost to semiconductor substrate 200 is exposed, and form third opening 213；Ashing method removes bottom
Portion's anti-reflecting layer and amorphous carbon layer.
As shown in Figure 10, wafer level is rotated from the second position to the third place, the third place and the second position
Between angle be θ1(θ1=60 degree), at this point, the film layer in the wafer substrate 200 from the bottom to top is pad oxide 202, corruption
Lose barrier layer 204.
It as shown in figure 11, is exposure mask with corrosion barrier layer 204 and pad oxide 202, along third opening etching semiconductor lining
Bottom 200 forms shallow trench 215；Full megohmite insulant is filled into shallow trench, is formed shallow trench isolation (not shown), adjacent shallow ridges
Region between slot isolation is active area.
Figure 12 to Figure 16 is the technical process schematic diagram that another embodiment of the present invention forms fleet plough groove isolation structure.Such as Figure 12
It is shown, semiconductor substrate 300 is provided；Pad oxide 302 is formed in semiconductor substrate 300；It is formed on pad oxide 302 rotten
Barrier layer 304 is lost, for protecting following pad oxide 302 from corrosion in subsequent etch process；Then, stop in corrosion
Amorphous carbon layer 306 is formed on layer 304, for the film layer of protection below in subsequent ashing photoresist layer and anti-reflecting layer；
Bottom anti-reflection layer 308 is formed on amorphous carbon layer 306, to protect lower face mask layer to influence in photoetching process from light；
Photoresist layer 310 is formed in bottom anti-reflection layer 308 with spin-coating method；Through overexposure, developing process, formed on photoresist layer
The first opening 311 corresponding with subsequent shallow trench.
It as shown in figure 13, is exposure mask with the photoresist layer 308 in Figure 12, via the first opening 311, etching bottom antireflection
Layer 308 and amorphous carbon layer 306 form the second opening 312 to corrosion barrier layer 304 is exposed；Ashing method or wet etching method are gone
Except the photoresist layer in Figure 12.
As shown in figure 14, wafer is rotated horizontally to first position, the first position is to match with maximum degree of asymmetry
Angle (it is described maximum degree of asymmetry acquisition it is identical as a upper embodiment), at this point, in the wafer substrate 300 from the bottom to top
Film layer be pad oxide 302, corrosion barrier layer 304, amorphous carbon layer 306 and bottom anti-reflection layer 308.
In the present embodiment, the position when first position and control wafer are placed has been rotated clockwise and maximum degree of asymmetry
The angle matched is 180 degree.In addition to this, it can also be 15 degree, 30 degree, 45 degree, 60 degree, 75 degree, 90 degree, 105 degree, 120 degree, 135
Degree, 165 degree etc., is specifically determined by maximum degree of asymmetry by 150 degree.
As shown in figure 15, in Figure 13 bottom anti-reflection layer 308 and amorphous carbon layer 306 be exposure mask, along second opening
Corrosion barrier layer 304 and pad oxide 302 are etched to semiconductor substrate 300 is exposed, forms third opening 313；Ashing method removal
Bottom anti-reflection layer and amorphous carbon layer.
It as shown in figure 16, is exposure mask with corrosion barrier layer 304 and pad oxide 302, along third opening etching semiconductor lining
Bottom 300 forms shallow trench 315；Full megohmite insulant is filled into shallow trench, is formed shallow trench isolation (not shown), adjacent shallow ridges
Region between slot isolation is active area.
In addition to embodiment, the step of rotating wafer, can also be put in etching bottom anti-reflecting layer 308 and amorphous carbon layer 306
To corrosion barrier layer 304 is exposed, formed before the second opening 312.Or it is put in and is with corrosion barrier layer 304 and pad oxide 302
Exposure mask is formed before shallow trench 315 along third opening etch semiconductor substrates 300.
It is formed before shallow ditch groove structure in this following embodiments, is required to first determine different location shallow ridges on wafer
Maximum degree of asymmetry between slot, the specific method is as follows:
Formed before shallow ditch groove structure in following embodiments, be required to first determine on wafer different location shallow trench it
Between maximum degree of asymmetry, the specific method is as follows:
During any batch processes, there is a control wafer to ensure that the process flow provides control wafer；Shallow trench every
From in structure-forming process, pad oxide, corrosion barrier layer and photoresist layer are sequentially formed from the bottom up in control wafer；By usual
Process (i.e. the process of the prior art) successively step etching corresponding film layer from top to bottom, until being formed in the semiconductor substrate shallow
Groove；By measuring the degree of asymmetry determined between different location shallow trench, to determine maximum degree of asymmetry X.
Subsequent rotation angle is determined according to maximum degree of asymmetry X and etch step number: rotation angle, θ=maximum is asymmetric
Spend X/ etch step number.The maximum degree of asymmetry is usually to combine the maximum difference of the shallow groove depths of different location according to warp
It tests and is judged.
Then with maximum degree of asymmetry for 90 degree, etch step is one embodiment of the invention of lower mask body Figure 17 to Figure 21
2 steps, then every step etches the different angle of preceding wafer rotation: etching for the first time, wafer rotates clockwise θ2=30 degree, second
Etching wafer is clockwise turned to again for 60 degree.
Figure 17 to Figure 21 is the technical process schematic diagram that yet another embodiment of the invention forms fleet plough groove isolation structure.
With reference to Figure 17, semiconductor substrate 400 is provided；Pad oxide 402 is formed in semiconductor substrate 400；It is aoxidized in pad
Corrosion barrier layer 404 is formed on layer 402, for protecting following pad oxide 202 from corrosion in subsequent etch process；With
Spin-coating method forms photoresist layer 406 on corrosion barrier layer 404；Through overexposure, developing process, formed with after on photoresist layer
Continue corresponding first opening 405 of shallow trench.
As shown in figure 18, wafer is rotated to first position and is placed in reaction chamber, in the wafer substrate 400 under
It is supreme to be formed with pad oxide 402, corrosion barrier layer 404 and photoresist layer 406.
In the present embodiment, it is θ that the position when first position and control wafer are placed, which has rotated clockwise angle,2, the θ2=
30 degree.
It as shown in figure 19, is exposure mask with the photoresist layer 406 in Figure 17, via the first opening 405, etching exposes corrosion resistance
Barrier 404 and pad oxide 402 form the second opening 407 to semiconductor substrate 400 is exposed；Ashing method or wet etching method are gone
Except the photoresist layer in Figure 17.
As shown in figure 20, wafer level is rotated clockwise to the second position from first position, the second position and the
Angle between one position is θ3, at this point, the film layer in the wafer substrate 200 from the bottom to top is pad oxide 202, corrosion resistance
Barrier 204, amorphous carbon layer 206 and bottom anti-reflection layer 208.
In the present embodiment, it is θ that the second position, which has rotated clockwise angle relative to the position of first position,3, the θ3
=60 degree.
It as shown in figure 21, is exposure mask with corrosion barrier layer 404 and pad oxide 402, along the second opening etching semiconductor lining
Bottom 400 forms shallow trench 408；Full megohmite insulant is filled into shallow trench, is formed shallow trench isolation (not shown), adjacent shallow ridges
Region between slot isolation is active area.
In addition to above-described embodiment is to rotate clockwise, it is also an option that rotation counterclockwise.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of shallow trench, characterized in that it comprises the following steps:
Semiconductor substrate is provided, the semiconductor substrate surface is sequentially formed with N tunic layer from the bottom up, and N is positive integer；
The photoresist layer with the first opening is formed, first opening is corresponding with the shallow trench being subsequently formed；
Successively step etching corresponding film layer from top to bottom, until shallow trench is formed in the semiconductor substrate, wherein before every step etching
Wafer is rotated horizontally into predetermined angular；
Wherein, the predetermined angular summation rotated before every step etching is equal to maximum degree of asymmetry.
2. the forming method of shallow trench according to claim 1, which is characterized in that before forming shallow trench, further include
Step:
Control wafer is provided；
It is sequentially formed with N tunic layer from the bottom up in control wafer；
Successively step etching corresponding film layer from top to bottom, until forming shallow trench in the semiconductor substrate；
Maximum degree of asymmetry between different location shallow trench is determined by measuring.
3. the forming method of shallow trench according to claim 2, which is characterized in that rotated before every step etching predetermined
Angle is identical or different.
4. the forming method of shallow trench according to claim 3, which is characterized in that rotated before every step etching pre-
Determine angle it is identical when, predetermined angular is equal to maximum degree of asymmetry divided by etch step number.
5. the forming method of shallow trench according to claim 3, which is characterized in that rotated before every step etching predetermined
Angle is different.
6. the forming method of shallow trench according to claim 2, which is characterized in that the maximum degree of asymmetry range is 1 °
~360 °.
7. the forming method of shallow trench according to claim 1, which is characterized in that described rotate horizontally is horizontal clockwise
Rotation or horizontal rotation counterclockwise.
8. the forming method of shallow trench according to claim 1 or 2, which is characterized in that the N tunic layer is two membranes
Layer, is divided into the corrosion barrier layer positioned at the pad oxide of semiconductor substrate surface and on pad oxide.
9. the forming method of shallow trench according to claim 1 or 2, which is characterized in that the N tunic layer is trilamellar membrane
Layer is divided into positioned at the pad oxide of semiconductor substrate surface, the corrosion barrier layer on pad oxide and is located at corrosion blocking
Amorphous carbon layer on layer.
10. the forming method of shallow trench according to claim 1 or 2, which is characterized in that the N tunic layer is four tunics
Layer is divided into the pad oxide positioned at semiconductor substrate surface, the corrosion barrier layer on pad oxide, is located at corrosion barrier layer
On amorphous carbon layer and the bottom anti-reflection layer on amorphous carbon layer.
11. a kind of forming method of shallow trench, characterized in that it comprises the following steps:
Semiconductor substrate is provided, the semiconductor substrate surface is sequentially formed with N tunic layer from the bottom up, and N is positive integer；
The photoresist layer with the first opening is formed, first opening is corresponding with the shallow trench being subsequently formed；
Successively step etching corresponding film layer from top to bottom, until shallow trench is formed in the semiconductor substrate, before any step etching
Wafer is rotated horizontally and the matched angle of maximum degree of asymmetry.
12. the forming method of shallow trench according to claim 11, which is characterized in that before forming shallow trench, also wrap
Include step:
Control wafer is provided；
It is sequentially formed with N tunic layer from the bottom up in control wafer；
Successively step etching corresponding film layer from top to bottom, until forming shallow trench in the semiconductor substrate；
Maximum degree of asymmetry between different location shallow trench is determined by measuring.
13. the forming method of shallow trench according to claim 12, which is characterized in that it is described maximum degree of asymmetry range be
1 °~360 °.
14. the forming method of shallow trench according to claim 11, which is characterized in that described rotate horizontally is horizontal up time
Needle rotation or horizontal rotation counterclockwise.
15. the forming method of shallow trench according to claim 11 or 12, which is characterized in that the N tunic layer is two layers
Film layer is divided into the corrosion barrier layer positioned at the pad oxide of semiconductor substrate surface and on pad oxide.
16. the forming method of shallow trench according to claim 11 or 12, which is characterized in that the N tunic layer is three layers
Film layer is divided into positioned at the pad oxide of semiconductor substrate surface, the corrosion barrier layer on pad oxide and is located at corrosion resistance
Amorphous carbon layer in barrier.
17. the forming method of shallow trench according to claim 11 or 12, which is characterized in that the N tunic layer is four layers
Film layer is divided into the pad oxide positioned at semiconductor substrate surface, the corrosion barrier layer on pad oxide, is located at corrosion blocking
Amorphous carbon layer on layer and the bottom anti-reflection layer on amorphous carbon layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090088A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Filling method for isolation groove |
| CN101459107A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove isolation structure and etching |
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| US6531413B2 (en) * | 2000-12-05 | 2003-03-11 | United Microelectronics Corp. | Method for depositing an undoped silicate glass layer |
| US7354834B2 (en) * | 2003-06-04 | 2008-04-08 | Dongbu Electronics Co., Ltd. | Semiconductor devices and methods to form trenches in semiconductor devices |
| US7806988B2 (en) * | 2004-09-28 | 2010-10-05 | Micron Technology, Inc. | Method to address carbon incorporation in an interpoly oxide |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090088A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Filling method for isolation groove |
| CN101459107A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove isolation structure and etching |
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