CN104701235A - Method for forming shallow trench - Google Patents
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- CN104701235A CN104701235A CN201310647706.2A CN201310647706A CN104701235A CN 104701235 A CN104701235 A CN 104701235A CN 201310647706 A CN201310647706 A CN 201310647706A CN 104701235 A CN104701235 A CN 104701235A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The invention relates to a method for forming a shallow trench, comprising the following steps: providing a semiconductor substrate, wherein N film layers are sequentially formed on the surface of the semiconductor substrate from bottom to top, and N is a positive integer; and sequentially etching the film layers step by step from top to bottom until a shallow trench is formed in the semiconductor substrate, wherein a wafer is horizontally rotated by a predetermined angle before each step of etching. According to the method of the invention, the wafer is constantly rotated by a certain angle before next step of etching to alleviate the difference between different positions in the amount of etching, so that the ultimately formed shallow trench has uniform depth in different positions, and the yield rate of semiconductor devices is ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of formation method of shallow trench.
Background technology
Along with the reduction of integrated circuit dimensions, the device of forming circuit must be placed more thick and fast, to adapt to the confined space available on chip.Due to the density of active device in the unit are that current research is devoted to increase Semiconductor substrate, so the effective insulation isolation between circuit becomes more important.
Shallow trench isolation has multinomial technique and electrical isolation advantage from (STI) technology, comprises and can reduce the integrated level that the area taking crystal column surface increases device simultaneously, keeps surface flatness and less channel width erosion etc.Therefore, the active area isolation layer of current element such as MOS circuit adopts shallow ditch groove separation process to make mostly.Concrete technology step is as follows:
With reference to figure 1, form pad oxide 102 on a semiconductor substrate 100, the method forming pad oxide 102 is thermal oxidation method, and the material of pad oxide 102 is specially silicon dioxide; On pad oxide 102, form corrosion barrier layer 104 with Low Pressure Chemical Vapor Deposition, for the pad oxide 102 below protecting in subsequent etching process from corrosion, wherein the material of corrosion barrier layer 104 is silicon nitride etc.; Then, corrosion barrier layer 104 forms amorphous carbon layer 106, for protecting the rete below it when follow-up ashing photoresist layer and anti-reflecting layer; Amorphous carbon layer 106 is formed bottom anti-reflection layer 108, affects from light in order to the lower face mask layer of protection in photoetching process; In bottom anti-reflection layer 108, photoresist layer 110 is formed with spin-coating method; Through overexposure, developing process, photoresist layer forms first opening 111 corresponding with follow-up shallow trench.
As shown in Figure 2, with the photoresist layer 110 in Fig. 1 for mask, via the first opening, etching bottom anti-reflecting layer 108 and amorphous carbon layer 106, to exposing corrosion barrier layer 104, form the second opening 112; Ashing method removes photoresist layer.
As shown in Figure 3, with the bottom anti-reflection layer 108 in Fig. 2 and amorphous carbon layer 106 for mask, along the second opening etching corrosion barrier layer 104 and pad oxide 102 to exposing Semiconductor substrate 100, form the 3rd opening 113; Ashing method removes bottom anti-reflection layer and amorphous carbon layer.
As shown in Figure 4, with corrosion barrier layer 104 and pad oxide 102 for mask, along the 3rd opening etch semiconductor substrates 100, form shallow trench 115; In shallow trench, fill full megohmite insulant, form shallow trench isolation from (not shown), the region between adjacent shallow trench isolation is active area.
But the shallow trench that prior art is formed can be very large in diverse location depth disparity, and then cause yields to reduce.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of shallow trench, prevents the final shallow trench formed can be very large in diverse location depth disparity.
For solving the problem, the invention provides a kind of formation method of shallow trench, a kind of formation method of shallow trench, comprises the following steps: to provide Semiconductor substrate, and described semiconductor substrate surface is formed with N tunic layer from the bottom up successively, and N is positive integer; The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate, wherein often all rotates predetermined angular by wafer level before step etching.
Optionally, before formation shallow trench, also step is comprised: provide control wafer; Control wafer is formed with N tunic layer from the bottom up successively; The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate; Maximum degree of asymmetry between diverse location shallow trench is determined by measuring.
Optionally, the predetermined angular rotated before described often step etching is identical or different.
Optionally, when the predetermined angular rotated before described often step etching is identical, predetermined angular equals maximum degree of asymmetry divided by etch step number.
Optionally, when the predetermined angular of the front rotation of described often step etching is different, leading to often before the rotation of step etching determines angle summation and equals maximum degree of asymmetry.
Optionally, described maximum degree of asymmetry scope is 1 ° ~ 360 °.
Optionally, horizontally rotate described in and to turn clockwise for level or level is rotated counterclockwise.
Optionally, described N tunic layer is two-layer rete, is divided into the pad oxide being positioned at semiconductor substrate surface and the corrosion barrier layer be positioned on pad oxide.
Optionally, optionally, described N tunic layer is trilamellar membrane layer, is divided into the pad oxide being positioned at semiconductor substrate surface, the amorphous carbon layer being positioned at the corrosion barrier layer on pad oxide and being positioned on corrosion barrier layer.
Optionally, described N tunic layer is four tunic layers, the bottom anti-reflection layer be divided into the pad oxide being positioned at semiconductor substrate surface, the corrosion barrier layer be positioned on pad oxide, being positioned at the amorphous carbon layer on corrosion barrier layer and being positioned on amorphous carbon layer.
The present invention also provides a kind of formation method of shallow trench, comprises the following steps: to provide Semiconductor substrate, and described semiconductor substrate surface is formed with N tunic layer from the bottom up successively, and N is positive integer; The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate, rotates the angle of mating with maximum degree of asymmetry by wafer level before arbitrary step etching.
Optionally, before formation shallow trench, also step is comprised: provide control wafer; Control wafer is formed with N tunic layer from the bottom up successively; The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate; Maximum degree of asymmetry between diverse location shallow trench is determined by measuring.
Optionally, described maximum degree of asymmetry scope is 1 ° ~ 360 °.
Optionally, horizontally rotate described in and to turn clockwise for level or level is rotated counterclockwise.
Optionally, described N tunic layer is two-layer rete, is divided into the pad oxide being positioned at semiconductor substrate surface and the corrosion barrier layer be positioned on pad oxide.
Optionally, described N tunic layer is trilamellar membrane layer, is divided into the pad oxide being positioned at semiconductor substrate surface, the amorphous carbon layer being positioned at the corrosion barrier layer on pad oxide and being positioned on corrosion barrier layer.
Optionally, described N tunic layer is four tunic layers, the bottom anti-reflection layer be divided into the pad oxide being positioned at semiconductor substrate surface, the corrosion barrier layer be positioned on pad oxide, being positioned at the amorphous carbon layer on corrosion barrier layer and being positioned on amorphous carbon layer.
Compared with prior art, technical scheme of the present invention has the following advantages: the corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate, wherein often all wafer level is rotated predetermined angular before step etching.When first time etches, diverse location just has etching difference; When second time etches, wafer is rotated predetermined angular etch, make to be etched when first time etching the little region of the degree of depth in current etching time removed a bit by many etchings, and the large region of the degree of depth that is etched when first time etching in current etching time by etching off after a little while except a bit; By that analogy, constantly rotating wafer angle before next step etching, to alleviate the etch amount difference of diverse location, makes the final shallow trench formed consistent in the degree of depth of diverse location, ensure that the yields of semiconductor device.
In addition, the corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate, rotates the angle of mating with maximum degree of asymmetry by wafer level before arbitrary step etching.When first time etches, diverse location can produce etching difference; Before arbitrary step etching, wafer level is rotated the angle of mating with maximum degree of asymmetry, and then etch, to alleviate the etch amount difference of diverse location, make the final shallow trench formed consistent in the degree of depth of diverse location, ensure that the yields of semiconductor device.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the technical process schematic diagram that prior art forms fleet plough groove isolation structure;
Fig. 5 to Figure 11 is the technical process schematic diagram that one embodiment of the invention forms fleet plough groove isolation structure;
Figure 12 to Figure 16 is the technical process schematic diagram that another embodiment of the present invention forms fleet plough groove isolation structure;
Figure 17 to Figure 21 is the technical process schematic diagram that yet another embodiment of the invention forms fleet plough groove isolation structure.
Embodiment
Existing at formation shallow trench isolation from in the process separating active area, can be trickle asymmetric due to the distribution of reaction chamber chamber piasma, or the difference slightly of etch rate, in the amount meeting difference that wafer diverse location rete is etched after same processing step can be caused, if and formation shallow trench needs multistep etching technics, so through difference accumulation, the final shallow trench formed is made can very greatly, and then to cause yields to reduce in diverse location depth disparity.
For addressing this problem the present invention in formation shallow trench process, often before step etching, the level angle of wafer is adjusted, make the angle of final adjustment consistent with maximum degree of asymmetry, to alleviate the heterogeneity of etch amount, make the final shallow trench formed consistent in the degree of depth of diverse location, ensure that the yields of semiconductor device.Or before arbitrary step etching, wafer level is rotated the angle of mating with maximum degree of asymmetry, region weak for etch amount is gone to the strong position of subsequent etching amount, effectively alleviate the problem that the shallow groove depths that causes due to the defect of etching technics differs.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Form shallow ditch groove structure in following the first two embodiment before, all need the maximum degree of asymmetry first determined on wafer between diverse location shallow trench, concrete grammar is as follows:
Form shallow ditch groove structure in following embodiment before, all need the maximum degree of asymmetry first determined on wafer between diverse location shallow trench, concrete grammar is as follows:
Due in arbitrary batch processes process, all there is a control wafer to guarantee that this technological process provides control wafer; In fleet plough groove isolation structure forming process, control wafer forms pad oxide, corrosion barrier layer, amorphous carbon layer, bottom anti-reflection layer and photoresist layer from the bottom up successively; By common flow process (i.e. the flow process of prior art) the corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate; By measuring the degree of asymmetry determined between diverse location shallow trench, to determine maximum degree of asymmetry X.
The follow-up anglec of rotation is determined: anglec of rotation θ=maximum degree of asymmetry X/ etch step number according to maximum degree of asymmetry X and etch step number.Described maximum degree of asymmetry normally rule of thumb carries out judging in conjunction with the maximum difference of the shallow groove depths of diverse location.
Suppose that maximum degree of asymmetry is 180 degree, etch step is 10 steps, and can choose often step etching and rotate equal angular, the angle θ that before namely often walking etching, wafer rotates is 18 degree.Also often step etching different rotation angle can be chosen, as long as the angle that final wafer rotates equals maximum degree of asymmetry.
And if maximum degree of asymmetry is 90 degree, etch step is 10 steps, and can choose often step etching and rotate equal angular, the angle θ that before namely often walking etching, wafer rotates is 10 degree.Also often step etching different rotation angle can be chosen, as long as the angle that final wafer rotates equals maximum degree of asymmetry.
One embodiment of the invention of lower mask body Fig. 5 to Figure 11 is then 180 degree with maximum degree of asymmetry, and etch step is 3 steps, and so often before step etching, wafer rotates identical angle θ be 60 degree is example.
Fig. 5 to Figure 11 is the technical process schematic diagram that one embodiment of the invention forms fleet plough groove isolation structure.
With reference to figure 5, provide Semiconductor substrate 200, described Semiconductor substrate 200 can be the semi-conducting materials such as silicon, germanium or silicon-on-insulator; Form pad oxide 202 on semiconductor substrate 200; Pad oxide 202 forms corrosion barrier layer 204, for the pad oxide 202 below protecting in subsequent etch process from corrosion; Then, corrosion barrier layer 204 forms amorphous carbon layer 206, for protecting the rete below it when follow-up ashing photoresist layer and anti-reflecting layer; Amorphous carbon layer 206 is formed bottom anti-reflection layer 208, affects from light in order to the lower face mask layer of protection in photoetching process; In bottom anti-reflection layer 208, photoresist layer 210 is formed with spin-coating method; Through overexposure, developing process, photoresist layer forms first opening 211 corresponding with follow-up shallow trench.
In the present embodiment, the method forming pad oxide 202 is thermal oxidation method, and the material of pad oxide 202 is specially silica.
In the present embodiment, the method forming corrosion barrier layer 204 is Low Pressure Chemical Vapor Deposition or plasma auxiliary chemical vapor deposition method, and the material of corrosion barrier layer 204 is silicon nitride.
In the present embodiment, the method forming amorphous carbon layer 206 is chemical vapour deposition technique.
As shown in Figure 6, wafer is rotated and is positioned in reaction chamber to primary importance, described wafer substrate 200 has been formed with pad oxide 202, corrosion barrier layer 204, amorphous carbon layer 206, bottom anti-reflection layer 208 and photoresist layer 210 from the bottom to top.
In the present embodiment, the angle that turned clockwise of position when described primary importance and control wafer are placed is θ
1, described θ
1=60 degree.
As shown in Figure 7, with the photoresist layer 208 in Fig. 5 for mask, via the first opening 211, etching bottom anti-reflecting layer 208 and amorphous carbon layer 206, to exposing corrosion barrier layer 204, form the second opening 212; Ashing method or wet etching method remove the photoresist layer in Fig. 5.
As shown in Figure 8, wafer level rotated to the second place from primary importance, the angle between the described second place and primary importance is θ
1(θ
1=60 degree), now, in described wafer substrate 200, rete is from the bottom to top pad oxide 202, corrosion barrier layer 204, amorphous carbon layer 206 and bottom anti-reflection layer 208.
As shown in Figure 9, with the bottom anti-reflection layer 208 in Fig. 7 and amorphous carbon layer 206 for mask, along the second opening etching corrosion barrier layer 204 and pad oxide 202 to exposing Semiconductor substrate 200, form the 3rd opening 213; Ashing method removes bottom anti-reflection layer and amorphous carbon layer.
As shown in Figure 10, wafer level rotated to the 3rd position from the second place, the described 3rd angle between position and the second place is θ
1(θ
1=60 degree), now, in described wafer substrate 200, rete is from the bottom to top pad oxide 202, corrosion barrier layer 204.
As shown in figure 11, with corrosion barrier layer 204 and pad oxide 202 for mask, along the 3rd opening etch semiconductor substrates 200, form shallow trench 215; In shallow trench, fill full megohmite insulant, form shallow trench isolation from (not shown), the region between adjacent shallow trench isolation is active area.
Figure 12 to Figure 16 is the technical process schematic diagram that another embodiment of the present invention forms fleet plough groove isolation structure.As shown in figure 12, Semiconductor substrate 300 is provided; Semiconductor substrate 300 is formed pad oxide 302; Pad oxide 302 forms corrosion barrier layer 304, for the pad oxide 302 below protecting in subsequent etch process from corrosion; Then, corrosion barrier layer 304 forms amorphous carbon layer 306, for protecting the rete below it when follow-up ashing photoresist layer and anti-reflecting layer; Amorphous carbon layer 306 is formed bottom anti-reflection layer 308, affects from light in order to the lower face mask layer of protection in photoetching process; In bottom anti-reflection layer 308, photoresist layer 310 is formed with spin-coating method; Through overexposure, developing process, photoresist layer forms first opening 311 corresponding with follow-up shallow trench.
As shown in figure 13, with the photoresist layer 308 in Figure 12 for mask, via the first opening 311, etching bottom anti-reflecting layer 308 and amorphous carbon layer 306, to exposing corrosion barrier layer 304, form the second opening 312; Ashing method or wet etching method remove the photoresist layer in Figure 12.
As shown in figure 14, wafer level is rotated to primary importance, described primary importance is and the angle that maximum degree of asymmetry is mated (acquisition of described maximum degree of asymmetry is identical with a upper embodiment), now, in described wafer substrate 300, rete is from the bottom to top pad oxide 302, corrosion barrier layer 304, amorphous carbon layer 306 and bottom anti-reflection layer 308.
In the present embodiment, position when described primary importance is placed with control wafer has turned clockwise the angle of mating with maximum degree of asymmetry, is 180 degree.In addition, can also be 15 degree, 30 degree, 45 degree, 60 degree, 75 degree, 90 degree, 105 degree, 120 degree, 135 degree, 150 degree, 165 degree etc., specifically be determined by maximum degree of asymmetry.
As shown in figure 15, with the bottom anti-reflection layer 308 in Figure 13 and amorphous carbon layer 306 for mask, along the second opening etching corrosion barrier layer 304 and pad oxide 302 to exposing Semiconductor substrate 300, form the 3rd opening 313; Ashing method removes bottom anti-reflection layer and amorphous carbon layer.
As shown in figure 16, with corrosion barrier layer 304 and pad oxide 302 for mask, along the 3rd opening etch semiconductor substrates 300, form shallow trench 315; In shallow trench, fill full megohmite insulant, form shallow trench isolation from (not shown), the region between adjacent shallow trench isolation is active area.
Except embodiment, the step of rotating wafer can also be put in etching bottom anti-reflecting layer 308 and amorphous carbon layer 306 to exposing corrosion barrier layer 304, before forming the second opening 312.Or be put in corrosion barrier layer 304 and pad oxide 302 for mask, along the 3rd opening etch semiconductor substrates 300, before forming shallow trench 315.
Form shallow ditch groove structure in this following embodiment before, all need the maximum degree of asymmetry first determined on wafer between diverse location shallow trench, concrete grammar is as follows:
Form shallow ditch groove structure in following embodiment before, all need the maximum degree of asymmetry first determined on wafer between diverse location shallow trench, concrete grammar is as follows:
Due in arbitrary batch processes process, all there is a control wafer to guarantee that this technological process provides control wafer; In fleet plough groove isolation structure forming process, control wafer forms pad oxide, corrosion barrier layer and photoresist layer from the bottom up successively; By common flow process (i.e. the flow process of prior art) the corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate; By measuring the degree of asymmetry determined between diverse location shallow trench, to determine maximum degree of asymmetry X.
The follow-up anglec of rotation is determined: anglec of rotation θ=maximum degree of asymmetry X/ etch step number according to maximum degree of asymmetry X and etch step number.Described maximum degree of asymmetry normally rule of thumb carries out judging in conjunction with the maximum difference of the shallow groove depths of diverse location.
One embodiment of the invention of lower mask body Figure 17 to Figure 21 is then 90 degree with maximum degree of asymmetry, and etch step is 2 steps, the different angles that so often before step etching, wafer rotates: first time etching, wafer turns clockwise θ
2=30 degree, it is example that second time etching wafer clockwise turns to 60 degree again.
Figure 17 to Figure 21 is the technical process schematic diagram that yet another embodiment of the invention forms fleet plough groove isolation structure.
With reference to Figure 17, provide Semiconductor substrate 400; Semiconductor substrate 400 is formed pad oxide 402; Pad oxide 402 forms corrosion barrier layer 404, for the pad oxide 202 below protecting in subsequent etch process from corrosion; On corrosion barrier layer 404, photoresist layer 406 is formed with spin-coating method; Through overexposure, developing process, photoresist layer forms first opening 405 corresponding with follow-up shallow trench.
As shown in figure 18, wafer is rotated and is positioned in reaction chamber to primary importance, described wafer substrate 400 has been formed with pad oxide 402, corrosion barrier layer 404 and photoresist layer 406 from the bottom to top.
In the present embodiment, the angle that turned clockwise of position when described primary importance and control wafer are placed is θ
2, described θ
2=30 degree.
As shown in figure 19, with the photoresist layer 406 in Figure 17 for mask, via the first opening 405, etching exposes corrosion barrier layer 404 and pad oxide 402 to exposing Semiconductor substrate 400, forms the second opening 407; Ashing method or wet etching method remove the photoresist layer in Figure 17.
As shown in figure 20, wafer level is gone to the second place from primary importance dextrorotation, the angle between the described second place and primary importance is θ
3, now, in described wafer substrate 200, rete is from the bottom to top pad oxide 202, corrosion barrier layer 204, amorphous carbon layer 206 and bottom anti-reflection layer 208.
In the present embodiment, the described second place is θ relative to the position of the primary importance angle that turned clockwise
3, described θ
3=60 degree.
As shown in figure 21, with corrosion barrier layer 404 and pad oxide 402 for mask, along the second opening etch semiconductor substrates 400, form shallow trench 408; In shallow trench, fill full megohmite insulant, form shallow trench isolation from (not shown), the region between adjacent shallow trench isolation is active area.
Except above-described embodiment is and turns clockwise, can also select to be rotated counterclockwise.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a formation method for shallow trench, is characterized in that, comprise the following steps:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with N tunic layer from the bottom up successively, and N is positive integer;
The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate, wherein often all rotates predetermined angular by wafer level before step etching.
2. the formation method of shallow trench according to claim 1, is characterized in that, before formation shallow trench, also comprises step:
Control wafer is provided;
Control wafer is formed with N tunic layer from the bottom up successively;
The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate;
Maximum degree of asymmetry between diverse location shallow trench is determined by measuring.
3. the formation method of shallow trench according to claim 2, is characterized in that, the predetermined angular rotated before described often step etching is identical or different.
4. the formation method of shallow trench according to claim 3, is characterized in that, when the predetermined angular rotated before described often step etching is identical, predetermined angular equals maximum degree of asymmetry divided by etch step number.
5. the formation method of shallow trench according to claim 3, is characterized in that, when the predetermined angular of the front rotation of described often step etching is different, leading to often before the rotation of step etching determines angle summation and equal maximum degree of asymmetry.
6. the formation method of shallow trench according to claim 2, is characterized in that, described maximum degree of asymmetry scope is 1 ° ~ 360 °.
7. the formation method of shallow trench according to claim 1, is characterized in that, described in horizontally rotate and to turn clockwise for level or level is rotated counterclockwise.
8. the formation method of shallow trench according to claim 1 and 2, is characterized in that, described N tunic layer is two-layer rete, is divided into the pad oxide being positioned at semiconductor substrate surface and the corrosion barrier layer be positioned on pad oxide.
9. the formation method of shallow trench according to claim 1 and 2, it is characterized in that, described N tunic layer is trilamellar membrane layer, is divided into the pad oxide being positioned at semiconductor substrate surface, the amorphous carbon layer being positioned at the corrosion barrier layer on pad oxide and being positioned on corrosion barrier layer.
10. the formation method of shallow trench according to claim 1 and 2, it is characterized in that, described N tunic layer is four tunic layers, the bottom anti-reflection layer be divided into the pad oxide being positioned at semiconductor substrate surface, the corrosion barrier layer be positioned on pad oxide, being positioned at the amorphous carbon layer on corrosion barrier layer and being positioned on amorphous carbon layer.
The formation method of 11. 1 kinds of shallow trenchs, is characterized in that, comprise the following steps:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with N tunic layer from the bottom up successively, and N is positive integer;
The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate, rotates the angle of mating with maximum degree of asymmetry by wafer level before arbitrary step etching.
The formation method of 12. shallow trenchs according to claim 11, is characterized in that, before formation shallow trench, also comprises step:
Control wafer is provided;
Control wafer is formed with N tunic layer from the bottom up successively;
The corresponding rete of step etching successively from top to bottom, until form shallow trench in the semiconductor substrate;
Maximum degree of asymmetry between diverse location shallow trench is determined by measuring.
The formation method of 13. shallow trenchs according to claim 12, is characterized in that, described maximum degree of asymmetry scope is 1 ° ~ 360 °.
The formation method of 14. shallow trenchs according to claim 11, is characterized in that, described in horizontally rotate and to turn clockwise for level or level is rotated counterclockwise.
The formation method of 15. shallow trenchs according to claim 11 or 12, it is characterized in that, described N tunic layer is two-layer rete, is divided into the pad oxide being positioned at semiconductor substrate surface and the corrosion barrier layer be positioned on pad oxide.
16. the formation method of the shallow trench according to claim 11 or 12, it is characterized in that, described N tunic layer is trilamellar membrane layer, is divided into the pad oxide being positioned at semiconductor substrate surface, the amorphous carbon layer being positioned at the corrosion barrier layer on pad oxide and being positioned on corrosion barrier layer.
17. the formation method of the shallow trench according to claim 11 or 12, it is characterized in that, described N tunic layer is four tunic layers, the bottom anti-reflection layer be divided into the pad oxide being positioned at semiconductor substrate surface, the corrosion barrier layer be positioned on pad oxide, being positioned at the amorphous carbon layer on corrosion barrier layer and being positioned on amorphous carbon layer.
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|---|---|---|---|---|
| US20020068416A1 (en) * | 2000-12-05 | 2002-06-06 | Chris Hsieh | Method for depositing an undopped silicate glass layer |
| US20040248373A1 (en) * | 2003-06-04 | 2004-12-09 | Geon-Ook Park | Semiconductor devices and methods to form trenches in semiconductor devices |
| US20060065286A1 (en) * | 2004-09-28 | 2006-03-30 | Niraj Rana | Method to address carbon incorporation in an interpoly oxide |
| CN101090088A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Filling method for isolation groove |
| CN101459107A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove isolation structure and etching |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020068416A1 (en) * | 2000-12-05 | 2002-06-06 | Chris Hsieh | Method for depositing an undopped silicate glass layer |
| US20040248373A1 (en) * | 2003-06-04 | 2004-12-09 | Geon-Ook Park | Semiconductor devices and methods to form trenches in semiconductor devices |
| US20060065286A1 (en) * | 2004-09-28 | 2006-03-30 | Niraj Rana | Method to address carbon incorporation in an interpoly oxide |
| CN101090088A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Filling method for isolation groove |
| CN101459107A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove isolation structure and etching |
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