CN104660081B - A kind of active clamp dual three-level frequency converter and its loss balancing modulation algorithm - Google Patents
A kind of active clamp dual three-level frequency converter and its loss balancing modulation algorithm Download PDFInfo
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Abstract
A kind of active clamp dual three-level frequency converter and its loss balancing modulation algorithm, belong to medium-high voltage frequency converter and modulation algorithm.The frequency converter includes pre-charge circuit, the level rectifying circuit of active clamp three, capacitor filter, active clamp three-level inverter circuit, 36 road pulse driving circuits and control panel；Wherein the level rectifying circuit of active clamp three, capacitor filter and active clamp three-level inverter circuit are connected using stack bus bar, pre-charge circuit is connected in the level rectifying circuit front-end of active clamp three, controller by 36 road pulse driving circuits with the level rectifying circuit of active clamp three and active clamp three-level inverter circuit.The optimum option that the present invention passes through active clamp three-level converter redundancy nought state, modulated using seven section space vectors are improved, loss of the reduction per two power devices in phase bridge arm inside, so as to improve the voltage utilization and load capacity of frequency converter, there is provided a kind of practical medium-high voltage frequency converter for the percent harmonic distortion of reduction voltage x current.
Description
Technical field
The present invention relates to a kind of medium-high voltage frequency converter and modulation algorithm, and in particular to a kind of active clamp dual three-level frequency conversion
Device and its loss balancing modulation algorithm.
Background technology
Energy shortage and environmental pollution are the common global problems that the mankind currently face.China's energy it is relatively poor and
Energy utilization rate is low, and economic growth is presented extensive, to the effective using very urgent in China of the energy.In Eleventh Five-Year Plan rule
In drawing, China proposes to set up resource-conserving and environment-friendly society, Development of Circular economy, realizes sustainable development
Conception.NPC three-level converters are widely used in industry, shipping industry, mining industry and traction application in terms of pressure, but have
The individual shortcoming for failing to overcome so far substantially is exactly the loss of traditional NPC three-level inverters power device in the process of running
Imbalance, is lifted which greatly limits the capacity of frequency converter and power device switching frequency.Become for the level of NPC tri-
This shortcoming of frequency device, Berlin, Germany University of Science and Technology professor T.Bruckner proposes the topology knot of active clamp three-level converter
Structure, to solve the shortcoming produced by the uneven NPC with alleviation of loss distribution.
Space vector modulation algorithm is a kind of pulse width modulation algorithm of multi-level frequency conversion device, and conventional carrier pulsewidth modulation is calculated
Method is compared, and has higher voltage utilization and relatively low percent harmonic distortion, is more applicable for the high performance motor such as vector controlled
Control strategy.At present, carried based PWM algorithm is used active clamp three-level converter, it is low to there is voltage utilization, humorous more
The big shortcoming of ripple aberration rate.
The content of the invention
The invention aims to provide a kind of active clamp dual three-level frequency converter and its loss balancing modulation algorithm, solution
Certainly in frequency converter running, unbalanced technical problem is lost in power device, improves voltage utilization and reduction voltage electricity
The percent harmonic distortion of stream.
The object of the present invention is achieved like this：The frequency converter includes pre-charge circuit, the level rectifying of active clamp three electricity
Road, capacitor filter, active clamp three-level inverter circuit, 36 road pulse driving circuits and controller；Wherein active clamp
Three level rectifying circuits, capacitor filter and active clamp three-level inverter circuit are connected using stack bus bar, precharge electricity
Road includes digital signal processor DSP and field programmable gate array in the level rectifying circuit front-end of active clamp three, controller
FPGA, wherein digital signal processor DSP and on-site programmable gate array FPGA produce the control pulse of 36 tunnels by bus communication
Signal, is connected by optical fiber with drive circuit, 36 road pulse driving circuits and the level rectifying circuit of active clamp three and active pincers
Position three-level inverter circuit connection；The level rectifying circuit of active clamp three and active clamp three-level inverter circuit per phase bridge arm by
Six IGBT are constituted；
The loss balancing modulation algorithm of the frequency converter, comprises the following steps：
The first step, according to the difference of power factor, it is determined that the primary and secondary nought state chosen；
Second step, defines modulation degree firstIn formula：VrefFor reference voltage vector, VdcFor DC voltage；So
Afterwards according to modulation degree m difference, the Dynamic gene k=0.5+0.5*m for determining primary and secondary nought state action time is calculated；In formula：K is
Dynamic gene, m is modulation degree；
The action time of nought state is designated as t in 3rd step, each carrier cycle0, according to Dynamic gene k difference, mainly
The action time of nought state is k*t0, the action time of secondary nought state is (1-k) * t0；
4th step, when power factor is equal to 1, in a carrier cycle, selection vector, which is only existed, once to be switched, and is defined
6 kinds of output voltage number of state indexes are respectively 1-6；When nought state and P-state switch, use vector order for：[4→3→1→1
→ 3 → 4], when N-state and nought state switch, use vector order for：[6→2→5→5→2→6]；
5th step, according to the sequence of operation of vector and action time, produces gate electrode drive signals, to transducer power device
Switch over.
Beneficial effect, by adopting the above-described technical solution, the active clamp dual three-level frequency converter and its damage of the present invention
Consumption balance modulation algorithm can reduce the damage of two power devices inside every phase bridge arm compared with traditional NPC three-level converters
Consumption, so that two power device losses are relatively low inside per phase bridge arm, it is possible to increase the load capacity and switching frequency of frequency converter
Lifting；Compared with conventional active clamper three-level converter carried based PWM algorithm, the voltage for improving frequency converter is utilized
Rate, reduces the percent harmonic distortion of voltage x current.
Brief description of the drawings
Fig. 1 is the system construction drawing of active clamp dual three-level frequency converter of the present invention.
Fig. 2 is active clamp tri-level inversion side structure figure of the present invention.
Fig. 3 is the level fundamental space polar plot of active clamp three of the present invention.
Fig. 4 is the SVPWM waveforms of segmentation the first great Qu first communities of tri- level of NPC seven of the present invention.
Fig. 5 is the SVPWM waveforms of level loss balancing the first great Qu first communities of active clamp three of the present invention.
Embodiment
One embodiment of the present of invention is further described below in conjunction with the accompanying drawings；
Fig. 1 is the system construction drawing of the active clamp dual three-level frequency converter of the present invention, and it is electric that the frequency converter includes precharge
Road, the level rectifying circuit of active clamp three, capacitor filter, active clamp three-level inverter circuit, 36 tunnel pulsed drive electricity
Road and DSP+FPGA control panels；The level rectifying circuit of active clamp three, capacitor filter and active clamp tri-level inversion electricity
Road is connected using stack bus bar, and pre-charge circuit includes data signal in the level rectifying circuit front-end of active clamp three, controller
Processor DSP and on-site programmable gate array FPGA, wherein digital signal processor DSP and on-site programmable gate array FPGA lead to
Cross bus communication, produce 36 road control waves, be connected by optical fiber with drive circuit, 36 road pulse driving circuits with it is active
The level rectifying circuit of clamper three and the connection of active clamp three-level inverter circuit；The level rectifying circuit of active clamp three and active pincers
Position three-level inverter circuit is made up of per phase bridge arm six IGBT；
Active clamp dual three-level frequency converter loss balancing space vector modulation algorithm is as follows：
The first step, according to the difference of power factor, it is determined that the primary and secondary nought state chosen：
As shown in Fig. 2 active clamp three-level converter has 6 power devices per phase bridge arm, therefore nought state has four kinds
Output mode：OU1, OU2, OL1, OL2, the on off state and output voltage of A phases are shown in Table 1.
The ANPC three-level converter on off states of table 1
The modulated degree m and power factor pf of loss distribution situation of active clamp three-level converter power device shadow
Ring：In the case of different modulation degree m, load current it is of different sizes, and then influence power device loss distribution；Work as power
When factor pf is different, the flow direction of load current and the conducting of device and switching can be influenceed, when pf is equal to 1 or -1, ANPC conversion
The loss skewness of device is more notable, therefore the present invention only considers boundary condition.
As shown in table 1, the commutation mode switched between output state P and O has 4 kinds： WithOutput state N and O switching equally also have four kinds.The loss of power device is all under each case
Differ, therefore the action time of reasonable distribution nought state, it is possible to realize the loss balancing control of power device.Although active
Clamper three-level converter has multiple power device participation work under various commutation modes, but substantially produces switching loss
Device there was only two, the power device conducting and switching when load current is positive and negative are respectively as shown in tables 2 and 3.
The electric current of table 2 is timing change of current device
The change of current device when electric current of table 3 is bears
The change of current provided in table 2 and table 3 can be divided into 4 classes according to the difference of the sense of current：Mode 1：Positive voltage negative current；
Mode 2：Positive voltage positive current；Mode 3：Negative voltage positive current；Mode 4：Negative voltage negative current.
For active clamp three-level converter, when power factor is that 1, modulation degree is higher, per the T of phase bridge arm2And T3Hair
Heat is the most serious, and loss is maximum.In order to solve this problem, the reduction T to be tried one's best2And T3On-state loss, according to power factor
Difference, the action time of four kinds of modes is also different：As 0≤pf≤1, mode 2 and the action time of mode 4 are longer, when -1≤
During pf≤0, mode 1 and the action time of mode 3 are longer.
For the loss of balance power device, during mode 1, nought state chooses OU2 first, secondly chooses OL1；During mode 2,
Nought state chooses OL1 first, secondly chooses OU2；During mode 3, nought state chooses OL2 first, secondly chooses OU1；During mode 4,
Nought state chooses OU1 first, secondly chooses OL2, and the primary and secondary nought state of selection is as shown in table 4.
The primary and secondary nought state of table 4
Second step, according to modulation degree m difference, calculates the Dynamic gene k for determining primary and secondary nought state action time：
For the loss of balance power device, the ON time of two kinds of nought states is by modulation degree m and power under different modes
Factor pf is determined.Wherein, modulation degreeIn formula：VrefFor reference voltage vector, VdcFor DC voltage.When power because
When number is 1, the 4 two kinds of changes of current of mode 2 and mode are only existed, in a carrier cycle T, A phase upper half bridge arm power devices are led
The logical time is as shown in table 5.
Switch device conductive time during 5 pf=1 of table
As shown in Table 5, the ON time of device is determined by modulation degree m and k.When k increases, T2、D5ON time subtract
It is few, T5、D2ON time increase, T1、D1ON time it is constant.With the increase of modulation degree, T2Loss is higher, and heating is more
Seriously, therefore its ON time is accordingly reduced.In the case of different modulation degree, in order to which balance power device is lost, k's takes
Value is different, when modulation degree is relatively low, and power device loss is relatively low, in order to simplify relation such as formula (1) institute of calculating, k and modulation degree m
Show.
K=0.5+0.5*m (1)
3rd step, determines the action time of primary and secondary nought state：
It is every mutually to have 6 kinds of on off states for active clamp three-level converter, therefore frequency converter has 216 kinds of switch shapes
State.
In alpha-beta plane, the polar plot corresponding to active clamp three-level converter on off state is as shown in figure 3, wherein X
Represent any one in four kinds of nought states.It is divided into 6 big region, each big region is divided into 6 zonules again, according to reference voltage
The difference in residing region, can be synthesized, voltage vector is divided into four classes by different voltage vectors：Zero vector (V0), short vector (V1-
V6), middle vector (V7-V12) and long vector (V13-V18)。
The action time of active clamp three-level converter vector and on off sequence can be obtained according to NPC, in order to balance
Loss is, it is necessary to choose different nought states.Using the segmentation SVPWM of Central Symmetry seven, by taking the first great Qu first communities as an example, switch
Sequence is as shown in table 6.As seen from table per the switching of the switching for mutually only existing nought state and P-state, or N-state and nought state.
The action time of nought state is designated as t in each carrier cycle0, according to Dynamic gene k difference, main nought state
Action time is k*t0, the action time of secondary nought state is (1-k) * t0。
The segmentation on off sequence of 6 first great Qu first communities of table seven
4th step, it is determined that the switching sequence in each carrier cycle：
The segmentation SVPWM waveforms of tri- level of NPC seven are as shown in figure 4, active clamp three-level converter loss balancing SVPWM ripples
Shape is as shown in figure 5, the calculating nought state resultant action time, is uniformly allocated, when nought state and P-state switching, using vector
Sequentially it is：[4 → 3 → 1 → 1 → 3 → 4], when N-state and nought state switch, use vector order for：[6→2→5→5→2
→6]。
5th step, according to the sequence of operation of vector and action time, produces gate electrode drive signals, to transducer power device
Switch over.
The present invention described in detail above.It should be appreciated that the ordinary skill of this area just can root without creative work
Many modifications and variations are made according to the design of the present invention.Therefore, all technical staff in the art exist under this invention's idea
The technical scheme obtained on the basis of prior art by logic analysis, reasoning, all should be in the guarantor being defined in the patent claims
In the range of shield.
Claims (1)
1. a kind of active clamp dual three-level frequency converter, the frequency converter includes pre-charge circuit, the level rectifying of active clamp three electricity
Road, capacitor filter, active clamp three-level inverter circuit, 36 road pulse driving circuits and controller；Wherein active clamp
Three level rectifying circuits, capacitor filter and active clamp three-level inverter circuit are connected using stack bus bar, precharge electricity
Road includes digital signal processor DSP and field programmable gate array in the level rectifying circuit front-end of active clamp three, controller
FPGA, wherein digital signal processor DSP and on-site programmable gate array FPGA produce the control pulse of 36 tunnels by bus communication
Signal, is connected by optical fiber with drive circuit, 36 road pulse driving circuits and the level rectifying circuit of active clamp three and active pincers
Position three-level inverter circuit connection；The level rectifying circuit of active clamp three and active clamp three-level inverter circuit per phase bridge arm by
Six IGBT are constituted；
It is characterized in that：Loss balancing modulation algorithm based on frequency converter, loss of the reduction per two power devices in phase bridge arm inside,
Comprise the following steps：
The first step, according to the difference of power factor, it is determined that the primary and secondary nought state chosen；
The selection of primary and secondary nought state is determined by two factors：（1）The polarity of voltage x current；（2）Power factor (PF)；
Described（1）The polarity of voltage x current：The change of current can be divided into 4 classes according to the difference of the sense of current：Mode 1：Positive voltage is born
Electric current；Mode 2：Positive voltage positive current；Mode 3：Negative voltage positive current；Mode 4：Negative voltage negative current；
Described（2）Power factor (PF)：For the loss of balance power device, during mode 1, nought state chooses OU2 first, secondly selects
Take OL1；During mode 2, nought state chooses OL1 first, secondly chooses OU2；During mode 3, nought state chooses OL2 first, secondly selects
Take OU1；During mode 4, nought state chooses OU1 first, secondly chooses OL2；
Second step, defines modulation degree first, in formula：V refFor reference voltage vector,V dcFor DC voltage；So
Afterwards according to modulation degreemDifference, calculate determine primary and secondary nought state action time Dynamic genek=0.5+0.5*m；In formula：kFor
Dynamic gene,mFor modulation degree；
The action time of nought state is designated as t in 3rd step, each carrier cycle0, according to Dynamic genekDifference, main nought state
Action time bek*t0, the action time of secondary nought state is（1-k）*t0；
4th step, when power factor is equal to 1, in a carrier cycle, selection vector, which is only existed, once to be switched, and defines 6 kinds
Output voltage number of state indexes is respectively 1-6, respectively P, OU1, OU2, OL1, OL2 and N；When nought state and P-state switch, adopt
It is with vector order：[4 → 3 → 1 → 1 → 3 → 4] are [OL1-OU2-P-P-OU2-0L1], when N-state and nought state switching,
Use vector order for：[6 → 2 → 5 → 5 → 2 → 6] are [N-OU1-OL2-OL2-OU1-N]；
Above-mentioned P, OU1, OU2, OL1, OL2 and N are the level state of output；
Active clamp three-level converter has 6 power devices per phase bridge arm, there is four kinds of nought state output modes, is respectively：
OU1, OU2, OL1 and OL2, have it is a kind of+V dc/ 2 output modes are P, have it is a kind of-V dc/ 2 output modes are N；It is various defeated in A phases
The on off state and output voltage of exit pattern are as follows：
Level state P, the first power device T1, the second power device T2 and the 6th power device T6 conductings, the 3rd power device
T3, the 4th power device T4 and the 5th power device T5 shut-off, output voltage for+V dc/2；
Level state OU1, the second power device T2 and the 5th power device T5 are turned on, the first power device T1, the 3rd power device
Part T3, the 4th power device T4 and the 6th power device T6 shut-offs, output voltage is zero；
Level state OU2, the second power device T2, the 4th power device T4 and the 5th power device T5 conductings, the first power device
Part T1, the 3rd power device T3 and the 6th power device T6 shut-offs, output voltage is zero；
Level state OL1, the 3rd power device T3 and the 6th power device T6 are turned on, the first power device T1, the second power device
Part T2, the 4th power device T4 and the 5th power device T5 shut-offs, output voltage is zero；
Level state OL2, the first power device T1, the 3rd power device T3 and the 6th power device T6 conductings, the second power device
Part T2, the 4th power device T4 and the 5th power device T5 shut-offs, output voltage is zero；
Level state N, the 3rd power device T3, the 4th power device T4 and the 5th power device T5 conductings, the first power device
T1, the second power device T2 and the 6th power device T6 shut-off, output voltage for-V dc/2；
5th step, according to the sequence of operation of vector and action time, produces gate electrode drive signals, transducer power device is carried out
Switching.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105337524B (en) * | 2015-11-25 | 2018-06-29 | 安徽大学 | Three level active neutral-point-clamped photovoltaic DC-to-AC converter switching loss balance control methods |
| CN108387830B (en) * | 2018-01-16 | 2020-06-02 | 中国矿业大学 | IGBT over-current detection device and method based on active clamp feedback |
| CN108377104B (en) * | 2018-03-15 | 2020-02-28 | 浙江大学 | Space vector control method applied to hybrid three-phase three-level active neutral point clamped converter |
| CN110912134A (en) * | 2019-11-29 | 2020-03-24 | 中国船舶重工集团公司第七一九研究所 | Multi-level active power filter with low harmonic content |
| CN113765428B (en) * | 2021-08-31 | 2023-09-05 | 河北科技大学 | Active neutral point clamped three-level converter and regulation and control method thereof |
| CN115473419A (en) * | 2022-10-12 | 2022-12-13 | 阳光电源股份有限公司 | Loss equalization modulation method and converter for ANPC topology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6411067B1 (en) * | 2001-02-20 | 2002-06-25 | Abb Ab | Voltage source converters operating either as back-to-back stations or as parallel static var compensators |
| CN1393049A (en) * | 2000-09-13 | 2003-01-22 | Abb研究有限公司 | Controlling and regulating method for three level power converter having active clamping switches, and device therefor |
| CN101013818A (en) * | 2007-02-07 | 2007-08-08 | 哈尔滨九洲电气股份有限公司 | Three-level medium voltage converter for megawatt wind power generation |
| CN101714816A (en) * | 2008-09-30 | 2010-05-26 | 洛克威尔自动控制技术股份有限公司 | Power electronic module pre-charge system and method |
-
2015
- 2015-01-26 CN CN201510039365.XA patent/CN104660081B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1393049A (en) * | 2000-09-13 | 2003-01-22 | Abb研究有限公司 | Controlling and regulating method for three level power converter having active clamping switches, and device therefor |
| US6411067B1 (en) * | 2001-02-20 | 2002-06-25 | Abb Ab | Voltage source converters operating either as back-to-back stations or as parallel static var compensators |
| CN101013818A (en) * | 2007-02-07 | 2007-08-08 | 哈尔滨九洲电气股份有限公司 | Three-level medium voltage converter for megawatt wind power generation |
| CN101714816A (en) * | 2008-09-30 | 2010-05-26 | 洛克威尔自动控制技术股份有限公司 | Power electronic module pre-charge system and method |
Non-Patent Citations (3)
| Title |
|---|
| 双馈电机双三电平调速系统的研究;郑宏等;《科技广场》;20130730(第7期);第109页左栏第7行-第110页左栏倒数第5行，图2-6 * |
| 基于DSP和CPLD的三电平背靠背变流器研究;邵章平等;《电力电子技术》;20101031;第44卷(第10期);第25页第2.1节-第26页第3.1节，图1-4 * |
| 有源钳位逆变器最小开关损耗调制策略的研究;郝琦;《机车电传动》;20140710(第4期);全文 * |
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