CN106059352B - Reduce the three-stage SVPWM algorithms of H/NPC converter switches loss - Google Patents
Reduce the three-stage SVPWM algorithms of H/NPC converter switches loss Download PDFInfo
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- CN106059352B CN106059352B CN201610405446.1A CN201610405446A CN106059352B CN 106059352 B CN106059352 B CN 106059352B CN 201610405446 A CN201610405446 A CN 201610405446A CN 106059352 B CN106059352 B CN 106059352B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention belongs to technical field of inverter control, and in particular to a kind of three-stage SVPWM algorithms reducing the loss of H/NPC converter switches.It includes the following steps：S1 calculates three basic vector V according to more level SVPWM algorithms based on 60 ° of coordinate systems1、V2、V3Corresponding action time T1、T2、T3；S2, fundamental space voltage vector on off state are chosen, and according to the principle for reducing common-mode voltage, choose the on off state among fundamental space voltage vector, and sort successively according to the value S of on off state is ascending；S3 determines the off status that first opens of next switch periods on off sequence according to the last on off state of a upper switch periods on off sequence, and it is initial state to choose on off state switching minimum；S4 designs three-stage on off sequence according to minimum principle is switched on off sequence；S5, on off state mapping.
Description
Technical field
The invention belongs to technical field of inverter control, and in particular to a kind of to reduce the three of the loss of H/NPC converter switches
Segmentation SVPWM algorithms.
Background technology
Currently, being used based on high-power frequency conversion device in fields such as electric power, ship naval vessels, mine hoisting, steel rollings
Converter technique has become the major measure that high efficiency of energy utilizes.The high-power multi-level converter topology of common mesohigh can be divided into
Two classes：1) semibridge system clamper type (diode clamp bit-type and striding capacitance type), 2) full-bridge type cascade connection type, there are DC side electricity for the former
The problem of holding the balance of voltage, when level number is more than three, control will become more complicated.It includes 2H bridge grades to cascade code converter
Connection, H/NPC cascades and Mixed cascading.It is simple that 2H bridge cascade connection types are easy to extension, control method, but needs a large amount of independent direct current electricity
Source.H/NPC cascade connection types can overcome that clamp diode or clamp capacitor are more, control is difficult and need lacking more than independent current source number
Point is suitable for middle high-pressure high-power applications occasion.
Space voltage vector modulation strategy (Space Vector Pulse Width Modulation, abbreviation SVPWM) is controlled
System is flexible, voltage utilization is high, extensive research has been obtained in multi-level converter pulsewidth modulation, more level common at present
Space voltage vector modulation strategy has：Traditional Space voltage vector method, reference voltage vector decomposition method, 60 ° of coordinate system methods, line electricity
Press coordinate system, sorting algorithm and virtual voltage vector method etc..Space voltage vector modulation strategy (SVPWM) is set according on off sequence
The different of meter mode can be divided into three-stage SVPWM algorithms, five-part form SVPWM algorithms and seven segmentation SVPWM algorithms etc. again.In two electricity
In gentle three-level current transformer, since the quantity of Redundanter schalter state and space voltage vector is small, seven segmentation SVPWM algorithms are easy to
It realizes.But the Multilevel Inverters more than five level, on off sequence design is more complicated, and seven segmentation on off sequences need to meet
Stringent restrictive condition causes on off sequence design dumb.Simultaneously when switching frequency is relatively low, seven segmentation SVPWM algorithms
In adjacent small inter-sector handoff, extra switch loss greatly increases on off sequence, and harmonic wave of output voltage increases, the day of one's doom
Application of the seven segmentation SVPWM algorithms in the more level fields of high-power especially low switching frequency is made.
Invention content
For shortcoming existing for existing seven segmentations SVPWM algorithms, the present invention proposes a kind of reduction H/NPC converters
The three-stage SVPWM algorithms of switching loss, on the basis of general 60 ° of coordinate systems more level SVPWM algorithms, in conjunction with H/NPC five
Electrical level inverter topological structure provides a kind of novel flexible three-stage SVPWM algorithms.Three-stage SVPWM modulation systems without
It need to consider stringent switch constraint condition, harmonic wave of output voltage performance can be improved while reducing switching loss.
The present invention adopts the following technical scheme that：
The three-stage SVPWM algorithms of H/NPC converter switches loss are reduced, it includes the following steps：
S1 calculates three basic vector V according to more level SVPWM algorithms based on 60 ° of coordinate systems1、V2、V3Corresponding work
With time T1、T2、T3；
S2, fundamental space voltage vector on off state are chosen, and according to the principle for reducing common-mode voltage, choose fundamental space electricity
The on off state among vector is pressed, and is sorted successively according to the value S of on off state is ascending；
S3 determines next switch periods on off sequence according to the last on off state of a upper switch periods on off sequence
First open off status, it is initial state to choose on off state switching minimum；
S4 designs three-stage on off sequence according to minimum principle is switched on off sequence；
S5 determines that on off state maps.
Further, step S2 specifically includes following steps,
S21, to arbitrary on off state [Sa, Sb, Sc], define its on off state value S=Sa+Sb+Sc, in order to indicate to switch
The switching of state, defines the total changing value Δ S of threephase switch state respectively and each phase on off state variation maximum value δ S are respectively
S22, to reference voltage vector VrefAll on off states in residing small sector, according to the original for reducing common-mode voltage
Then, intermediate Redundanter schalter state is chosen, and calculates its on off state value S, according to the size of on off state value S, from small to large
All on off states are sorted successively and constitute set A.
Further, step S3 specifically includes following steps,
S31 selects the on off state of the total changing value Δ S minimums of threephase switch state from all on off states of selection
For set B, if set B states containing multiple switch, go to step S32, otherwise terminate；
S32, it is set C that the on off state of each phase on off state variation maximum value δ S minimums is selected from set B, if set
C states containing multiple switch then go to step S33, otherwise terminate；
S33, the selecting switch state value S minimum on off states from set C.
The present invention is for the purpose of reducing devices switch loss, it is proposed that a kind of novel three-stage SVPWM algorithms.This three sections
The more level SVPWM algorithms of general simplification of the formula SVPWM strategies based on 60 ° of coordinate systems not only avoid complicated sector and judge and three
Angle function calculates；And not stringent switch constraint condition, it can also improve output voltage while reducing switching frequency
Frequency spectrum, especially in low switching frequency and high modulation, advantage becomes apparent.
Description of the drawings
Fig. 1 is the flow chart for the three-stage SVPWM algorithms for reducing the loss of H/NPC converter switches；
Fig. 2 is the Ith big sector space voltage vector-diagram；
Fig. 3 is switching frequency fsWhen=500Hz, VabLine voltage oscillogram；
Fig. 4 is switching frequency fsWhen=500Hz, VabThe spectrum analysis figure of line voltage；
Fig. 5 is switching frequency fsWhen=500Hz, iaLoad current waveform figure；
Fig. 6 is switching frequency fsWhen=500Hz, iaLoad current spectrum analysis figure；
When Fig. 7 is three-stage M=0.9, fs/f0=10 switching tube pulse simulation result diagram；
Fig. 8 is M=0.9, fs/f0The experimental result picture of seven segmentation SVPWM algorithms when=10；
Fig. 9 is the output waveform figure of three-stage SVPWM under corresponding conditions.
Specific implementation mode
To further illustrate that each embodiment, the present invention are provided with attached drawing.These attached drawings are that the invention discloses one of content
Point, mainly to illustrate embodiment, and the associated description of specification can be coordinated to explain the operation principles of embodiment.Cooperation ginseng
These contents are examined, those of ordinary skill in the art will be understood that other possible embodiments and advantages of the present invention.In figure
Component be not necessarily to scale, and similar component symbol is conventionally used to indicate similar component.
In conjunction with the drawings and specific embodiments, the present invention is further described.
As shown in fig.1, for the three-stage SVPWM algorithms proposed by the present invention for reducing the loss of H/NPC converter switches
Flow chart, it includes the following steps：
S1 calculates three basic vector V according to more level SVPWM algorithms based on 60 ° of coordinate systems1、V2、V3Corresponding work
With time T1、T2、T3；
S2, fundamental space voltage vector on off state are chosen, and according to the principle for reducing common-mode voltage, choose fundamental space electricity
The on off state among vector is pressed, and is sorted successively according to the value S of on off state is ascending；
S3 determines next switch periods on off sequence according to the last on off state of a upper switch periods on off sequence
First open off status, it is initial state to choose on off state switching minimum；
S4 designs three-stage on off sequence according to minimum principle is switched on off sequence；
S5 determines that on off state maps.
Consideration may will produce additional switching between adjacent small sector.If opening in the 1st switch periods
Pass sequence is [Sa1, Sb1, Sa1]-[Sa2, Sb2, Sc2]-[Sa3, Sb3, Sc3], the on off sequence in the 2nd switch periods is [Sa1',
Sb1', Sa1′]-[Sa2', Sb2', Sc2′]-[Sa3', Sb3', Sc3'], as [Sa1', Sb1', Sa1'] and [Sa3, Sb3, Sc3] when differing
It just will produce additional switching.A kind of flexible three-stage SVPWM on off sequences design that the embodiment provides, can basis
Last on off state [the S of a upper switch periodsa3, Sb3, Sc3] neatly select next switch periods first open off status
[Sa1', Sb1', Sa1'] so that the switching number in two switch periods keeps minimum.
To arbitrary on off state [Sa, Sb, Sc], its on off state value S is defined,
S=Sa+Sb+Sc,
In order to indicate the switching of on off state, the total changing value Δ S of threephase switch state and each phase on off state are defined respectively
Changing maximum value δ S is
To reference voltage vector VrefAll on off states in residing small sector, according to the principle for reducing common-mode voltage, choosing
Intermediate Redundanter schalter state is taken, and calculate its on off state value S according to the size of on off state value S from small to large to own
On off state sort successively constitute set A, according to the last on off state [S of a upper switch periodsa3, Sb3, Sc3].Take with
Lower judgment criterion therefrom selects the off status that first opens of next switch periods, i.e. step S2 to specifically include following steps：
S31 selects the on off state of the total changing value Δ S minimums of threephase switch state from all on off states of selection
For set B, which can be effectively reduced additional switching, if set B states containing multiple switch, go to step
Otherwise S32 terminates；
S32, it is set C, the criterion that the on off state of each phase on off state variation maximum value δ S minimums is selected from set B
The saltus step that output-voltage levels can be limited avoids significantly level switching unreasonable in voltage waveform, if set C is containing more
A on off state then goes to step S33, otherwise terminates；
S33, the selecting switch state value S minimum on off states from set C, to complete to first open the selection of off status.
As shown in fig.2, being the Ith big sector space voltage vector-diagram, with reference voltage vector VrefPositioned at the Ith big sector
For 11st small sector, according to the value S of on off state it is ascending sort 1. [310] → 2. [320] → 3. set A is
[420]→④[421]→⑤[431].If first opening off status to be chosen to be 2., take 2. [320] → 3. [420] of positive sequence → 4.
[421] it is three-stage SVPWM on off sequences；If first opening off status to be chosen to be 4., take 4. [421] → 3. [420] of negative phase-sequence →
2. [320] being three-stage SVPWM on off sequences.In this way, on off state switching is only a level series in each switch periods,
Meet on off state constraints；Meanwhile only carrying out twice that switching, i.e. a phase on off state be not in switch periods
Become, switching loss is greatly reduced.
With reference voltage vector V in Fig. 2refFor in the 11st small sector of the Ith big sector, according to based on 60 ° of coordinate systems
Five-level SVPWM algorithm, obtain synthesized reference voltage vector VrefThree basic vector V1、V2、V3, choose fundamental space electricity
Press the Redundanter schalter state among vector, according to the ascending set A that sort successively to obtain of the value S of on off state, on off state
Value S is continuous integer, and number consecutively obtains 1. [310] → 2. [320] → 3. [420] → 4. [421] → 5. [431].Ith sector
On off state there are five containing in 11st small sector, shares 5 kinds of switching sequences.If first opening off status to be chosen to be 2., positive sequence is taken
2. [320] → 3. [420] → 4. [421] being the on off sequence of three-stage SVPWM；If first opening off status to be chosen to be 4., take negative
4. [421] → 3. [420] → 2. [320] of sequence are the on off sequence of three-stage SVPWM.
As seen from Figure 2, there are not Redundanter schalter state, each switch periods in the on off sequence of three-stage SVPWM
The switching of interior on off state only changes a level series, meets the constraints of on off state, meanwhile, a switch periods
Interior carries out switching twice, has a phase on off state constant, greatly reduces switching loss.
The embodiment is based on having built five level H/NPC inverter simulation models in MATLAB, takes DC power supply Vdc=
500V is loaded and is loaded for resistance sense, and power factor is φ=0.95 cos, fundamental frequency f0=50Hz.Give different switching frequencies
With line voltage, current waveform and its spectrum analysis under modulation degree.When Fig. 3 and Fig. 4 is three-stage M=0.9 respectively, fs/f0=
10, i.e. switching frequency fsWhen=500Hz, VabLine voltage waveform and its spectrum analysis figure；Fig. 5 and Fig. 6 is three-stage M=respectively
When 0.9, fs/f0=10, i.e. switching frequency fsWhen=500Hz, iaLoad current waveform and its spectrum analysis figure.Fig. 7 is three-stage
When M=0.9, fs/f0=10 switching tube pulse simulation result diagram.
The embodiment has also built the experimental verification that H/NPC five-electrical level inverters carry out SVPWM algorithms based on DSP+FPGA.
Experiment parameter is：DC power supply M=0.9 is loaded and is loaded for resistance sense, and power factor is φ=0.90 cos, fundamental frequency f0=
50Hz.Experimental verification has been carried out to the line voltage under different switching frequencies, current waveform.
Fig. 8 is M=0.9, fs/f0The experimental result picture of seven segmentation SVPWM algorithms, V when=10dc=75V, Fig. 9 are then phase
The output waveform figure of three-stage SVPWM under the conditions of answering.By Fig. 8 and Fig. 9 it is found that the switch of three-stage algorithm is cut under similarity condition
It is lower to change frequency, and equally maintains good output performance.
Although specifically showing and describing the present invention in conjunction with preferred embodiment, those skilled in the art should be bright
In vain, it is not departing from the spirit and scope of the present invention defined by the appended claims, it in the form and details can be right
The present invention makes a variety of changes, and is protection scope of the present invention.
Claims (3)
1. reducing the three-stage SVPWM algorithms of H/NPC converter switches loss, it is characterised in that：It includes the following steps：
S1 calculates three basic vector V according to more level SVPWM algorithms based on 60 ° of coordinate systems1、V2、V3When corresponding effect
Between T1、T2、T3；
S2, fundamental space voltage vector on off state are chosen, and according to the principle for reducing common-mode voltage, choose fundamental space voltage arrow
Intermediate on off state is measured, and is sorted successively according to the value S of on off state is ascending；
S3 determines the head of next switch periods on off sequence according to the last on off state of a upper switch periods on off sequence
On off state, it is initial state to choose the minimum value of on off state switching；
S4 designs three-stage on off sequence according to minimum principle is switched on off sequence；
S5 determines that on off state maps.
2. reducing the three-stage SVPWM algorithms of H/NPC converter switches loss as described in claim 1, it is characterised in that：Institute
It states step S2 and specifically includes following steps,
S21, to arbitrary on off state [Sa, Sb, Sc], define its on off state value S=Sa+Sb+Sc, in order to indicate on off state
Switching, define respectively the total changing value Δ S of threephase switch state and each phase on off state variation maximum value δ S be respectively
S22, to reference voltage vector VrefAll on off states in residing small sector, according to the principle for reducing common-mode voltage, choosing
Intermediate Redundanter schalter state is taken, and calculate its on off state value S according to the size of on off state value S from small to large to own
On off state sort constitute set A successively；
Wherein, on off state [Sa, Sb, Sc] refer to the on off state of three-phase, Si1' refer to that next switch periods first open pass
State, Si3It is the last on off state of a upper switch periods.
3. reducing the three-stage SVPWM algorithms of H/NPC converter switches loss as claimed in claim 2, it is characterised in that：Institute
It states step S3 and specifically includes following steps,
S31 selects the on off state of the total changing value Δ S minimums of threephase switch state for collection from all on off states of selection
B is closed, if set B states containing multiple switch, go to step S32, otherwise terminate；
S32, it is set C that the on off state of each phase on off state variation maximum value δ S minimums is selected from set B, if set C contains
Multiple switch state then goes to step S33, otherwise terminates；
S33, the selecting switch state value S minimum on off states from set C.
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| CN107394796A (en) * | 2017-08-09 | 2017-11-24 | 广东电网有限责任公司云浮供电局 | A kind of three level comprehensive compensation systems and its detection method based on three-stage SVPWM modulation |
| CN110545042B (en) * | 2018-05-29 | 2020-11-10 | 株洲中车时代电气股份有限公司 | PWM rectifier control method and device |
| CN109256972B (en) * | 2018-10-26 | 2020-07-24 | 西安理工大学 | SVPWM modulation method based on five-segment five-level converter |
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| CN103107761A (en) * | 2013-01-11 | 2013-05-15 | 哈尔滨工业大学 | Three-dimensional space vector pulse width modulation (SVPWM) method based on four-phrase five-wire topology |
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| KR101268585B1 (en) * | 2011-10-05 | 2013-06-04 | 주식회사 오토파워 | Compensation method of dwad-time for three-phase inverter of SVPWM |
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