CN104658941B - A kind of measuring method of chip-stack structural parameters - Google Patents

A kind of measuring method of chip-stack structural parameters Download PDF

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CN104658941B
CN104658941B CN201510089321.8A CN201510089321A CN104658941B CN 104658941 B CN104658941 B CN 104658941B CN 201510089321 A CN201510089321 A CN 201510089321A CN 104658941 B CN104658941 B CN 104658941B
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chip
semiconductor layer
insulating barrier
formula
curve
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CN104658941A (en
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郭宇锋
李曼
张长春
吉新村
夏晓娟
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Nanjing University of Posts and Telecommunications Nantong Institute Limited
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Nanjing Post and Telecommunication University
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Abstract

The invention provides a kind of method of testing of chip-stack structural parameters.It measures the high frequency capacitance-voltage curve and low frequency capacitive-voltage curve of chip-stack structure using electric capacity-voltage tester, measure the thickness of insulating layer and doping content of semiconductor of the structure respectively according to low frequency saturation value and high frequency saturation value, point and feature extreme point that the applied voltage according to low frequency capacitive-voltage curve is zero measure the insulating barrier fixed charge density of the structure.This invention is used to provide a simple and nondestructive characterizing method to assess the reliability of three-dimensionally integrated chips laminated construction.

Description

A kind of measuring method of chip-stack structural parameters
Technical field
The present invention relates to thickness of insulating layer, semiconductor in field of semiconductor device test, more particularly to chip-stack structure The method of testing of doping concentration and insulating barrier fixed charge density.
Background technology
Three-dimensionally integrated is to overcome " More Moore " applications, to improve packaging density and circuit operating rate and realize integrated The final solution of Multifunctional circuit challenge.Chip-stacked technology is to realize one of three-dimensionally integrated key technology, and is realized Chip-stacked basic skills is characteristics of Direct Wafer Bonded.In order to assess bonding quality, current people frequently with cross-sectional analysis Although directly perceived with bond strength detection method, the chip after detection goes to pot, and is a kind of destructive detection, its application by Limitation.Although infrared thermography is non-damaged data, but be only capable of detection bonding cavity, and can not be obtained more effective Information.Accordingly, it is capable to which the no one kind that finds neither destroys three-dimensional stacking structure, and can para-linkage interface carries out the non-broken of effective evaluation Bad property detection mode, it is significant.
Three-dimensionally integrated basic structure --- chip-stack structure is divided into five layers, as shown in figure 1, the first semiconductor layer 1, second Semiconductor layer 5, the first insulating barrier 2, the second insulating barrier 4, metal level 3.Wherein, the first semiconductor layer 1, second semiconductor layer 5 Doping type is identical, you can be p-type or N-type.
Currently, the non-damaged data mode commonly used in semiconductor technology is C-V characteristic methods, low frequency and High Frequency C-V curve It is widely used and the extraction isostructural physical parameter of MIS, MOS.Tang Yi, Chinese patent, 200710046681.5, utilize electric charge Pump method of testing extracts metal-oxide-semiconductor interfacial state.Duan little Jin, Chinese patent, ZL200710120481.X, it is integrated with photocarrier radiation E measurement technology and free-carrier Absorption e measurement technology, there is provided a kind of method for measuring doping content of semiconductor.
The invention provides a kind of method of nondestructive characterization chip-stack structure, i.e. low-and high-frequency C-V methods, based on the party Method can measure the thickness of insulating layer, doping content of semiconductor and insulating barrier fixed charge density of chip-stack structure.
The content of the invention
Goal of the invention：It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of chip-stack structural parameters Method of testing, can quickly measure the thickness of insulating layer, doping content of semiconductor and insulating barrier fixed charge density of the structure.
Technical scheme：The method of testing of the extraction chip-stack structural parameters of the present invention, it comprises the following steps：
Step 1：It is the High Frequency C-V curve and low frequency that C-V testers measure chip-stack structure with electric capacity-voltage tester C-V curve；
Step 2：Electric capacity saturation value is read from low frequency C-V curve, the insulating barrier of chip-stack structure first is measured using formula 1 (2), the thickness of insulating layer of the second insulating barrier (4)；
Wherein, tiFor thickness of insulating layer, εiIt is the dielectric constant of insulating barrier, CLF maxIt is low frequency capacitive saturation value；
Step 3：Semiaxis is born from High Frequency C-V curve and reads electric capacity saturation value, and chip-stack structure first is measured using formula 2 The doping content of semiconductor of semiconductor layer (1)；
Wherein, CHF minIt is high frequency capacitance saturation value, εsIt is the dielectric constant of semiconductor layer, k is Boltzmann constant, and T is Absolute temperature, q are electron charges, and θ is transoid modifying factor, and its value is 2.125, niIt is intrinsic carrier concentration, NAIt is semiconductor Layer doping concentration；
Step 4：Electric capacity saturation value is read from High Frequency C-V curve positive axis, chip-stack structure second is measured using formula 2 The doping content of semiconductor of semiconductor layer (5)；
Step 5：Capacitance when applied voltage is zero is read from high frequency or low frequency C-V curve, establishes formula 3 and formula 4；
Wherein, C0Capacitance when for applied voltage being zero, CiIt is capacitive dielectric layer, its value is：Ci≈ei/ti, Cs10With Cs20Respectively upper lower semiconductor layer differential capacitance, they are on Vs10、Vs20Function, Vs10With Vs20It is zero for applied voltage When, upper and lower semiconductor layer surface gesture；
Wherein, β=q/kT, np0And pp0It is the equilibrium electron concentration and hole concentration of P-type silicon respectively, LDIt is semiconductor layer Debye length, F (a, b) expression formula are：Qf1, Qf2For the first insulating barrier (2), the fixed charge density of the second insulating barrier (4), VfermiFor Fermi potential, Qs10With Qs20Respectively the first semiconductor layer (1), The charge density of two semiconductor layers (5), they are on Vs10、Vs20Function；
Step 6：Feature extreme point (V is read from high frequency or low frequency C-V curveg *, C*), establish formula 5 and formula 6；
WhereinAnd Qm0Tried to achieve by following formula：
Qm0=Ci(2Vfermi-Vs01-Vs02)；
Step 7：Simultaneous formula 3,4,5,6, measure the first insulating barrier (2) using Program, the second insulating barrier (4) are consolidated Determine charge density.
First semiconductor layer (1), the dopant material of the second semiconductor layer (5) are Si, Ge, GaAs or InP.
First insulating barrier (2), the material of the second insulating barrier (4) are SiO2, SiN or Si3N4Dielectric material.
The material of metal level (3) is Cu, TiN or Ti.
First semiconductor layer (1), the doping type of the second semiconductor layer (5) are identical, are p-type or N-type.
First semiconductor layer (1), the doping concentration of the second semiconductor layer (5) is identical or differs.
Fixed charge density in first insulating barrier (2), the second insulating barrier (4) is identical or differs.
Beneficial effect：
1) present invention is a kind of method of nondestructive characterization chip-stack structure, i.e. low-and high-frequency C-V methods.
2) present invention can measure more seed ginsengs of the structure using the low frequency and High Frequency C-V curve of chip-stack structure Number, you can the thickness of insulating layer and doping content of semiconductor of the structure are measured using low frequency saturation value and high frequency saturation value, is utilized Point and feature extreme point that low frequency C-V curve applied voltage is zero measure the insulating barrier fixed charge density of the structure.
3) present invention may apply to different types of C-V curve.When applied voltage is zero, according to semiconductor layer 1 and 5 Surface state, the low frequency and High Frequency C-V curve of chip-stack structure are divided into four types：I, II, III, IV, respectively as schemed Shown in 2~5.Its corresponding surface state is as shown in table 1.
The surface state of layer 1 and 5 and chip-stack structure C-V curve type relation tables during 1 zero bias of table
4) the auto-adaptive parameter measuring method independent of specific device model of the invention is for new device model When carrying out parameter measurement, for measured value with respect to actual value error below 4%, both uniformity are good, therefore the present invention can be with Effectively measure the structural parameters of the structure.The measuring method of the present invention reduces to be carried out early stage to chip-stack structural model formula The processing spent time is calculated, substantially reduces the cycle of model parameter measurement, it is simple and quick.
Brief description of the drawings
Fig. 1 is chip-stack structural representation；
Fig. 2 is chip-stack structure low frequency and High Frequency C-V curve type I provided by the invention；
Fig. 3 is chip-stack structure low frequency and High Frequency C-V curve type II provided by the invention；
Fig. 4 is chip-stack structure low frequency and High Frequency C-V curve type III provided by the invention；
Fig. 5 is chip-stack structure low frequency and High Frequency C-V curve type IV provided by the invention.
Wherein have：First semiconductor layer 1, the second semiconductor layer 5, the first insulating barrier 2, the second insulating barrier 4, metal level 3.
Embodiment
The present invention, but the scope not limiting the invention in any way are further illustrated below by embodiment.
In the present embodiment, the substrate silicon layer of sample is p-type doping, and its thickness is 725 μm, insulating barrier SiO2 thickness For 500nm, metal level uses TiN+Ti+TiN laminated construction, wherein, two layers of TiN thickness is 60nm, and Ti thickness is 80nm. TiN and Ti work function is respectively 4.7eV and 4.33eV.
Sample is positioned on test platform, chassis material is copper, and top pressure probe material is tungsten, by recording pressure Alternating voltage and alternating current between probe and chassis calculate the impedance of sample, and then obtain low-frequency electrical capacitance and high frequency Capacitance.Substrate ground during experiment, the DC offset voltage on pressure probe are scanned to 40V, scanning 0.1V per second from -40V.It is low The frequency of frequency small-signal is 20HZ, amplitude 20mV.The frequency of high frequency small-signal is 2MHz, amplitude 20mV.
In order that the change of Fig. 2~5, the device that the present invention selects is presented in the low frequency and High Frequency C-V curve of chip-stack structure Part size includes (thickness of insulating layer ti, doping content of semiconductor NA, insulating barrier fixed charge density Qf1、Qf2)0.3μm、3× 1014cm-3、-9×1011cm-3V-1、-1×1011cm-3V-1；0.5μm、5×1014cm-3、2×1011cm-3V-1、8×1011cm-3V-1；0.7μm、7×1014cm-3、4×1011cm-3V-1、10×1011cm-3V-1With 0.9 μm, 9 × 1014cm-3、7×1011cm-3V-1、 14×1011cm-3V-1Deng yardstick.
All devices are measured in different applied voltage VgUnder low frequency and high frequency C-V characteristic, according to above-mentioned technical side Case calculation formula calculates thickness of insulating layer, doping content of semiconductor and insulating barrier fixed charge density.Errors such as table 2 Shown in~4.
The thickness of insulating layer actual value of table 2 and its relative error with measured value
The doping content of semiconductor actual value of table 3 and its relative error with measured value
The fixed charge density actual value of table 4 and its relative error with measured value

Claims (7)

  1. A kind of 1. measuring method of chip-stack structural parameters, from top to bottom including the first semiconductor layer (1), the first insulating barrier (2), metal level (3), the second insulating barrier (4), the second semiconductor layer (5)；It is characterized in that：This method comprises the following steps：
    Step 1：It is the High Frequency C-V curve and low frequency C-V that C-V testers measure chip-stack structure with electric capacity-voltage tester Curve；
    Step 2：From low frequency C-V curve read electric capacity saturation value, using formula 1 measure the insulating barrier of chip-stack structure first (2), The thickness of insulating layer of second insulating barrier (4)；
    Wherein, tiFor thickness of insulating layer, εiIt is the dielectric constant of insulating barrier, CLFmaxIt is low frequency capacitive saturation value；
    Step 3：Semiaxis is born from High Frequency C-V curve and reads electric capacity saturation value, and measuring chip-stack structure the first half using formula 2 leads The doping content of semiconductor of body layer (1)；
    Wherein, CHFminIt is high frequency capacitance saturation value, εsIt is the dielectric constant of semiconductor layer, k is Boltzmann constant, and T is absolute Temperature, q are electron charges, and θ is transoid modifying factor, and its value is 2.125, niIt is intrinsic carrier concentration, NAIt is that semiconductor layer is mixed Miscellaneous concentration；
    Step 4：Electric capacity saturation value is read from High Frequency C-V curve positive axis, measuring chip-stack structure the second half using formula 2 leads The doping content of semiconductor of body layer (5)；
    Step 5：Capacitance when applied voltage is zero is read from high frequency or low frequency C-V curve, establishes formula 3 and formula 4；
    Wherein, C0Capacitance when for applied voltage being zero, Ci is capacitive dielectric layer, and its value is：Ci≈ei/ti, Cs10With Cs20Point Not Wei upper lower semiconductor layer differential capacitance, they are on Vs10、Vs20Function, Vs10With Vs20When for applied voltage being zero, on Lower semiconductor layer surface potential；
    Wherein, β=q/kT, np0And pp0It is the equilibrium electron concentration and hole concentration of P-type silicon respectively, LDIt is the debye of semiconductor layer Length, F (a, b) expression formula are：Qf1, Qf2For the first insulating barrier (2), The fixed charge density of two insulating barriers (4), VfermiFor Fermi potential, Qs10With Qs20Respectively the first semiconductor layer (1), the second half lead The charge density of body layer (5), they are on Vs10、Vs20Function；
    Step 6：Feature extreme point (V is read from high frequency or low frequency C-V curveg *, C*), establish formula 5 and formula 6；
    WhereinAnd Qm0Tried to achieve by following formula：
    Qm0=Ci(2Vfermi-Vs01-Vs02)；
    Step 7：Simultaneous formula 3,4,5,6, the fixed electricity of the first insulating barrier (2), the second insulating barrier (4) is measured using Program Lotus density.
  2. 2. chip-stack structural parameters method of testing as claimed in claim 1, it is characterised in that：First semiconductor layer (1), The dopant material of second semiconductor layer (5) is Si, Ge, GaAs or InP.
  3. 3. chip-stack structural parameters method of testing as claimed in claim 1, it is characterised in that：First insulating barrier (2), The material of two insulating barriers (4) is SiO2, SiN or Si3N4Dielectric material.
  4. 4. chip-stack structural parameters method of testing as claimed in claim 1, it is characterised in that：The material of metal level (3) It is Cu, TiN or Ti.
  5. 5. chip-stack structural parameters method of testing as claimed in claim 1, it is characterised in that：First semiconductor layer (1), The doping type of second semiconductor layer (5) is identical, is p-type or N-type.
  6. 6. chip-stack structural parameters method of testing as claimed in claim 1, it is characterised in that：First semiconductor layer (1), The doping concentration of second semiconductor layer (5) is identical or differs.
  7. 7. chip-stack structural parameters method of testing as claimed in claim 1, it is characterised in that：First insulating barrier (2), Fixed charge density in two insulating barriers (4) is identical or differs.
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CN110531243A (en) * 2019-10-16 2019-12-03 启发(天津)电子科技有限公司 A kind of semiconducter device testing method and system
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