CN104658941A - Method for measuring parameters of chip lamination structure - Google Patents

Abstract

The invention provides a method for testing parameters of a chip lamination structure. According to the method, a high-frequency capacitance-voltage curve and a low-frequency capacitance-voltage curve of the chip lamination structure are tested by the aid of a capacitance-voltage tester, the insulation layer thickness and the semiconductor doping concentration of the structure are measured respectively according to a low-frequency saturation value and a high-frequency saturation value, and the insulation layer fixed charge density of the structure is measured according to a point with zero externally-applied voltage in the low-frequency capacitance-voltage curve as well as a characteristic extreme value point. A simple and non-destructive characterization method is provided for evaluation of the reliability of the chip lamination structure in three-dimensional integration.

Description

A kind of method of measurement of chip-stack structural parameters

Technical field

The present invention relates to field of semiconductor device test, particularly relate to the method for testing of thickness of insulating layer in chip-stack structure, doping content of semiconductor and insulating barrier fixed charge density.

Background technology

Three-dimensional is integrated is the final solution overcoming " More Moore " application, raising packaging density and circuit working speed and realize the multi-functional challenge of integrated circuit.Chip-stacked technology realizes one of three-dimensional integrated key technology, and to realize chip-stacked basic skills be characteristics of Direct Wafer Bonded.In order to assess bonding quality, although the cross-sectional analysis that often adopts of current people and bond strength detection method directly perceived, namely the chip after detecting goes to pot, and be a kind of destructively to detect, its application is restricted.Although infrared thermography is non-damaged data, only can detects bonding cavity, and more efficiently information can not be obtained.Therefore, one can be found neither to destroy three-dimensional stacking structure, the non-damaged data mode of effective evaluation can be carried out in para-linkage interface again, significant.

It is three-dimensional that integrated basic structure---chip-stack structure is divided into five layers, as shown in Figure 1, and the first semiconductor layer 1, second semiconductor layer 5, first insulating barrier 2, second insulating barrier 4, metal level 3.Wherein, the doping type of the first semiconductor layer 1, second semiconductor layer 5 is identical, namely can be P type, also can be N-type.

Current, non-damaged data mode conventional in semiconductor technology is C-V characteristic method, and low frequency and High Frequency C-V curve are widely used and extract the isostructural physical parameter of MIS, MOS.Tang Yi, Chinese patent, 200710046681.5, utilize charge pump method of testing to extract metal-oxide-semiconductor interfacial state.Duan little Jin, Chinese patent, ZL200710120481.X, is integrated with photocarrier radiometric technique and free-carrier Absorption measuring technique, provides a kind of method measuring doping content of semiconductor.

The invention provides a kind of method of nondestructive characterization chip-stack structure, i.e. low-and high-frequency C-V method, the thickness of insulating layer of chip-stack structure, doping content of semiconductor and insulating barrier fixed charge density can be recorded based on the method.

Summary of the invention

Goal of the invention: the object of the invention is to overcome the deficiencies in the prior art, provides a kind of method of testing of chip-stack structural parameters, can the thickness of insulating layer of this structure of Quick Measurement, doping content of semiconductor and insulating barrier fixed charge density.

Technical scheme: the method for testing of extraction chip-stack structural parameters of the present invention, it comprises the following steps:

Step 1: the High Frequency C-V curve and the low frequency C-V curve that record chip-stack structure with electric capacity-voltage tester and C-V tester;

Step 2: read electric capacity saturation value from low frequency C-V curve, utilize formula 1 to record the thickness of insulating layer of chip-stack structure first insulating barrier (2), the second insulating barrier (4);

$t_i>>\frac{e_i}{{2C}_{\mathrm{LF}\max }}$ Formula 1

Wherein, t _ifor thickness of insulating layer, ε _ithe dielectric constant of insulating barrier, C _lFmaxit is low frequency capacitive saturation value;

Step 3: bear semiaxis from High Frequency C-V curve and read electric capacity saturation value, utilize formula 2 to record the doping content of semiconductor of chip-stack structure first semiconductor layer (1);

$C_{\mathrm{HF}\min }>>\frac{e_i}{{2t}_i+\frac{e_i}{e_s}\sqrt{\frac{{2\mathrm{qe}}_s\mathrm{kT}}{q^2{N}_A}\ln \left(\frac{N_A}{n_i}\right)}}$ Formula 2

Wherein, C _hFminhigh frequency capacitance saturation value, ε _sbe the dielectric constant of semiconductor layer, k is Boltzmann constant, and T is absolute temperature, and q is electron charge.θ is transoid modifying factor, and its value is 2.125, n _iintrinsic carrier concentration, N _asemiconductor layer doped concentration;

Step 4: read electric capacity saturation value from High Frequency C-V curve positive axis, utilize formula 2 to record the doping content of semiconductor of chip-stack structure second semiconductor layer (5);

Step 5: capacitance when being zero from high frequency or low frequency C-V curve reading applied voltage, sets up formula 3 and formula 4;

$\frac{1}{C_0}=\frac{2}{C_i}+\frac{1}{C_{s10}}+\frac{1}{C_{s20}}$ Formula 3

$(V_{s10}+V_{s20})-{2V}_{\mathrm{fermi}}=\frac{Q_{s10}+Q_{s20}}{C_i}+\frac{Q_{f1}+Q_{f2}}{C_i}$ Formula 4

Wherein, C ₀for capacitance when applied voltage is zero, C _ibe capacitive dielectric layer, its value is: C _i>>e _i/ t _i.C _s10with C _s20be respectively lower semiconductor layer differential capacitance, they are about V _s10, V _s20function, V _s10with V _s20for applied voltage be zero time, upper and lower semiconductor layer surface gesture;

$C_{s10}=\frac{{\mathrm{\ϵ}}_s}{L_D}\frac{-\exp \left({-\mathrm{\βV}}_{s10}\right)+1+\frac{n_{p0}}{p_{p0}}(\exp \left({\mathrm{\βV}}_{s10}\right)-1)}{F({\mathrm{\βV}}_{s10},n_{p0}/p_{p0})}$

$C_{s20}=\frac{{\mathrm{\ϵ}}_s}{L_D}\frac{-\exp (-{\mathrm{\βV}}_{s20})+1+\frac{n_{p0}}{p_{p0}}(\exp \left({\mathrm{\βV}}_{s20}\right)-1)}{F({\mathrm{\βV}}_{s20},n_{p0}/p_{p0})}$

Wherein, n _p0and p _p0equilibrium electron concentration and the hole concentration of P-type silicon respectively, L _dbe the Debye length of semiconductor layer, the expression formula of F (a, b) is: q _f1, Q _f2be the fixed charge density of the first insulating barrier (2), the second insulating barrier (4), V _fermifor Fermi potential.Q _s10with Q _s20be respectively the charge density of the first semiconductor layer (1), the second semiconductor layer (5), they are about V _s10, V _s20function;

$Q_{s10}=-\mathrm{sign}\left(V_{s10}\right)\frac{{2\mathrm{\ϵ}}_s}{{\mathrm{\βL}}_D}F({\mathrm{\βV}}_{s10},n_{p0}/p_{p0})/q$

$Q_{s20}=-\mathrm{sign}\left(V_{s20}\right)\frac{{2\mathrm{\ϵ}}_s}{{\mathrm{\βL}}_D}F({\mathrm{\βV}}_{s20},n_{p0}/p_{p0})/q$

Step 6: read feature extreme point (V from high frequency or low frequency C-V curve _g ^*, C ^*), set up formula 5 and formula 6;

$Q_{f1}+Q_{f2}=-\frac{{4\mathrm{\ϵ}}_s}{{\mathrm{\βL}}_D}F({\mathrm{\βV}}_s^{*},n_{p0}/p_{p0})-Q_{m0}$ Formula 5

$Q_{f1}-Q_{f2}=V_g^{*}{C}_i$ Formula 6

Wherein and Q _m0tried to achieve by following formula:

$\frac{{\mathrm{\ϵ}}_s}{L_D}\frac{-\exp (-{\mathrm{\βV}}_s^{*})+1+\frac{n_{p0}}{p_{p0}}(\exp \left({\mathrm{\βV}}_s^{*}\right)-1)}{F({\mathrm{\βV}}_s^{*},n_{p0}/p_{p0})}=\frac{{2C}^{*}{C}_i}{C_i-{2C}^{*}}$

Q _m0＝C _i(2V _fermi-V _s01-V _s02)；

Step 7: simultaneous formula 3,4,5,6, utilizes Program to record the fixed charge density of the first insulating barrier (2), the second insulating barrier (4).

The dopant material of the first semiconductor layer (1), the second semiconductor layer (5) is Si, Ge, GaAs or InP.

The material of the first insulating barrier (2), the second insulating barrier (4) is SiO ₂, SiN or Si ₃n ₄dielectric material.

The material of metal level (3) is Cu, TiN or Ti.

The doping type of the first semiconductor layer (1), the second semiconductor layer (5) is identical, is namely P type or N-type.

The doping content of the first semiconductor layer (1), the second semiconductor layer (5) is identical or not identical.

Fixed charge density in first insulating barrier (2), the second insulating barrier (4) is identical or not identical.

Beneficial effect:

1) the present invention is a kind of method of nondestructive characterization chip-stack structure, i.e. low-and high-frequency C-V method.

2) the present invention can utilize the low frequency of chip-stack structure and High Frequency C-V curve to measure the many kinds of parameters of this structure, low frequency saturation value and high frequency saturation value can be utilized to measure thickness of insulating layer and the doping content of semiconductor of this structure, utilize low frequency C-V extra curvature making alive be zero point and feature extreme point measure the insulating barrier fixed charge density of this structure.

3) the present invention goes for dissimilar C-V curve.When applied voltage is zero, according to the surface state of semiconductor layer 1 and 5, low frequency and the High Frequency C-V curve of chip-stack structure are divided into Four types: I, II, III, IV, respectively as shown in Figure 2-5.The surface state of its correspondence is as shown in table 1.

Table 1 zero partially time the surface state of layer 1 and 5 and chip-stack structure C-V curve type relation table

4) the auto-adaptive parameter method of measurement not relying on concrete device model of the present invention is when carrying out parameter measurement for new device model, the relative actual value error of measured value is all below 4%, both consistency are good, and therefore the present invention effectively can measure the structural parameters of this structure.Method of measurement of the present invention decreases carries out the time spent by computing to chip-stack structural model formula in earlier stage, substantially reduces the cycle that this model parameter is measured, simple and quick.

Accompanying drawing explanation

Fig. 1 is chip-stack structural representation;

Fig. 2 is chip-stack structure low frequency provided by the invention and High Frequency C-V curve type I;

Fig. 3 is chip-stack structure low frequency provided by the invention and High Frequency C-V curve type II;

Fig. 4 is chip-stack structure low frequency provided by the invention and High Frequency C-V curve type III;

Fig. 5 is chip-stack structure low frequency provided by the invention and High Frequency C-V curve type IV.

Wherein have: the first semiconductor layer 1, second semiconductor layer 5, first insulating barrier 2, second insulating barrier 4, metal level 3.

Embodiment

Further illustrate the present invention below by embodiment, but and limit the scope of the invention never in any form.

In the present embodiment, the substrate silicon layer of sample is the doping of P type, and its thickness is 725 μm, insulating barrier SiO ₂thickness be 500nm, metal level adopts TiN+Ti+TiN laminated construction, and wherein, the thickness of two-layer TiN is the thickness of 60nm, Ti is 80nm.The work function of TiN and Ti is respectively 4.7eV and 4.33eV.

Be positioned over by sample on test platform, chassis material is copper, and top pressure probe material is tungsten, is calculated the impedance of sample, and then obtain low frequency capacitive value and high-frequency electrical capacitance by the alternating voltage between record pressure probe and chassis and alternating current.Substrate ground during experiment, the DC offset voltage on pressure probe scans 40V from-40V, scanning 0.1V per second.The frequency of low frequency small-signal is 20HZ, and amplitude is 20mV.The frequency of high frequency small-signal is 2MHz, and amplitude is 20mV.

In order to the change making the low frequency of chip-stack structure and High Frequency C-V curve present Fig. 2 ~ 5, the device size that the present invention selects comprises (thickness of insulating layer t _i, doping content of semiconductor N _a, insulating barrier fixed charge density Q _f1, Q _f2) 0.3 μm, 3 × 10 ¹⁴cm ^-3,-9 × 10 ¹¹cm ^-3v ^-1,-1 × 10 ¹¹cm ^-3v ^-1; 0.5 μm, 5 × 10 ¹⁴cm ^-3, 2 × 10 ¹¹cm ^-3v ^-1, 8 × 10 ¹¹cm ^-3v ^-1; 0.7 μm, 7 × 10 ¹⁴cm ^-3, 4 × 10 ¹¹cm ^-3v ^-1, 10 × 10 ¹¹cm ^-3v ^-1with 0.9 μm, 9 × 10 ¹⁴cm ^-3, 7 × 10 ¹¹cm ^-3v ^-1, 14 × 10 ¹¹cm ^-3v ^-1deng yardstick.

Measure all devices at different applied voltage V _gunder low frequency and high frequency C-V characteristic, calculate thickness of insulating layer, doping content of semiconductor and insulating barrier fixed charge density according to technique scheme computing formula.Errors is as shown in table 2 ~ 4.

Table 2 thickness of insulating layer actual value and the relative error with measured value thereof

Table 3 doping content of semiconductor actual value and the relative error with measured value thereof

Table 4 fixed charge density actual value and the relative error with measured value thereof

Claims (7)

1. a method of measurement for chip-stack structural parameters, is characterized in that: the method comprises the following steps:

Step 1: the High Frequency C-V curve and the low frequency C-V curve that record chip-stack structure with electric capacity-voltage tester and C-V tester;

Step 2: read electric capacity saturation value from low frequency C-V curve, utilize formula 1 to record the thickness of insulating layer of chip-stack structure first insulating barrier (2), the second insulating barrier (4);

$t_i>>\frac{e_i}{2C_{\mathrm{LF}\max }}$ Formula 1

Wherein, t _ifor thickness of insulating layer, ε _ithe dielectric constant of insulating barrier, C _lFmaxit is low frequency capacitive saturation value;

Step 3: bear semiaxis from High Frequency C-V curve and read electric capacity saturation value, utilize formula 2 to record the doping content of semiconductor of chip-stack structure first semiconductor layer (1);

$C_{\mathrm{HF}\min }>>\frac{e_i}{2t_i+\frac{e_i}{e_s}\sqrt{\frac{2{\mathrm{qe}}_s\mathrm{kT}}{q^2{N}_A}\ln \left(\frac{N_A}{n_i}\right)}}$ Formula 2

Wherein, C _hFminhigh frequency capacitance saturation value, ε _sbe the dielectric constant of semiconductor layer, k is Boltzmann constant, and T is absolute temperature, and q is electron charge.θ is transoid modifying factor, and its value is 2.125, n _iintrinsic carrier concentration, N _asemiconductor layer doped concentration;

Step 4: read electric capacity saturation value from High Frequency C-V curve positive axis, utilize formula 2 to record the doping content of semiconductor of chip-stack structure second semiconductor layer (5);

Step 5: capacitance when being zero from high frequency or low frequency C-V curve reading applied voltage, sets up formula 3 and formula 4;

$\frac{1}{C_0}=\frac{2}{C_i}+\frac{1}{C_{s10}}+\frac{1}{C_{s20}}$ Formula 3

$(V_{s10}+V_{s20})-2V_{\mathrm{fermi}}=\frac{Q_{s10}+Q_{s20}}{C_i}+\frac{Q_{f1}+Q_{f2}}{C_i}$ Formula 4

Wherein, C ₀for capacitance when applied voltage is zero, C _ibe capacitive dielectric layer, its value is: C _i> > e _i/ t _i.C _s10with C _s20be respectively lower semiconductor layer differential capacitance, they are about V _s10, V _s20function, V _s10with V _s20for applied voltage be zero time, upper and lower semiconductor layer surface gesture;

$C_{s10}=\frac{{\mathrm{\ϵ}}_s}{L_D}\frac{-\exp (-{\mathrm{\βV}}_{s10})+1+\frac{n_{p0}}{p_{p0}}(\exp \left({\mathrm{\βV}}_{s10}\right)-1)}{F({\mathrm{\βV}}_{s10},n_{p0}/p_{p0})}$

$C_{s20}=\frac{{\mathrm{\ϵ}}_s}{L_D}\frac{-\exp (-{\mathrm{\βV}}_{s20})+1+\frac{n_{p0}}{p_{p0}}(\exp \left({\mathrm{\βV}}_{s20}\right)-1)}{F({\mathrm{\βV}}_{s20},n_{p0}/p_{p0})}$

Wherein, n _p0and p _p0equilibrium electron concentration and the hole concentration of P-type silicon respectively, L _dbe the Debye length of semiconductor layer, the expression formula of F (a, b) is: q _f1, Q _f2be the fixed charge density of the first insulating barrier (2), the second insulating barrier (4), V _fermifor Fermi potential.Q _s10with Q _s20be respectively the charge density of the first semiconductor layer (1), the second semiconductor layer (5), they are about V _s10, V _s20function;

$Q_{s10}=-\mathrm{sign}\left(V_{s10}\right)\frac{2{\mathrm{\ϵ}}_s}{\mathrm{\β}{L}_D}F({\mathrm{\βV}}_{s10},n_{p0}/p_{p0})/q$

$Q_{s20}=-\mathrm{sign}\left(V_{s20}\right)\frac{2{\mathrm{\ϵ}}_s}{\mathrm{\β}{L}_D}F({\mathrm{\βV}}_{s20},n_{p0}/p_{p0})/q$

Step 6: read feature extreme point (V from high frequency or low frequency C-V curve _g ^*, C ^*), set up formula 5 and formula 6;

$Q_{f1}+Q_{f2}=\frac{4{\mathrm{\ϵ}}_s}{{\mathrm{\βL}}_D}F({\mathrm{\βV}}_s^{*},n_{p0}/p_{p0})-Q_{m0}$ Formula 5

$Q_{f1}-Q_{f2}=V_g^{*}{C}_i$ Formula 6

Wherein and Q _m0tried to achieve by following formula:

$\frac{{\mathrm{\ϵ}}_s}{L_D}\frac{-\exp (-{\mathrm{\βV}}_s^{*})+1+\frac{n_{p0}}{p_{p0}}(\exp \left({\mathrm{\βV}}_s^{*}\right)-1)}{F({\mathrm{\βV}}_s^{*},n_{p0}/p_{p0})}=\frac{2C^{*}{C}_i}{C_i-2C^{*}}$

Q _m0＝C _i(2V _fermi-V _s01-V _s02)；

Step 7: simultaneous formula 3,4,5,6, utilizes Program to record the fixed charge density of the first insulating barrier (2), the second insulating barrier (4).

2. chip-stack structural parameters method of testing as claimed in claim 1, is characterized in that: the dopant material of the first semiconductor layer (1), the second semiconductor layer (5) is Si, Ge, GaAs or InP.

3. chip-stack structural parameters method of testing as claimed in claim 1, is characterized in that: the material of the first insulating barrier (2), the second insulating barrier (4) is SiO ₂, SiN or Si ₃n ₄dielectric material.

4. chip-stack structural parameters method of testing as claimed in claim 1, is characterized in that: the material of metal level (3) is Cu, TiN or Ti.

5. chip-stack structural parameters method of testing as claimed in claim 1, is characterized in that: the doping type of the first semiconductor layer (1), the second semiconductor layer (5) is identical, is namely P type or N-type.

6. chip-stack structural parameters method of testing as claimed in claim 1, is characterized in that: the doping content of the first semiconductor layer (1), the second semiconductor layer (5) is identical or not identical.

7. chip-stack structural parameters method of testing as claimed in claim 1, is characterized in that: the fixed charge density in the first insulating barrier (2), the second insulating barrier (4) is identical or not identical.