CN104458035B - Detect structure and detection method - Google Patents
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- CN104458035B CN104458035B CN201310439124.5A CN201310439124A CN104458035B CN 104458035 B CN104458035 B CN 104458035B CN 201310439124 A CN201310439124 A CN 201310439124A CN 104458035 B CN104458035 B CN 104458035B
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Abstract
One kind detection structure and detection method, the detection structure include：Semiconductor substrate, positioned at the unit to be detected of semiconductor substrate surface, the test MOS transistor being disposed adjacent with the unit to be detected, by measuring the charge pump current of the test MOS transistor, obtains the temperature of the unit to be detected.Because the test MOS transistor is disposed adjacent with unit to be detected, it is only necessary to which the temperature of unit to be detected can be obtained by detecting the temperature of the test MOS transistor；And because the maximum and temperature of the charge pump current for testing MOS transistor are proportional, the maximum of the charge pump current by measuring the test MOS transistor can obtain the temperature of the unit to be detected in real time.
Description
Technical field
The present invention relates to semiconductor test technology, more particularly to a kind of detection structure and detection method.
Background technology
The high resistant conductive material such as polysilicon, tantalum nitride is widely used in current integrated circuit, the high resistant
Conductive material is typically used in form the high resistant semiconductor devices such as resistance.With continuing to develop for semiconductor technology, semiconductor device
The size of part is constantly reducing, therefore the size of the high resistant semiconductor devices such as resistance is also constantly being reduced, simultaneously because institute
It is usually bar shaped or linear structure to state resistance, and the width of resistance is less and less, easily causes electromigration effect so that resistance is contour
The electrical parameter of resistance semiconductor devices changes, in some instances it may even be possible to cause the high resistant semiconductor device failure such as resistance.Simultaneously as
The resistance of high-resistance semi-conductor device is larger, and temperature during work is higher, and electromigration effect is influenced by temperature very greatly, therefore,
High-resistance semi-conductor device is easier to be influenceed by electromigration effect.
Therefore, being highly desirable to detect influence of the high temperature to the electric property of high-resistance semi-conductor device.In the prior art,
Typically substrate to be tested is clamped on wafer-supporting platform and is heated to after specific temperature, to the high-resistance semi-conductor on substrate to be tested
Device carries out the test of electric property, so that when judging specified temp, shadow of the high-resistance semi-conductor device by electromigration effect
The degree of sound.But because high-resistance semi-conductor device can also produce heat in test so that high-resistance semi-conductor device correspondence position
Temperature is more than the heating-up temperature that wafer-supporting platform is set, if being directly used as height during test by the use of the heating-up temperature that the wafer-supporting platform is set
The temperature of semiconductor devices is hindered, test result can be caused inaccurate.And because the surface of the high-resistance semi-conductor device is toward contact
It is formed with interlayer dielectric layer, therefore also is difficult to directly carry out testing high-resistance semi-conductor device real-time using the mode of infrared measurement of temperature
Temperature.
The content of the invention
The problem of present invention is solved is to provide a kind of detection structure and detection method, can easily and accurately detect to be tested
The temperature of unit.
To solve the above problems, the invention provides a kind of detection method, including：Detection structure, the detection knot are provided
Structure includes：Semiconductor substrate, positioned at the unit to be detected of semiconductor substrate surface, the survey being disposed adjacent with the unit to be detected
Try MOS transistor；The detection structure is placed on the wafer-supporting platform surface with heating function, the unit to be detected not work
Make, the temperature of geodesic structure to be checked adjusted using wafer-supporting platform, thus obtain the maximum of the charge pump current of test MOS transistor with
Corresponding relation between temperature；Test voltage is applied to the unit to be detected, the charge pump current of test MOS transistor is measured
Maximum so that according to test MOS transistor charge pump current maximum and temperature between corresponding relation worked as
The temperature of preceding unit to be detected.
Optionally, measuring the method for the maximum of the charge pump current of the test MOS transistor includes：The test
The source region of MOS transistor and drain region are electrically connected to be connected with one end of dc source afterwards, and the other end of the dc source
It is connected by an ammeter with Semiconductor substrate, voltage pulse signal is applied in the gate electrode of the test MOS transistor,
The voltage pulse signal is across the threshold voltage and flat-band voltage of test MOS transistor, and the voltage pulse signal is upper
The time of liter, fall time are respectively less than the time constant of boundary defect transmitting, and charge pump current is measured using the ammeter；And it is logical
The bias crossed between adjustment Semiconductor substrate and source region, drain region, obtains the maximum of charge pump current.
Optionally, the high level of each pulse of the voltage pulse signal is equal and more than test MOS transistor
Threshold voltage, the low level of each pulse of the voltage pulse signal is equal and electric less than the flat rubber belting of test MOS transistor
Pressure.
Optionally, the charge pump electricity of the corresponding test MOS transistor of test voltage measurement is applied to the unit to be detected
During the maximum of stream, the heating function of the wafer-supporting platform is closed.
Optionally, the electric property for treating detection unit application test voltage using the end method of testing of Kelvin four is surveyed
Examination.
Optionally, the electromigration characteristic for treating detection unit application test voltage using the end method of testing of Kelvin four is surveyed
Examination.
Structure is detected present invention also offers one kind, including：Semiconductor substrate, positioned at the to be detected of semiconductor substrate surface
Unit, the test MOS transistor being disposed adjacent with the unit to be detected, by the electric charge for measuring the test MOS transistor
Pump electric current, obtains the temperature of the unit to be detected.
Optionally, the unit to be detected is resistance or MOS transistor.
Optionally, when the unit to be detected is resistance, the two ends of the resistance have respectively utilizes the end of Kelvin four
Two test leads that method of testing is tested.
Optionally, when the unit to be detected is resistance, the material of the unit to be detected is polysilicon, tantalum nitride or
Titanium nitride.
Optionally, the test MOS transistor is located at the both sides of unit to be detected or set around unit to be detected.
Optionally, when the quantity of the test MOS transistor is two, described two test MOS transistors distinguish position
Gate electrode in the both sides of unit to be detected, and described two test MOS transistors is electrically connected, and described two test MOS are brilliant
The source region of body pipe is electrically connected, and the drain region of described two test MOS transistors is electrically connected.
Optionally, the test MOS transistor is the MOS transistor in input/output device area.
Compared with prior art, technical scheme has advantages below：
Because the test MOS transistor is disposed adjacent with unit to be detected, the temperature of the test MOS transistor is with treating
The temperature of detection unit is identical, it is only necessary to which the temperature of unit to be detected can be obtained by detecting the temperature of the test MOS transistor
Degree；And the boundary defect quantity between the gate dielectric layer and Semiconductor substrate due to testing MOS transistor and test MOS transistor
Charge pump current maximum it is proportional, and the boundary defect quantity and temperature are also proportional, therefore the test MOS is brilliant
The maximum of the charge pump current of body pipe and temperature are proportional, by measuring the charge pump current for testing MOS transistor
Maximum, the temperature of test MOS transistor can be obtained in real time, the temperature of the unit to be detected can be obtained in real time,
So as to measure the electric property of unit to be detected under specified temp exactly.
Brief description of the drawings
Fig. 1 is the overlooking the structure diagram of the detection structure of the embodiment of the present invention；
Cross-sectional views of the Fig. 2 for the detection structure in Fig. 1 along AA ' directions；
Fig. 3 is the measurement structural representation using charge pumping technique measure interface defects count；
Fig. 4 is the pulse signal schematic diagram for the voltage pulse signal that the embodiment of the present invention applies on gate electrode：
When Fig. 5 differs for the bias between Semiconductor substrate and source region, drain region, the electric current point of corresponding charge pump current
Cloth schematic diagram.
Embodiment
Because prior art does not have a kind of energy accurate and easily treat the detection knot that the temperature of test cell is detected
Structure, therefore, the embodiments of the invention provide one kind detection structure and detection method, the detection structure includes：Unit to be detected,
The test MOS transistor being disposed adjacent with the unit to be detected, by the charge pump electricity for measuring the test MOS transistor
Stream, obtains the temperature of unit to be detected.Because the test MOS transistor is disposed adjacent with unit to be detected, the test MOS
The temperature of transistor is identical with the temperature of unit to be detected, it is only necessary to which detecting the temperature of the test MOS transistor can obtain
Obtain the temperature of unit to be detected；And the boundary defect number between the gate dielectric layer and Semiconductor substrate due to testing MOS transistor
The maximum of charge pump current of the amount with testing MOS transistor is proportional, and the boundary defect quantity and temperature are also proportional,
Therefore the maximum and temperature of the charge pump current of the test MOS transistor are proportional, by measuring the test MOS crystal
The maximum of the charge pump current of pipe, the temperature of the test MOS transistor can be obtained in real time, institute can be obtained in real time
State the temperature of unit to be detected.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 and Fig. 2 are refer to, Fig. 1 is the overlooking the structure diagram of the detection structure of the embodiment of the present invention, and Fig. 2 is in Fig. 1
Cross-sectional view of the detection structure along AA ' directions, including：Semiconductor substrate 100, positioned at the Semiconductor substrate 100
Interior fleet plough groove isolation structure 101 and the resistance 110 positioned at the surface of fleet plough groove isolation structure 101；Positioned at the resistance 110
Test MOS transistor in the active area of both sides, the test MOS transistor includes the grid positioned at the surface of Semiconductor substrate 100
Pole structure 121, the source region 122 in the Semiconductor substrate 100 of the both sides of grid structure 121 and drain region 123, the grid structure
121 include the gate dielectric layer 124 and the gate electrode 125 positioned at the surface of gate dielectric layer 124 positioned at the surface of Semiconductor substrate 100；Position
Inserted in first conductive plunger 131 on the surface of grid structure 121 and positioned at the surface of the first conductive plunger 131 and with the first conduction
The first metal interconnecting layers 141 that are electrically connected of plug 131, positioned at second conductive plunger 132 on the surface of source region 122 and positioned at the
The surface of two conductive plunger 132 and the second metal interconnecting layer 142 being electrically connected with the second conductive plunger 132, positioned at the drain region
3rd conductive plunger 133 on 123 surfaces and positioned at the surface of the 3rd conductive plunger 133 and with the electricity of the 3rd conductive plunger 133
3rd metal interconnecting layer 143 of connection；Corresponding first metal interconnecting layer 141 of difference test MOS transistor is electrically connected so that
The grid structure 121 of two MOS transistors is electrically connected；The corresponding electricity of second metal interconnecting layer 142 of difference test MOS transistor
Learn connection so that the source region 122 of two MOS transistors is electrically connected；The corresponding 3rd metal interconnection of difference test MOS transistor
Layer 143 is electrically connected so that the drain region 123 of two MOS transistors is electrically connected.
In the present embodiment, the resistance 110 is unit to be tested, and the material of the resistance 110 is polysilicon, tantalum nitride
Or the high resistant conductive material such as titanium nitride, the resistance of the resistance 110 formed by high resistant conductive material is larger, therefore during work
Temperature is very high, it is easier to cause electromigration, with greater need for that can measure temperature when resistance 110 works exactly, so as to exactly
Assess influence degree of the temperature to the electromigration of resistance 110.
In other embodiments, structure to be tested can also be metal interconnecting wires, inductance, the MOS positioned at core device region
Transistor etc., it is accurate and easily detect the real time temperature of structure to be tested using the detection structure of the embodiment of the present invention, from
And can judge to assess the influence degree that temperature treats test structure electromigration exactly.Wherein due to positioned at core device region
The grid structure of MOS transistor is smaller, and gate dielectric layer is relatively thin, easily breakdown when charge pump is tested, therefore can only be using this
The corresponding temperature of detection structure detection of inventive embodiments.
In the present embodiment, the resistance 110 be located at fleet plough groove isolation structure 101 surface, using the shallow trench every
From structure 101 by resistance 110 and Semiconductor substrate 100 and other semiconductor devices electric isolations.And the shallow trench isolation junction
MOS transistor in the active area of the both sides of structure 101 is used for the real time temperature of test resistance 110.In other embodiments, it is described to treat
Test structure can also be located immediately at the semiconductor substrate surface.
In the present embodiment, the two ends of the resistance 110 have two test leads respectively, and the end of later use Kelvin four is surveyed
Examination method is tested the electric property of resistance 110, and test voltage is applied to one of test lead at the two ends of resistance 110
In, the electric current of resistance 110 is passed through by another test lead test at the two ends of resistance 110, because voltage and current is separately tested,
Influence of the additional resistance to test result when avoiding applying voltage, is conducive to improving the accuracy of test result.In other realities
Apply in example, the two ends of the resistance can also all only have a test lead.
In the present embodiment, there are two test MOS transistors in the both sides of resistance 110, because the test MOS is brilliant
Body pipe is disposed adjacent with resistance 110, and the temperature of the test MOS transistor is equal to the temperature of resistance 110, therefore by measuring
The temperature of the resistance 110 can be measured by stating the temperature of test MOS transistor.
In other embodiments, a test MOS transistor also can be only formed in the side of structure to be tested, for testing
The real time temperature of the structure to be tested.Or several are formed around the structure to be tested around structure setting to be tested
Test MOS transistor, the real time temperature for testing the structure to be tested.
In the present embodiment, grid structure, source region and the drain region of two test MOS transistors of the both sides of resistance 110
All link together so that the charge pump current of two test MOS transistors can be tested simultaneously.In other embodiment
In, grid structure, source region and the drain region of described two test MOS transistors can be independently arranged, and can be measured respectively described
The charge pump current of MOS transistor is tested, so as to obtain the temperature of test MOS transistor respectively.
In the present embodiment, for the different test grid structures of MOS transistors, source region are connected with drain region first
Metal interconnecting layer 141, the second metal interconnecting layer 142 and the 3rd metal interconnecting layer 143 are located in same layer metal level.In other realities
Apply in example, first metal interconnecting layer, the second metal interconnecting layer and the 3rd metal interconnecting layer can also be located at different metals
Layer.
In the present embodiment, the test MOS transistor is the MOS transistor in input/output device area, the test
The thickness of the gate dielectric layer of MOS transistor is thicker, can avoid gate dielectric layer in the charge pump current of measurement test MOS transistor
When it is breakdown.
Using above-mentioned detection structure, the embodiment of the present invention additionally provides a kind of detection method, specifically included：
The detection structure is provided；
The detection structure is placed on the wafer-supporting platform surface with heating function, the unit to be detected does not work, profit
The temperature of geodesic structure to be checked is adjusted with wafer-supporting platform, so as to obtain the maximum and temperature of the charge pump current of test MOS transistor
Between corresponding relation；
Test voltage is applied to the unit to be detected, the maximum of the charge pump current of test MOS transistor is measured, from
And current unit to be detected is obtained according to the corresponding relation between the maximum and temperature of the charge pump current of test MOS transistor
Temperature.
Fig. 2 is refer to, because the gate dielectric layer 124 of the test MOS transistor is formed on a semiconductor substrate 100, institute
State gate dielectric layer 124 be usually silicon oxide layer or high-K gate dielectric material layer, and Semiconductor substrate 100 be usually silicon layer, germanium layer or
Lattice between germanium silicon layer etc., therefore the gate dielectric layer 124 and Semiconductor substrate 100 is mismatched, the He of gate dielectric layer 124
Presence of an interface defect between Semiconductor substrate 100（Interface trap）, found by research, the quantity of the boundary defect
It is proportional with temperature, by measuring the boundary defect quantity between gate dielectric layer and Semiconductor substrate, test MOS can be obtained brilliant
The real time temperature of body pipe.And because the test MOS transistor is disposed adjacent with unit to be detected, therefore the test MOS is brilliant
The temperature of body pipe is the temperature of unit to be detected.
In the prior art, generally using capacitance-voltage method, 1/f noise analytic approach, grid-control leakage lining PN junction method etc. quantitatively
The quantity of measure interface defect, but the several method all there is respective defect so that test result is not accurate enough.Therefore, this
Inventive embodiments utilize charge pump（Charge Pumping）The quantity of technology measure interface defect, is tested using charge pumping technique
Physical model it is more visible, can directly reflect the quantity of boundary defect, and be easy to test.
Fig. 3 is refer to, to utilize the measurement structural representation of charge pumping technique measure interface defects count, including：Partly lead
Body substrate 200；Grid structure 210 positioned at the surface of Semiconductor substrate 200, the grid structure 210 includes being located at semiconductor lining
The gate dielectric layer 211 on the surface of bottom 200 and the gate electrode 212 positioned at the surface of gate dielectric layer 211；Positioned at 210 liang of the grid structure
Source region 230 and drain region 240 in the Semiconductor substrate 200 of side, the Semiconductor substrate 200 and one end phase of an ammeter 250
Connection, the ammeter 250 is used for the size for testing the alternating current for flowing through Semiconductor substrate 200；The source region 230 and drain region
240 are electrically connected and are connected with one end of dc source 260, and the other end of the dc source 260 is another with ammeter 250
One end is connected, and causes that the PN junction between source region 230, drain region 240 and Semiconductor substrate 200 is anti-using the dc source 260
Partially.In the present embodiment, illustrated by taking nmos pass transistor as an example, the Semiconductor substrate 200 is adulterated for p-type, the source region
230th, drain region 240 is n-type doping, and in other embodiments, the MOS transistor can also be PMOS transistor.
During using charge pumping technique measure interface defects count, apply specific frequency, specific width on the gate electrode 212
The voltage pulse signal of degree.It refer to Fig. 4, threshold voltage V of the voltage pulse signal across test MOS transistorthPeace
V with voltagefb, i.e., threshold voltage V of the high level more than the test MOS transistor of described voltage pulse signalth, the electricity
The low level of pressure pulse signal is less than flat-band voltage Vfb.In the present embodiment, the high level phase of each voltage pulse signal
Together, low level is also all identical.In other embodiments, the high level of each voltage pulse signal, low level can also
Differ, but threshold voltage V of at least part high level more than the MOS transistor of whole voltage pulse signalth, whole electricity
At least part low level of pressure pulse signal is less than flat-band voltage Vfb.And when rise time, the decline of the voltage pulse signal
Between be respectively less than boundary defect transmitting time constant.
When the voltage that gate electrode 212 applies is the high level of voltage pulse signal, at the channel region surface of MOS transistor
In anti-type state, electronics flows to channel region from source region 230, drain region 240, and a portion is captured by boundary defect.When grid electricity
When the voltage that pole 212 applies is changed into the low level of voltage pulse signal, channel region will be changed into accumulated state, the movable electricity of channel region
Subflow can source region 230 and drain region 240, but rise time, fall time due to voltage pulse signal be respectively less than boundary defect hair
The time constant penetrated, the electronics captured by boundary defect, especially those be located at compared with deep energy level boundary defect capture electronics,
Have little time to be transmitted back to conduction band, and with the hole-recombination of Semiconductor substrate 200.Similarly, when gate electrode 212 apply voltage again
When being changed into the high level of voltage pulse signal, boundary defect has little time transmitting so that the hole of valence band and source region 230 and drain region
240 electronics is combined.Therefore, from the point of view of whole cycle, source region and leakage are flowed to equivalent to one is generated by Semiconductor substrate
The electric current in area, the electric current is referred to as charge pump current.
Fig. 5 is refer to, when the bias between Semiconductor substrate 200 and source region 230, drain region 240 is differed, corresponding electricity
Lotus pump electric current is also differed, in the present embodiment, when the bias between Semiconductor substrate 200 and source region 230, drain region 240 for-
During 0.6V~-0.8V, charge pump current is maximum Icpmax, now correspond to the quantity as grid structure of the boundary defect measured
Whole boundary defect quantity between 210 and Semiconductor substrate 200.The expression formula of the charge pump current maximum is：
Icpmax=q Δs EfWLNit
Wherein q is electron charge, and Δ E is the boundary defect energy range of chief of the Xiongnu in Acient China's charge pump current, and f is pulse frequency, W, L
For the wide of channel region and long, NitFor average surface defect concentration.From above-mentioned formula it can be seen that the quantity WLN of boundary defectitWith
Charge pump current maximum IcpmaxIt is proportional, average surface defect concentration NitWith charge pump current maximum IcpmaxIt is proportional.Together
When due to the quantity and temperature of boundary defect it is proportional, therefore, the charge pump current maximum IcpmaxIt is proportional with temperature, only
Need to measure the charge pump current maximum I of the MOS transistorcpmax, you can obtain the real time temperature of MOS transistor.
Therefore, the detection structure first is placed on into the wafer-supporting platform surface with heating function, the unit to be detected is not
Work, the temperature of geodesic structure to be checked is adjusted using wafer-supporting platform, so as to obtain the maximum of the charge pump current of test MOS transistor
Corresponding relation between temperature.
Fig. 2 is refer to, because the unit to be detected does not work, does not apply voltage, therefore unit to be detected will not be spontaneous
Heat, the temperature of the unit to be detected is to be equal to the temperature that wafer-supporting platform is set.By adjusting the temperature of wafer-supporting platform, measurement correspondence temperature
The charge pump current maximum I of test MOS transistor under degreecpmax。
In the present embodiment, the source region 122 and drain region 123 for testing MOS transistor by two are electrically connected straight with one afterwards
One end of stream voltage is connected, and the other end of the DC voltage is connected by an ammeter with Semiconductor substrate 100,
Apply voltage pulse signal, threshold voltage V of the voltage pulse signal across test MOS transistor on gate electrode 125thWith
Flat-band voltage Vfb, and the voltage pulse signal rise time, fall time be respectively less than boundary defect transmitting time constant.
By adjusting the bias between Semiconductor substrate and source region, drain region, the charge pump electricity of test MOS transistor under relevant temperature is obtained
Flow maximum Icpmax.Simultaneously by adjusting the temperature that wafer-supporting platform is set, the charge pump that MOS transistor is tested under different temperatures is obtained
Current maxima Icpmax, obtain the maximum of charge pump current and the corresponding relation of temperature.
Then, test voltage is applied to the unit to be detected, measures the maximum of the charge pump current of test MOS transistor
Value, so as to obtain current to be checked according to the corresponding relation between the maximum and temperature of the charge pump current of test MOS transistor
Survey the temperature of unit.
In the present embodiment, carried out because the two ends of the unit to be detected have respectively using the end method of testing of Kelvin four
Test two test leads, therefore using the end method of testing of Kelvin four treat detection unit apply test voltage electric property enter
Go and test, including treat electromigration characteristic, voltage-current characteristic, breakdown characteristics of detection unit etc. and tested.Wherein
In one embodiment, when the electromigration characteristic that detection unit is treated using the end method of testing of Kelvin four is tested, specifically include：
Apply the larger voltage stress of voltage in one of test lead of the unit to be detected per one end, by unit to be detected per one end
The measurement of another test lead by the electric current of unit to be detected, judge whether occur electromigration effect by the change of electric current.
Because unit to be detected applies test voltage, unit to be detected can be caused to generate heat, the temperature of unit to be detected is higher than
Ambient temperature, using prior art it is difficult to real time temperature that is accurate and easily measuring unit to be detected.And the embodiment of the present invention
In, measure the charge pump current maximum of the test MOS transistor again using charge pumping technique.When measuring corresponding electric charge
Pump current maxima IcpmaxWhen, according to the corresponding relation of the maximum of the charge pump current and temperature, acquisition now measures MOS
The temperature of transistor.
In the present embodiment, when applying test voltage to the unit to be detected, the heating function of the wafer-supporting platform is closed.
In other embodiments, when applying test voltage to the unit to be detected, the heating function of the wafer-supporting platform can also be opened.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (12)
1. a kind of detection method, it is characterised in that including：
Detection structure is provided, the detection structure includes：Semiconductor substrate, positioned at the unit to be detected of semiconductor substrate surface,
The test MOS transistor being disposed adjacent with the unit to be detected；
The detection structure is placed on the wafer-supporting platform surface with heating function, the unit to be detected does not work, using holding
Piece platform adjusts the temperature of geodesic structure to be checked, so that between obtaining the maximum and temperature of the charge pump current of test MOS transistor
Corresponding relation；
Test voltage is applied to the unit to be detected, the maximum of the charge pump current of test MOS transistor is measured, so that root
The temperature of current unit to be detected is obtained according to the corresponding relation between the maximum and temperature of the charge pump current of test MOS transistor
Degree；
The method of the maximum of the charge pump current of the measurement test MOS transistor includes：The source of the test MOS transistor
Area and drain region are electrically connected to be connected with one end of dc source afterwards, and the other end of the dc source passes through an ammeter
It is connected with Semiconductor substrate, voltage pulse signal, the voltage pulse letter is applied in the gate electrode of the test MOS transistor
Number across test MOS transistor threshold voltage and flat-band voltage, and rise time, the fall time of the voltage pulse signal
Respectively less than the time constant of boundary defect transmitting, charge pump current is measured using the ammeter；And served as a contrast by adjusting semiconductor
Bias between bottom and source region, drain region, obtains the maximum of charge pump current, wherein, the voltage pulse signal is across test
The threshold voltage and flat-band voltage of MOS transistor be：It is brilliant that at least part high level of the voltage pulse signal is more than the MOS
The threshold voltage of body pipe, at least part low level of the voltage pulse signal is less than flat-band voltage.
2. detection method as claimed in claim 1, it is characterised in that the height electricity of each pulse of the voltage pulse signal
Threshold voltage that is flat equal and being more than test MOS transistor, the low level of each pulse of the voltage pulse signal is equal
And less than the flat-band voltage of test MOS transistor.
3. detection method as claimed in claim 1, it is characterised in that test voltage measurement pair is applied to the unit to be detected
During the maximum of the charge pump current for the test MOS transistor answered, the heating function of the wafer-supporting platform is closed.
4. detection method as claimed in claim 1, it is characterised in that treat detection unit using the end method of testing of Kelvin four and apply
Plus the electric property of test voltage is tested.
5. detection method as claimed in claim 4, it is characterised in that treat detection unit using the end method of testing of Kelvin four and apply
Plus the electromigration characteristic of test voltage is tested.
6. one kind detection structure, it is characterised in that including：
Semiconductor substrate, positioned at the unit to be detected of semiconductor substrate surface, the test being disposed adjacent with the unit to be detected
MOS transistor, the maximum of the charge pump current by measuring the test MOS transistor, obtains the unit to be detected
Temperature；
The method of the maximum of the charge pump current of the measurement test MOS transistor includes：The source of the test MOS transistor
Area and drain region are electrically connected to be connected with one end of dc source afterwards, and the other end of the dc source passes through an ammeter
It is connected with Semiconductor substrate, voltage pulse signal, the voltage pulse letter is applied in the gate electrode of the test MOS transistor
Number across test MOS transistor threshold voltage and flat-band voltage, and rise time, the fall time of the voltage pulse signal
Respectively less than the time constant of boundary defect transmitting, charge pump current is measured using the ammeter；And served as a contrast by adjusting semiconductor
Bias between bottom and source region, drain region, obtains the maximum of charge pump current, wherein, the voltage pulse signal is across test
The threshold voltage and flat-band voltage of MOS transistor be：It is brilliant that at least part high level of the voltage pulse signal is more than the MOS
The threshold voltage of body pipe, at least part low level of the voltage pulse signal is less than flat-band voltage.
7. structure is detected as claimed in claim 6, it is characterised in that the unit to be detected is for resistance or positioned at core devices
The MOS transistor in area.
8. structure is detected as claimed in claim 7, it is characterised in that when the unit to be detected is resistance, the resistance
Two ends there are two test leads being tested using the end method of testing of Kelvin four respectively.
9. structure is detected as claimed in claim 7, it is characterised in that described to be checked when the unit to be detected is resistance
The material for surveying unit is polysilicon, tantalum nitride or titanium nitride.
10. structure is detected as claimed in claim 6, it is characterised in that the test MOS transistor is located at unit to be detected
Both sides are set around unit to be detected.
11. structure is detected as claimed in claim 6, it is characterised in that when the quantity of the test MOS transistor is two
When, described two test MOS transistors are located at the both sides of unit to be detected, and the grid of described two test MOS transistors respectively
Electrode is electrically connected, and the source region of described two test MOS transistors is electrically connected, the drain region of described two test MOS transistors
It is electrically connected.
12. structure is detected as claimed in claim 6, it is characterised in that the test MOS transistor is input/output device
The MOS transistor in area.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW452907B (en) * | 1999-11-22 | 2001-09-01 | Winbond Electronics Corp | Testing device and method of positive mobile ion contamination |
| CN1377068A (en) * | 2001-03-28 | 2002-10-30 | 华邦电子股份有限公司 | Test device and method removing cationic pollution |
| CN1482620A (en) * | 2002-07-12 | 2004-03-17 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
| CN1502132A (en) * | 2001-02-23 | 2004-06-02 | �����ɷ� | Electromigration test structure for detecting the reliability of wiring |
| CN102841300A (en) * | 2012-09-14 | 2012-12-26 | 北京大学 | Structure and method for testing temperature characteristic of MOS (Metal Oxide Semiconductor) device |
| CN103098198A (en) * | 2010-09-03 | 2013-05-08 | 三菱电机株式会社 | Semiconductor device |
| CN103187397A (en) * | 2011-12-27 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Micro heating device |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW452907B (en) * | 1999-11-22 | 2001-09-01 | Winbond Electronics Corp | Testing device and method of positive mobile ion contamination |
| CN1502132A (en) * | 2001-02-23 | 2004-06-02 | �����ɷ� | Electromigration test structure for detecting the reliability of wiring |
| CN1377068A (en) * | 2001-03-28 | 2002-10-30 | 华邦电子股份有限公司 | Test device and method removing cationic pollution |
| CN1482620A (en) * | 2002-07-12 | 2004-03-17 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
| CN103098198A (en) * | 2010-09-03 | 2013-05-08 | 三菱电机株式会社 | Semiconductor device |
| CN103187397A (en) * | 2011-12-27 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Micro heating device |
| CN102841300A (en) * | 2012-09-14 | 2012-12-26 | 北京大学 | Structure and method for testing temperature characteristic of MOS (Metal Oxide Semiconductor) device |
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