CN104639145B - Input interface circuit - Google Patents
Input interface circuit Download PDFInfo
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- CN104639145B CN104639145B CN201310556588.4A CN201310556588A CN104639145B CN 104639145 B CN104639145 B CN 104639145B CN 201310556588 A CN201310556588 A CN 201310556588A CN 104639145 B CN104639145 B CN 104639145B
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Abstract
The invention discloses a kind of input interface circuit, including：One esd protection circuit, is made up of, the damage for preventing external electrostatic discharges from being caused to chip main esd protection circuit and time esd protection circuit；One shaping circuit, is made up of Schmidt circuit and buffer, is connected with esd protection circuit, and the power supply of its Schmidt circuit is provided by inputting PAD, for carrying out shaping to input signal；One trap resistance circuit, is connected with shaping circuit, for preventing attacker to chip internal addition signal；One internal protection circuitry, is connected with trap resistance circuit, the damage for the voltage that prevents from producing during scribing to chip internal circuits, and the output end of input interface circuit is exported fixed low level when resistance is cut off；One buffer circuit, is connected with internal protection circuitry, for strengthening input interface driving force.The present invention can significantly improve the attack tolerant of chip, attacker can not be attacked by inputting PAD chip internal circuits.
Description
Technical field
The present invention relates to I/O interface circuits field, more particularly to a kind of input interface circuit.
Background technology
With the fast development of integrated circuit technology, chip is widely used in all trades and professions, makes in financial security field
Chip proposes higher requirement to the security of chip.
For the higher chip of level of security, designer will not only be concerned about the security algorithm module of chip but also pay close attention to core
The interface of piece.Interface circuit is directly connected with the external world, thus is easiest to be attacked, and attacker need not destroy chip, it is possible to
Chip is attacked by I/O interfaces.
Shown in Figure 1, traditional input interface circuit is by esd protection circuit, Schmidt circuit and buffer circuit composition.
Esd protection circuit is exactly ESD protection circuit, can solve chip encapsulating, assemble, test, depositing, removing
The most of electrostatic discharge problems suffered from during fortune etc..When outside high-voltage pulse is by chip interface, ESD protections
Circuit is opened, high current of releasing, so as to protect internal circuit, is not resulted in the internal components of chip and irreversible is punctured damage
It is bad.
Schmidt circuit is to carry out shaping to input signal.The signal generally come from input port is not preferable height
Level signal, wherein may some burrs, Schmidt circuit can filter out these burrs.
Buffer circuit is to be used to strengthen input interface driving force to drive successive load.
External signal is by PAD (interface) ports to chip input data, and data are after esd protection circuit, then pass through
Schmidt circuit shaping, the inside of chip is output to finally by buffer circuit.
Traditional input interface circuit does not have attack tolerant.Due in traditional input interface circuit, input PAD with it is interior
There is parasitic diode between portion's I/O power supplys (VCC), attacker can directly change the electricity of internal electric source by inputting PAD
Pressure, destroys the normal work of internal circuit, chip is entered the default state of attacker, so as to obtain the significant data of inside.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of input interface circuit, it can effectively improve chip input and connect
The attack tolerant energy of mouth.
In order to solve the above technical problems, the input interface circuit of the present invention, including：
One esd protection circuit, is made up of main esd protection circuit and time esd protection circuit, prevents external electrostatic discharges to core
The damage that piece is caused；
One shaping circuit, is made up of Schmidt circuit and buffer, is connected with the esd protection circuit, its Schmidt
The power supply of circuit is provided by inputting PAD, for carrying out shaping to input signal；
One trap resistance circuit, is connected with the shaping circuit, for preventing attacker to chip internal addition signal；
One internal protection circuitry, is connected with the trap resistance circuit, for the voltage that prevents from producing during scribing to chip
The damage of internal circuit, and the output end of input interface circuit is exported fixed low level when resistance is cut off；
One buffer circuit, is connected with the internal protection circuitry, for strengthening input interface driving force, so as to drive
Late-class circuit works.
In the input interface circuit of the present invention, esd protection circuit has done suitably modified to traditional esd protection circuit, mesh
Be in order to remove the parasitic diode between PAD and I/O power supplies VCC, so that attacker can not directly be grasped by PAD
Control I/O power supplies VCC.
The power supply of Schmidt circuit is provided by inputting PAD in shaping circuit, without being provided by I/O power supplies VCC
Power supply.Therefore also different from traditional Schmidt circuit.It can so make completely not having between input PAD and I/O power supply VCC
There is path, so as to further increase safety coefficient.
Trap resistance circuit can prevent attacker from adding signal to chip internal.
Internal protection circuitry has two effects, one is the voltage that protection chip internal circuits are produced when will not be because of scribing
And sustain damage；The second is making the output end of input interface circuit export fixed low level after resistance is cut off.
The present invention can significantly improve the attack tolerant of chip, make attacker can not be by inputting PAD to chip internal circuits
Attacked.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is traditional input interface circuit schematic diagram；
Fig. 2 is the embodiment schematic diagram of input interface circuit one of the present invention；
Fig. 3 is the embodiment schematic diagram of Schmidt circuit one in Fig. 2.
Embodiment
It is shown in Figure 2, input interface circuit of the invention in the following embodiments, including：
One esd protection circuit, by nmos pass transistor M11 and M12, resistance R11 and R12 are constituted.Wherein, nmos pass transistor
M11 and resistance R11 is main esd protection circuit, uses grid coupled structure.Resistance R12 is ESD current-limiting resistances, NMOS crystal
Pipe M12 is time esd protection circuit, the grid of protection late-class circuit (Schmidt circuit).
Nmos pass transistor M11 drain electrode is connected with resistance R12 one end, and is used as PAD input, nmos pass transistor
M11 grid is connected with resistance R11 one end, and the resistance R11 other end connects with nmos pass transistor M11 source electrode and substrate
Ground.
The resistance R12 other end is connected with PMOS transistor M12 source electrode, and its node connected is designated as net1, and it is made
For the power supply input of Schmidt circuit；
Nmos pass transistor M12 grid, source electrode and Substrate ground.
One shaping circuit, is made up of Schmidt circuit and buffer.
With reference to shown in Fig. 3, the Schmidt circuit is by PMOS transistor M31~M33, nmos pass transistor M34~M36 groups
Into.PMOS transistor M31 source electrode is connected with power supply VCC ends, the power supply electricity of power supply VCC ends and Schmidt circuit
Source input net1 ends are connected.PMOS transistor M31 drain electrode and PMOS transistor M32 source electrode and PMOS transistor M33
Source electrode be connected.PMOS transistor M31~M33 substrate is connected with power supply VCC ends.
PMOS transistor M32 drain electrode is brilliant with PMOS transistor M33 grid, nmos pass transistor M34 drain electrode and NMOS
Body pipe M36 grid is connected.Its connect node as Schmidt circuit output end OUT.Nmos pass transistor M34 source electrode
The source electrode of drain electrode and nmos pass transistor M36 with nmos pass transistor M35 is connected.Nmos pass transistor M36 drain electrode and power supply electricity
Source VCC ends are connected.
The source ground of nmos pass transistor M34~M36 substrate, PMOS transistor M33 drain electrode and nmos pass transistor M35
VSS。
PMOS transistor M31 grid, PMOS transistor M32 grid, nmos pass transistor M34 grid and NMOS crystal
Pipe M35 grid is connected, and its node connected is designated as A.
Buffer is made up of PMOS transistor M13 and nmos pass transistor M14, and PMOS transistor M13 grid and NMOS is brilliant
Body pipe M14 grid is connected with the output end OUT of Schmidt circuit, and its node connected is designated as net2.PMOS transistor M13
Source electrode and substrate be connected with node net1.PMOS transistor M13 drain electrode is connected with nmos pass transistor M14 drain electrode,
Its node connected is designated as net3 and as the output end of buffer.PMOS transistor M14 source electrode and Substrate ground VSS.
When PAD input high levels, economize on electricity net1 is high level, and the node net2 of Schmidt circuit SMT1 output ends is low
Level, the output end net3 of buffer is high level；When PAD inputs are low level, economize on electricity net1 is low level, close due to applying
The power supply of special circuit and buffer is all connected on resistance R2 one end and is low level, therefore the node of Schmidt circuit output end
Net2 is low level, and the output end net3 of buffer is low level.
One trap resistance circuit, is made up of, its one end is connected with node net3, the other end is designated as net4 ends trap resistance R13.
Trap resistance R13 has two kinds of ways：One kind is that trap resistance R13 is placed on into chip internal, and another is to be placed on trap resistance R13
In scribe line (chip exterior).If trap resistance R13 is placed in scribe line, after chip scribing, trap resistance R13 is drawn disconnected,
The connection at node net3 ends and net4 ends disconnects, and so inputting PAD just can not internally add any signal, this way one
As be used for test I/O interfaces, just test access is cut off after the completion of chip testing, prevents attacker from internally adding signal.Such as
Fruit trap resistance R13 is made in chip internal, then no matter chip whether scribing, trap resistance R13 will not be drawn disconnected.If as normal
The input interface circuit used, trap resistance R13 is positioned over chip internal.
One internal protection circuitry, is made up of nmos pass transistor M15 and nmos pass transistor M16.Nmos pass transistor M15 drain electrode
It is connected with node net4 ends, nmos pass transistor M15 grid, source electrode and Substrate ground VSS.Nmos pass transistor M16 drain electrode
It is connected with node net4 ends, nmos pass transistor M16 source electrode and Substrate ground VSS.Nmos pass transistor M16 grid and power supply
Voltage vdd terminal is connected.Trap resistance R13, which is drawn, to have no progeny, in order to ensure the low electricity of input interface circuit output end OUT output fixations
Flat, nmos pass transistor M16 is used as the weak resistance got off, and internal protection circuitry is designed as down than pipe.Nmos pass transistor M15 is played
The effect of ESD protections, voltage that protection internal circuit is produced when will not be because of scribing and sustain damage.
One buffer circuit, by nmos pass transistor M18 and M20, PMOS transistor M17 and M19 are constituted.PMOS transistor M17
Source electrode and substrate be connected with PMOS transistor M19 source electrode and substrate with supply voltage vdd terminal.PMOS transistor M17's
Grid is connected with nmos pass transistor M18 grid with node net4 ends, nmos pass transistor M18 source electrode and Substrate ground VSS.
PMOS transistor M17 drain electrode and nmos pass transistor M18 drain electrode, PMOS transistor M19 grid and nmos pass transistor M20
Grid is connected.PMOS transistor M19 drain electrode is connected with nmos pass transistor M20 drain electrode.Nmos pass transistor M20 source electrode
With Substrate ground VSS.
In order to strengthen driving force during buffer circuit, so as to drive late-class circuit to work.
Although the present invention is illustrated using specific embodiment, the explanation to embodiment is not intended to limit the present invention's
Scope.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, easily carry out various modifications or embodiment can be combined.
Claims (3)
1. a kind of input interface circuit, it is characterised in that including：
One esd protection circuit, is made up of main esd protection circuit and time esd protection circuit, prevents external electrostatic discharges from being made to chip
Into damage；
One shaping circuit, is made up of Schmidt circuit and buffer, is connected with the esd protection circuit, its Schmidt circuit
Power supply by input PAD provide, for input signal carry out shaping；
One trap resistance circuit, is connected with the shaping circuit, for preventing attacker to chip internal addition signal；
One internal protection circuitry, is connected with the trap resistance circuit, for the voltage that prevents from producing during scribing to chip internal
The damage of circuit, and the output end of input interface circuit is exported fixed low level when resistance is cut off；
One buffer circuit, is connected with the internal protection circuitry, for strengthening input interface driving force, so as to drive rear class
Circuit works；
The esd protection circuit, by the 11st nmos pass transistor (M11) and the tenth bi-NMOS transistor (M12), the 11st resistance
(R11) constituted with the 12nd resistance (R12)；Wherein, the 11st nmos pass transistor (M11) and the 11st resistance (R11) are main ESD
Protection circuit, using grid coupled structure；12nd resistance (R12) is ESD current-limiting resistances, and the tenth bi-NMOS transistor (M12) is
Secondary esd protection circuit, protects the grid of rear class Schmidt circuit；
The drain electrode of 11st nmos pass transistor (M11) is connected with one end of the 12nd resistance (R12), and is used as PAD input
End, the grid of the 11st nmos pass transistor (M11) is connected with one end of the 11st resistance (R11), the 11st resistance (R11)
The source electrode and Substrate ground of the other end and the 11st nmos pass transistor (M11)；
The other end of 12nd resistance (R12) is connected with the drain electrode of the tenth bi-NMOS transistor (M12), its node connected note
For net1, its as Schmidt circuit power supply input；
Grid, source electrode and the Substrate ground of tenth bi-NMOS transistor (M12)；
The Schmidt circuit is by the PMOS transistor (M31~M33) of the 31st PMOS transistor~the 33rd, the 34th
The nmos pass transistor (M34~M36) of nmos pass transistor~the 36th composition；The source electrode of 31st PMOS transistor (M31) with
Power supply (VCC) end is connected；The drain electrode of 31st PMOS transistor (M31) and the 32nd PMOS transistor (M32)
Source electrode and the source electrode of the 33rd PMOS transistor (M33) be connected；The PMOS of 31st PMOS transistor~the 33rd
The substrate of transistor (M31~M33) is connected with power supply (VCC) end；
The drain electrode of 32nd PMOS transistor (M32) and grid, the 34th NMOS of the 33rd PMOS transistor (M33)
The drain electrode of transistor (M34) is connected with the grid of the 36th nmos pass transistor (M36), and its node connected is used as Schmidt
The output end (OUT) of circuit；The leakage of the source electrode and the 35th nmos pass transistor (M35) of 34th nmos pass transistor (M34)
Pole is connected with the source electrode of the 36th nmos pass transistor (M36)；The drain electrode of 36th nmos pass transistor (M36) and power supply electricity
Source (VCC) end is connected；
The substrate of the nmos pass transistor (M34~M36) of 34th nmos pass transistor~the 36th, the 33rd PMOS transistor
(M33) drain electrode and the source ground (VSS) of the 35th nmos pass transistor (M35)；
Grid, grid, the 34th NMOS of the 32nd PMOS transistor (M32) of 31st PMOS transistor (M31)
The grid of the grid of transistor (M34) and the 35th nmos pass transistor (M35) is connected, and its node connected is designated as A；
The buffer is made up of the 13rd PMOS transistor (M13) and the 14th nmos pass transistor (M14), and the 13rd PMOS is brilliant
The grid of body pipe (M13) and the 14th nmos pass transistor (M14) is connected with the output end (OUT) of Schmidt circuit, and it is connected
Node be designated as net2；The source electrode and substrate of 13rd PMOS transistor (M13) hold phase with Schmidt circuit power supply (VCC)
Connection；The drain electrode of 13rd PMOS transistor (M13) is connected with the drain electrode of the 14th nmos pass transistor (M14), what it was connected
Node is designated as net3 and as the output end of buffer；The source electrode and Substrate ground (VSS) of 14th nmos pass transistor (M14)；
The internal protection circuitry is made up of the 15th nmos pass transistor (M15) and the 16th nmos pass transistor (M16)；15th
The drain electrode of nmos pass transistor (M15) is connected with the output end of the trap resistance circuit, the grid of the 15th nmos pass transistor (M15)
Pole, source electrode and Substrate ground (VSS)；The drain electrode of 16th nmos pass transistor (M16) and the output end phase of the trap resistance circuit
Connection, the source electrode and Substrate ground (VSS) of the 16th nmos pass transistor (M16)；The grid of 16th nmos pass transistor (M16) with
Supply voltage (VDD) end is connected.
2. input interface circuit as claimed in claim 1, it is characterised in that：The trap resistance circuit is by trap resistance (R13) group
Into its one end is connected with the output end of the buffer, and the other end is designated as net4 ends.
3. input interface circuit as claimed in claim 2, it is characterised in that：The trap resistance (R13) is placed on chip internal,
Or be placed in scribe line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310556588.4A CN104639145B (en) | 2013-11-11 | 2013-11-11 | Input interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310556588.4A CN104639145B (en) | 2013-11-11 | 2013-11-11 | Input interface circuit |
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| Publication Number | Publication Date |
|---|---|
| CN104639145A CN104639145A (en) | 2015-05-20 |
| CN104639145B true CN104639145B (en) | 2017-10-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310556588.4A Active CN104639145B (en) | 2013-11-11 | 2013-11-11 | Input interface circuit |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115903986B (en) * | 2023-02-08 | 2023-05-16 | 上海海栎创科技股份有限公司 | Input/output circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101046853A (en) * | 2007-04-28 | 2007-10-03 | 华中科技大学 | Static protection circuit suitable for radio frequency identification label chip |
| CN101478300A (en) * | 2009-01-06 | 2009-07-08 | 东南大学 | Digital clock duty ratio calibrating circuit |
| CN101826791A (en) * | 2010-05-06 | 2010-09-08 | 日银Imp微电子有限公司 | UVLO circuit |
| CN202759437U (en) * | 2012-06-21 | 2013-02-27 | 上海华虹集成电路有限责任公司 | Interface circuit for dual-interface smart card |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7894174B2 (en) * | 2004-08-23 | 2011-02-22 | Monolithic Power Systems, Inc. | Method and apparatus for fault detection scheme for cold cathode fluorescent lamp (CCFL) integrated circuits |
-
2013
- 2013-11-11 CN CN201310556588.4A patent/CN104639145B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101046853A (en) * | 2007-04-28 | 2007-10-03 | 华中科技大学 | Static protection circuit suitable for radio frequency identification label chip |
| CN101478300A (en) * | 2009-01-06 | 2009-07-08 | 东南大学 | Digital clock duty ratio calibrating circuit |
| CN101826791A (en) * | 2010-05-06 | 2010-09-08 | 日银Imp微电子有限公司 | UVLO circuit |
| CN202759437U (en) * | 2012-06-21 | 2013-02-27 | 上海华虹集成电路有限责任公司 | Interface circuit for dual-interface smart card |
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| Publication number | Publication date |
|---|---|
| CN104639145A (en) | 2015-05-20 |
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