CN104639145A - Input interface circuit - Google Patents
Input interface circuit Download PDFInfo
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- CN104639145A CN104639145A CN201310556588.4A CN201310556588A CN104639145A CN 104639145 A CN104639145 A CN 104639145A CN 201310556588 A CN201310556588 A CN 201310556588A CN 104639145 A CN104639145 A CN 104639145A
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Abstract
The invention discloses an input interface circuit comprising an ESD (electro-static discharge) protection circuit, a waveshaping circuit, a well resistor circuit, an internal protection circuit and a buffer circuit. The ESD protection circuit includes a main ESD protection circuit and an auxiliary ESD protection circuit and prevents a chip from the damage made by external electrostatic discharge. The waveshaping circuit is composed of a Schmidt circuit and a buffer and connected with the ESD protection circuit. The Schmidt circuit is powered by an input PAD and used for shaping input signals. The well resistor circuit is connected with the waveshaping circuit and used for preventing an attacker from adding signals into the chip. The internal protection circuit is connected with the well resistor circuit and used for preventing voltage, caused during scribing, against damaging a circuit in the chip and allowing an output end of the input interface circuit outputting fixed low level as a resistor is cut off. The buffer circuit is connected with the internal protection circuit and used for strengthening drive capability of an input interface. The input interface circuit has the advantages that anti-attacking capability of the chip is remarkably improved, and accordingly the circuit in the chip is protected from damage of the attacker through the input PAD.
Description
Technical field
The present invention relates to I/O interface circuit field, particularly relate to a kind of input interface circuit.
Background technology
Along with the fast development of integrated circuit technology, chip is widely used in all trades and professions, and the fail safe of chip to chip used in financial security field is had higher requirement.
For the chip that level of security is higher, designer not only will be closed the security algorithm module of chip centroid but also will be paid close attention to the interface of chip.Interface circuit is directly connected with the external world, is thus the most easily attacked, and assailant, without the need to destroying chip, just can be attacked chip by I/O interface.
Shown in Figure 1, traditional input interface circuit is by esd protection circuit, and Schmidt circuit and buffer circuit form.
Esd protection circuit is exactly ESD protection circuit, can solve chip encapsulating, most of electrostatic discharge problems of assembling, test, deposit, suffering from the process such as carrying.When the high-voltage pulse of outside is by chip interface, esd protection circuit is opened, big current of releasing, thus protection internal circuit, make the internal components of chip can not cause irreversible punch through damage.
Schmidt circuit carries out shaping to input signal.The signal of usually coming from input port is not desirable low and high level signal, wherein may some burr, and Schmidt circuit can by these burr filterings.
Buffer circuit is for strengthening input interface driving force thus can driving successive load.
External signal is by PAD(interface) port inputs data to chip, and data after esd protection circuit, then through Schmidt circuit shaping, output to the inside of chip finally by buffer circuit.
Traditional input interface circuit does not have attack tolerant.Due in traditional input interface circuit, parasitic diode is there is between input PAD and inner I/O power supply (VCC), assailant directly can change the voltage of internal electric source by input PAD, destroy the normal work of internal circuit, the state making chip enter assailant to preset, thus obtain inner significant data.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of input interface circuit, effectively can improve the attack resistance performance of chip input interface.
For solving the problems of the technologies described above, input interface circuit of the present invention, comprising:
One esd protection circuit, is made up of main esd protection circuit and time esd protection circuit, prevents the damage that external electrostatic discharges causes chip;
One shaping circuit, is made up of Schmidt circuit and buffer, is connected with described esd protection circuit, and the power supply of its Schmidt circuit provides by inputting PAD, for carrying out shaping to input signal;
One trap resistance circuit, is connected with described shaping circuit, adds signal for preventing assailant to chip internal;
One internal protection circuitry, is connected with described trap resistance circuit, for preventing the voltage produced during scribing to the damage of chip internal circuits, and makes the output of input interface circuit export fixing low level when resistance is cut off;
One buffer circuit, is connected with described internal protection circuitry, for strengthening input interface driving force, thus drives late-class circuit work.
In input interface circuit of the present invention; esd protection circuit has made suitable amendment to traditional esd protection circuit; object is the parasitic diode in order to remove between PAD and I/O power supply VCC, thus makes assailant cannot directly manipulate I/O power supply VCC by PAD.
In shaping circuit, the power supply of Schmidt circuit provides by inputting PAD, without the need to providing power supply by I/O power supply VCC.Therefore traditional Schmidt circuit is also different from.Can make there is no path completely between input PAD and I/O power supply VCC like this, thus further increase coefficient of safety.
Trap resistance circuit can prevent assailant from adding signal to chip internal.
Internal protection circuitry has two effects, and first protect IC internal circuit can not sustain damage because of the voltage produced during scribing; It two is after resistance is cut off, make the output of input interface circuit export fixing low level.
The present invention can significantly improve the attack tolerant of chip, and assailant cannot be attacked chip internal circuits by input PAD.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is traditional input interface circuit schematic diagram;
Fig. 2 is input interface circuit one embodiment schematic diagram of the present invention;
Fig. 3 is Schmidt circuit one embodiment schematic diagram in Fig. 2.
Embodiment
Shown in Figure 2, input interface circuit of the present invention in the following embodiments, comprising:
One esd protection circuit, by nmos pass transistor M11 and M12, resistance R11 and R12 is formed.Wherein, nmos pass transistor M11 and resistance R11 is main esd protection circuit, employing be gate coupling structure.Resistance R12 is ESD current-limiting resistance, and nmos pass transistor M12 is the grid of time esd protection circuit, protection late-class circuit (Schmidt circuit).
The drain electrode of nmos pass transistor M11 is connected with one end of resistance R12, and as the input of PAD, the grid of nmos pass transistor M11 is connected with one end of resistance R11, the other end of resistance R11 and the source electrode of nmos pass transistor M11 and Substrate ground.
The other end of resistance R12 is connected with the source electrode of PMOS transistor M12, and its node connected is designated as net1, and it is as the power supply input of Schmidt circuit;
The grid of nmos pass transistor M12, source electrode and Substrate ground.
One shaping circuit, is made up of Schmidt circuit and buffer.
Shown in composition graphs 3, described Schmidt circuit is by PMOS transistor M31 ~ M33, and nmos pass transistor M34 ~ M36 forms.The source electrode of PMOS transistor M31 is held with power supply VCC1 and is connected, and power supply VCC1 end is held with the power supply input net1 of Schmidt circuit and is connected.The drain electrode of PMOS transistor M31 is connected with the source electrode of PMOS transistor M33 with the source electrode of PMOS transistor M32.The substrate of PMOS transistor M31 ~ M33 is held with power supply VCC1 and is connected.
The drain electrode of PMOS transistor M32 is connected with the grid of nmos pass transistor M36 with the drain electrode of the grid of PMOS transistor M33, nmos pass transistor M34.Its node connected is as the output OUT1 of Schmidt circuit.The source electrode of nmos pass transistor M34 is connected with the source electrode of nmos pass transistor M36 with the drain electrode of nmos pass transistor M35.The drain electrode of nmos pass transistor M36 is held with power supply VCC1 and is connected.
The source ground VSS of the substrate of nmos pass transistor M34 ~ M36, the drain electrode of PMOS transistor M33 and nmos pass transistor M35.
The grid of the grid of PMOS transistor M31, the grid of PMOS transistor M32, nmos pass transistor M34 is connected with the grid of nmos pass transistor M35, and its node connected is designated as A.
Buffer is made up of PMOS transistor M13 and nmos pass transistor M14, and the grid of PMOS transistor M13 is connected with the output OUT1 of Schmidt circuit with the grid of nmos pass transistor M14, and its node connected is designated as net2.The drain electrode of PMOS transistor M13 is connected with node net1 with substrate.The drain electrode of PMOS transistor M13 is connected with the drain electrode of nmos pass transistor M14, and its node connected is designated as net3 and as the output of buffer.The source electrode of PMOS transistor M14 and Substrate ground VSS.
When PAD input high level, economize on electricity net1 is high level, and the node net2 of Schmidt circuit SMT1 output is low level, and the output net3 of buffer is high level; When PAD is input as low level, economize on electricity net1 is low level, power supply due to Schmidt circuit and buffer is all connected on one end of resistance R2 and is low level, therefore the node net2 of Schmidt circuit output is low level, and the output net3 of buffer is low level.
One trap resistance circuit, be made up of trap resistance R13, its one end is connected with node net3, and the other end is designated as net4 end.Trap resistance R13 has two kinds of ways: one is that trap resistance R13 is placed on chip internal, and another kind is placed in scribe line (chip exterior) by trap resistance R13.If trap resistance R13 is placed in scribe line, after chip scribing, trap resistance R13 is drawn disconnected, node net3 holds the connection of holding with net4 to disconnect, such input PAD just cannot internally add any signal, this way is generally used for test I/O interface, is just cut off by test access, prevent assailant from internally adding signal after chip testing completes.If trap resistance R13 is made in chip internal, so no matter chip whether scribing, trap resistance R13 can not be drawn disconnected.If as the normal input interface circuit used, trap resistance R13 is positioned over chip internal.
One internal protection circuitry, is made up of nmos pass transistor M15 and nmos pass transistor M16.The drain electrode of nmos pass transistor M15 is held with node net4 and is connected, the grid of nmos pass transistor M15, source electrode and Substrate ground VSS.The drain electrode of nmos pass transistor M16 is held with node net4 and is connected, the source electrode of nmos pass transistor M15 and Substrate ground VSS.The grid of nmos pass transistor M16 is connected with supply voltage vdd terminal.Trap resistance R13 is drawn to have no progeny, and in order to ensure that input interface circuit output OUT exports fixing low level, nmos pass transistor M16 is used as the weak resistance got off, and internal protection circuitry is designed to down than pipe.Nmos pass transistor M15 plays the effect of esd protection, and protection internal circuit can not sustain damage because of the voltage produced during scribing.
One buffer circuit, is made up of nmos pass transistor M18 and M20, PMOS transistor M17 and M19.The source electrode of PMOS transistor M17 is connected with supply voltage vdd terminal with substrate with the source electrode of PMOS transistor M19 with substrate.The grid of PMOS transistor M17 and the grid of nmos pass transistor M18 are held with node net4 and are connected, nmos pass transistor M18 source electrode and Substrate ground VSS.The drain electrode of PMOS transistor M17 is connected with the grid of nmos pass transistor M20 with the drain electrode of nmos pass transistor M18, the grid of PMOS transistor M19.The drain electrode of PMOS transistor M19 is connected with the drain electrode of nmos pass transistor M20.The source electrode of nmos pass transistor M20 and Substrate ground VSS.
In order to strengthen driving force during buffer circuit, thus drive late-class circuit work.
Although the present invention utilizes specific embodiment to be described, the explanation of embodiment is not limit the scope of the invention.One skilled in the art, by reference to explanation of the present invention, when not deviating from the spirit and scope of the present invention, easily carrying out various amendment or can combine embodiment.
Claims (6)
1. an input interface circuit, is characterized in that, comprising:
One esd protection circuit, is made up of main esd protection circuit and time esd protection circuit, prevents the damage that external electrostatic discharges causes chip;
One shaping circuit, is made up of Schmidt circuit and buffer, is connected with described esd protection circuit, and the power supply of its Schmidt circuit provides by inputting PAD, for carrying out shaping to input signal;
One trap resistance circuit, is connected with described shaping circuit, adds signal for preventing assailant to chip internal;
One internal protection circuitry, is connected with described trap resistance circuit, for preventing the voltage produced during scribing to the damage of chip internal circuits, and makes the output of input interface circuit export fixing low level when resistance is cut off;
One buffer circuit, is connected with described internal protection circuitry, for strengthening input interface driving force, thus drives late-class circuit work.
2. input interface circuit as claimed in claim 1, is characterized in that: described esd protection circuit, and by the 11 nmos pass transistor (M11) and the tenth bi-NMOS transistor (M12), the 11 resistance (R11) and the 12 (R12) are formed; Wherein, the 11 nmos pass transistor (M11) and the 11 resistance (R11) are main esd protection circuits, adopt gate coupling structure; 12 resistance (R12) is ESD current-limiting resistance, and the tenth bi-NMOS transistor (M12) is time esd protection circuit, the grid of protection rear class Schmidt circuit;
The drain electrode of the 11 nmos pass transistor (M11) is connected with one end of the 12 resistance (R12), and as the input of PAD, the grid of the 11 nmos pass transistor (M11) is connected with one end of the 11 resistance (R11), the other end of the 11 resistance (R11) and the source electrode of the 11 nmos pass transistor (M11) and Substrate ground;
The other end of the 12 resistance (R12) is connected with the drain electrode of the tenth bi-NMOS transistor (M12), and its node connected is designated as net1, and it is as the power supply input of Schmidt circuit;
The grid of the tenth bi-NMOS transistor (M12), source electrode and Substrate ground.
3. input interface circuit as claimed in claim 1, is characterized in that:
Described Schmidt circuit is by the 31 PMOS transistor ~ the 33 PMOS transistor (M31 ~ M33), and the 34 nmos pass transistor ~ the 36 nmos pass transistor (M34 ~ M36) forms; The drain electrode of the 31 PMOS transistor (M31) is held with power supply (VCC1) and is connected; The source electrode of the 31 PMOS transistor (M31) is connected with the drain electrode of the 33 PMOS transistor (M33) with the drain electrode of the 32 PMOS transistor (M32); The substrate of the 31 PMOS transistor ~ the 33 PMOS transistor (M31 ~ M33) is held with power supply (VCC1) and is connected;
The source electrode of the 32 PMOS transistor (M32) is connected with the grid of the 36 nmos pass transistor (M36) with the grid of the 33 PMOS transistor (M33), the source electrode of the 34 nmos pass transistor (M34), and its node connected is as the output OUT1 of Schmidt circuit; The drain electrode of the 34 nmos pass transistor (M34) is connected with the drain electrode of the 36 nmos pass transistor (M36) with the source electrode of the 35 nmos pass transistor (M35); The source electrode of the 36 nmos pass transistor (M36) is held with power supply (VCC1) and is connected;
The substrate of the 34 nmos pass transistor ~ the 36 nmos pass transistor (M34 ~ M36), the drain electrode of the 33 PMOS transistor (M33) and the source ground VSS of nmos pass transistor M35.
The grid of the grid of PMOS transistor M31, the grid of PMOS transistor M32, nmos pass transistor M34 is connected with the grid of the 35 nmos pass transistor (M35), and its node connected is designated as A;
Described buffer is made up of the 13 PMOS transistor (M13) and the 14 nmos pass transistor (M14), 13 PMOS transistor (M13) is connected with the output (OUT1) of Schmidt circuit with the grid of the 14 nmos pass transistor (M14), and its node connected is designated as net2; The drain electrode of the 13 PMOS transistor (M13) and substrate are held with Schmidt circuit power supply (VCC1) and are connected; The drain electrode of the 13 PMOS transistor (M13) is connected with the drain electrode of the 14 nmos pass transistor (M14), and its node connected is designated as net3 and as the output of buffer; The source electrode of the 14 nmos pass transistor (M14) and Substrate ground VSS.
4. input interface circuit as claimed in claim 1, is characterized in that: described trap resistance circuit is made up of trap resistance (R13), and its one end is connected with the output of described buffer, and the other end is designated as net4 end.
5. input interface circuit as claimed in claim 4, is characterized in that: described trap resistance (R13) is placed on chip internal, or is placed in scribe line.
6. input interface circuit as claimed in claim 1, is characterized in that: described internal protection circuitry is made up of the 15 nmos pass transistor (M15) and the 16 nmos pass transistor (M16); The drain electrode of the 15 nmos pass transistor (M15) is connected with the output of described trap resistance circuit, the grid of the 15 nmos pass transistor (M15), source electrode and Substrate ground VSS; The drain electrode of the 16 nmos pass transistor (M16) is connected with the output of described trap resistance circuit, the source electrode of the 15 nmos pass transistor (M15) and Substrate ground VSS; The grid of the 16 nmos pass transistor (M16) is connected with supply voltage vdd terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310556588.4A CN104639145B (en) | 2013-11-11 | 2013-11-11 | Input interface circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310556588.4A CN104639145B (en) | 2013-11-11 | 2013-11-11 | Input interface circuit |
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| CN104639145A true CN104639145A (en) | 2015-05-20 |
| CN104639145B CN104639145B (en) | 2017-10-31 |
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| CN201310556588.4A Active CN104639145B (en) | 2013-11-11 | 2013-11-11 | Input interface circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115903986A (en) * | 2023-02-08 | 2023-04-04 | 上海海栎创科技股份有限公司 | Input/output circuit |
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| CN101046853A (en) * | 2007-04-28 | 2007-10-03 | 华中科技大学 | Static protection circuit suitable for radio frequency identification label chip |
| US20080158760A1 (en) * | 2004-08-23 | 2008-07-03 | Monolithic Power Systems, Inc. | Method and apparatus for fault detection scheme for cold cathode florescent lamp (ccfl) integrated circuits |
| CN101478300A (en) * | 2009-01-06 | 2009-07-08 | 东南大学 | Digital clock duty ratio calibrating circuit |
| CN101826791A (en) * | 2010-05-06 | 2010-09-08 | 日银Imp微电子有限公司 | UVLO circuit |
| CN202759437U (en) * | 2012-06-21 | 2013-02-27 | 上海华虹集成电路有限责任公司 | Interface circuit for dual-interface smart card |
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2013
- 2013-11-11 CN CN201310556588.4A patent/CN104639145B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080158760A1 (en) * | 2004-08-23 | 2008-07-03 | Monolithic Power Systems, Inc. | Method and apparatus for fault detection scheme for cold cathode florescent lamp (ccfl) integrated circuits |
| CN101046853A (en) * | 2007-04-28 | 2007-10-03 | 华中科技大学 | Static protection circuit suitable for radio frequency identification label chip |
| CN101478300A (en) * | 2009-01-06 | 2009-07-08 | 东南大学 | Digital clock duty ratio calibrating circuit |
| CN101826791A (en) * | 2010-05-06 | 2010-09-08 | 日银Imp微电子有限公司 | UVLO circuit |
| CN202759437U (en) * | 2012-06-21 | 2013-02-27 | 上海华虹集成电路有限责任公司 | Interface circuit for dual-interface smart card |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115903986A (en) * | 2023-02-08 | 2023-04-04 | 上海海栎创科技股份有限公司 | Input/output circuit |
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| CN104639145B (en) | 2017-10-31 |
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