CN104576872B - Semiconductor LED chip and manufacturing method thereof - Google Patents
Semiconductor LED chip and manufacturing method thereof Download PDFInfo
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- CN104576872B CN104576872B CN201310476571.8A CN201310476571A CN104576872B CN 104576872 B CN104576872 B CN 104576872B CN 201310476571 A CN201310476571 A CN 201310476571A CN 104576872 B CN104576872 B CN 104576872B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 26
- 238000001312 dry etching Methods 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002360 preparation method Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 238000004020 luminiscence type Methods 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 238000000605 extraction Methods 0.000 abstract description 7
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical class [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 241001062009 Indigofera Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention relates to a semiconductor LED (Light-Emitting Diode) chip and a manufacturing method thereof. The semiconductor LED chip comprises a transparent conductive layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a p-type contact layer, a dielectric insulating layer, an n-type contact layer, a bonding metal layer and a substrate, wherein the n-type contact layer reaches the interior of the n-type semiconductor layer or penetrates through the whole n-type semiconductor layer by virtue of through holes penetrating through each layer at the upper part of the n-type contact layer. The manufacturing method for the semiconductor LED chip comprises the following steps of manufacturing an epitaxial wafer, bonding the epitaxial wafer to another conductive or insulating substrate, removing a growing substrate, and manufacturing the transparent conductive layer on the surface of the n-type semiconductor layer. According to the semiconductor LED chip and the manufacturing method thereof, a transparent conductive layer material is adopted as a current expansion layer, so that the thickness or doping concentration of the n-type semiconductor layer is reduced, light is favorably absorbed by an n-type material, and the light extraction efficiency of the LED chip is improved.
Description
Technical field
The present invention relates to a kind of semiconductor light-emitting diode chip and preparation method thereof, belongs to semiconductor light-emitting-diode neck
Domain.
Background technology
In recent years, light emitting diode（Light emitting diode, abbreviation LED）As a kind of new type light source in society
Various fields of recent life is widely used, such as outdoor display, instrument instruction, general illumination etc..
Existing LED structure includes substrate 110, p-type semiconductor layer 111, active layer 112, n-type semiconductor layer 113, p-electrode
114 and n-electrode 115, when the applied voltage between p-electrode 114 and n-electrode 115, electric current from p-electrode 114 to n-electrode 115,
Electric light conversion is carried out in active layer 112.As shown in Figure 1.Because p, n-electrode are located at chip the same side, when causing chip operation, note
Enter that CURRENT DISTRIBUTION is uneven, affect the luminous efficiency of LED.Another kind of existing LED thin film chips, structure includes conductive substrates 120,
P-type semiconductor layer 121, active layer 122, n-type semiconductor layer 123 has a p between p-type semiconductor layer 121 and conductive substrates 120
The metallic bond coat 127 of type contact layer 126 and.P-electrode 124 and n-electrode 125 are located at the both sides of chip.When in p-electrode 124 and n
Between electrode 125 during applied voltage, electric current vertical injection active layer 122, as shown in Figure 2.Relative to the chip of Fig. 1, its electric current
Distributing homogeneity is increased.But, when high current passes through, the closer to where n-electrode 125, the electric current for flowing through is close
Degree is bigger, and CURRENT DISTRIBUTION inhomogeneities is more obvious.Above-mentioned existing chip has a common ground, is exactly required to by N-shaped half
Conductor layer is carrying out the extending transversely of electric current.This requires that n-type semiconductor layer has larger thickness（Generally more than 2 microns）With
And higher doping content（Generally higher than 1E18 is per cubic centimeter）.This brings a new problem：N-type semiconductor layer is to light
Absorb.In order to reduce the absorption of n-type semiconductor, the doping content of n-type semiconductor layer is thinning or reduction semiconductor.But individually
CURRENT DISTRIBUTION is uneven when can all reduce the conductive capability of n-type semiconductor using both approaches, and then cause chip operation, drop
Low chip light emitting efficiency.
The content of the invention
For the deficiencies in the prior art, the present invention provides a kind of semiconductor light-emitting diode chip and preparation method thereof.
Technical scheme is as follows：
A kind of semiconductor light-emitting diode chip, its structure includes successively from top to bottom transparency conducting layer, n-type semiconductor
Layer, active layer, p-type semiconductor layer, P type contact layer, dielectric insulation layer, bonding metal layer, conductive substrates, n-electrode；Wherein, institute
Transmitance of the electrically conducting transparent layer material in the wave band of the semiconductor diode chip launching light is stated more than 90%；Transparency conducting layer
It is to deposit in n-type semiconductor layer after the growth substrates of growing n-type semiconductor layer are removed；
N-contact layer is provided between dielectric insulation layer and bonding metal layer, n-contact layer is by through each layer in its top
The through n-type semiconductor layer of through hole in realize being contacted with n-type semiconductor layer, realize the electrical connection of n-electrode and n semiconductor layers；
Or the through hole is realized being contacted with transparency conducting layer through whole n-type semiconductor layer；
Chip surface has window, and p-electrode is located at window area, and p-electrode is contacted with P type contact layer, realizes p-electrode and p-type
The electrical connection of semiconductor layer.
Through hole endosexine deposition in the n-contact layer has n-contact layer material.
The n-contact layer is provided with multiple through holes.Design via count depends on chip area, further preferably described logical
The distance between hole is in 50-200 microns.The through hole is circular or square hole.Through hole bore is little luminous to reduce as best one can
The reduction of area.
The transparency conducting layer with low resistance and the characteristics of high permeability, substitute or aid in n-type semiconductor layer to enter
Row electric current and extending transversely.Preferably, the electrically conducting transparent layer material is tin indium oxide（ITO）Or zinc oxide, thickness be 50~
500 nanometers.
N-type semiconductor layer thickness is thinned to 0.5~1 micron, and than conventional more than half is reduced；The doping of n-type semiconductor layer
Concentration is that 1E17~1E19 is per cubic centimeter, and more preferably 1E17~1E18 is per cubic centimeter, than it is conventional reduce half with
On.Prior art is pressed in the thickness of other each layers and doping.
According to currently preferred, the n-type semiconductor layer and/or p-type semiconductor layer are Al, Ga, In, N quaternary material
System or Al, Ga, In, P quaternary material system.
According to currently preferred, the P type contact layer is one of Ni, Ag, Al, Ti, Au, Pt or combination.
According to currently preferred, the n-contact layer is one of Cr, Ni, Al, Au, Ge, Ti or combination.It is further excellent
Choosing, the n-contact layer is metal laminated chrome gold.
According to currently preferred, the dielectric insulation layer is silica either silicon nitride or silicon oxynitride, and thickness is
0.1~1 micron.
The method that the present invention adopts conventional epitaxial growth semi-conducting material：The epitaxial growth N-shaped half successively in growth substrates
Conductor layer, active layer, p-type semiconductor layer.The thickness of wherein n-type semiconductor layer is thinning, doping content is reduced.Structure and existing skill
Art is different.
The present invention proposes a kind of preparation method of semiconductor light-emitting diode chip, comprises the following steps：
（1）Epitaxial growth n-type semiconductor layer, active layer, p-type semiconductor layer successively in growth substrates.
（2）Multiple through holes are made on epitaxial layer by dry or wet etching technique, the depth of through hole reaches N-shaped and partly leads
Body layer completely penetrates through epitaxial layer and reaches growth substrates.
（3）P type contact layer, dielectric insulation layer, n-contact layer, bonding metal layer are made successively.By wafer bond techniques
Obtained epitaxial wafer is bonded with another conductive substrates.
（4）Growth substrates are removed by mechanical lapping, polishing, dry method or wet etch technique, exposes n-type semiconductor
Layer.N-type semiconductor layer is thinned to into 0.5~1 micron by dry etching or wet etching.
（5）Transparency conducting layer is made in n-type semiconductor layer surface.
（6）Window is made in epitaxial layer life by dry or wet etching technique, exposes P type contact layer, prepare p-electrode with
P type contact layer connects.N-electrode is prepared at the conductive substrates back side.
（7）Cutting crystal wafer, is fabricated to independent luminescence chip.
According to currently preferred, the conductive substrates are selected from conductive silicon, germanium, carborundum or metal substrate；Metal liner
The preferred copper in bottom, nickel, tungsten, or the alloy of copper, nickel, tungsten.
Such as above-mentioned step（1）The thickness of the n-type semiconductor layer of middle growth be 0.5-1 microns, above-mentioned steps（4）In thinning n
The operation of type semiconductor layer can be saved.
According to the present invention, the conductive substrates of semiconductor light-emitting diode chip are replaced with into dielectric substrate, constituted another kind of
Semiconductor light-emitting diode chip structure.
A kind of semiconductor light-emitting diode chip of dielectric substrate, its structure includes successively from top to bottom transparency conducting layer, n
Type semiconductor layer, active layer, p-type semiconductor layer, P type contact layer, dielectric insulation layer, bonding metal layer, dielectric substrate；Wherein,
Transmitance of the electrically conducting transparent layer material in the wave band of the semiconductor diode chip launching light is more than 90%；Electrically conducting transparent
Layer is deposited in n-type semiconductor layer after the growth substrates of growing n-type semiconductor layer are removed；
N-contact layer is provided between dielectric insulation layer and bonding metal layer, n-contact layer is by through each layer in its top
The through n-type semiconductor layer of through hole in realizes being contacted with n-type semiconductor layer, or the through hole is through whole n-type semiconductor layer
Realization is contacted with transparency conducting layer；
Chip surface has two windows, and one of window is p-electrode window, and p-electrode is contacted with P type contact layer, realizes p
The electrical connection of electrode and p-type semiconductor layer；Another window is n-electrode window, and making in n-contact layer has n-electrode, real
The electrical connection of existing n-electrode and n-type semiconductor layer.Preferably, p, n-electrode are located at chip the same side.
The semiconductor of the semiconductor light-emitting diode chip of above-mentioned dielectric substrate, other technical characteristics and aforesaid conductive substrate
Light-emitting diode chip for backlight unit is identical.
According to the semiconductor light-emitting diode chip of above-mentioned dielectric substrate, the present invention proposes another kind of pole of semiconductor light emitting two
The preparation method of die, comprises the following steps：
1）Epitaxial growth n-type semiconductor layer, active layer, p-type semiconductor layer successively in growth substrates.
2）Multiple through holes are made on epitaxial layer by dry or wet etching technique, the depth of through hole reaches N-shaped and partly leads
Body layer completely penetrates through epitaxial layer and reaches growth substrates.
3）P type contact layer, dielectric insulation layer, n-contact layer, bonding metal layer are made successively.By wafer bond techniques
Obtained epitaxial wafer is bonded with another dielectric substrate.
4）Growth substrates are removed by technologies such as mechanical lapping, polishing, dry method or wet etchings, exposes n-type semiconductor
Layer.N-type semiconductor layer is thinned to into 0.5~1 micron by dry etching or wet etching.
5）Transparency conducting layer is made in n-type semiconductor layer surface.
6）Two windows are made on epitaxial layer by dry or wet etching technique, n-contact layer and p-type are exposed respectively
Contact layer, prepares n-electrode in n-contact layer, and p-electrode is prepared in P type contact layer.P, n-electrode are all located in dielectric substrate
Side.
7）Cutting crystal wafer, is fabricated to independent luminescence chip.
According to currently preferred, the dielectric substrate is selected from SOI or sapphire.
Such as above-mentioned step 1）The thickness of the n-type semiconductor layer of middle growth be 0.5-1 microns, above-mentioned steps 4）In thinning N-shaped
The operation of semiconductor layer can be saved.
Beneficial effects of the present invention：
New construction LED of the present invention by transparency conducting layer with low resistance and high permeability the characteristics of, do not rely on N-shaped entirely
Semiconductor layer carries out lateral current, and using transparent conductive material the extending transversely of electric current is realized, and so just can reduce n
The thickness of type semiconductor layer reduces the doping content of n-type semiconductor layer reducing absorption of the n-type semiconductor layer to light, improves
The light extraction efficiency of chip.
The present invention another has the advantages that under identical growth rate, reduces epitaxial growth n-type semiconductor
The time of layer, epitaxial growth cost is reduced, improve the utilization ratio of epitaxial growth equipment.
The present invention another has the advantages that, reduces the gross thickness of epitaxial layer, reduces due to epitaxial growth material
Chip warpage caused by material and backing material heat adaptation, is conducive to the enforcement of the semiconductor planar chemical industry skill of large-sized wafer.
Description of the drawings
Fig. 1, Fig. 2 are respectively the schematic cross-sectional view of existing LED chip.In Fig. 1：110th, substrate；111st, p-type semiconductor layer；
112nd, active layer；113rd, n-type semiconductor layer；114th, p-electrode；115th, n-electrode.In Fig. 2：120th, conductive substrates；121st, type is partly led
Body layer；122nd, active layer；123rd, n-type semiconductor layer；124th, p-electrode；125th, n-electrode；126th, P type contact layer；127th, metal glues
Close layer.
Fig. 3 A to Fig. 3 H are the schematic cross-section of the light emitting diode manufacturing process of the embodiment of the present invention 1.
Fig. 4 is the schematic cross-section of light emitting diode prepared by embodiment 2.Fig. 5 is light emitting diode prepared by embodiment 3
Schematic cross-section.
Fig. 3 A- Fig. 3 H, Fig. 4, in Fig. 5：200th, growth substrates；210th, epitaxial layer；211st, p-type semiconductor layer；212nd, activity
Layer；213rd, n-type semiconductor layer；220th, through hole；230th, window, 240, window；300th, P type contact layer；310th, p-electrode；400th, it is situated between
Matter insulating barrier；500th, n-contact layer；510th, bonding metal layer；520th, conductive substrates；530th, n-electrode；600th, transparency conducting layer.
521st, dielectric substrate.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is further described, but not limited to this.
Embodiment 1：
A kind of semiconductor light-emitting diode chip, its structure is followed successively by from top to bottom transparency conducting layer 600, n-type semiconductor
Layer 213, active layer 212, p-type semiconductor layer 211, P type contact layer 300, dielectric insulation layer 400, the N-shaped with multiple through holes connect
Contact layer 500, bonding metal layer 510, conductive substrates 520, n-electrode 530.N-contact layer 500 runs through whole epitaxial layer 210, and saturating
Bright conductive layer 600 is contacted.Chip surface has window 230, and p-electrode 310 is located at window area, p-electrode 310 and P type contact layer
300 contacts.N-type semiconductor layer used, p-type semiconductor layer are gallium nitride（GaN）, active layer is indium gallium nitrogen（InGaN）Material.
Preparation method, comprises the following steps, as shown in Fig. 2A~2H：
The first step, as shown in Figure 3A, uses MOCVD methods grown epitaxial layer 210, the epitaxial layer in growth substrates 200
Including n-type GaN layer 213, active layer InGaN212 and p-type GaN layer 211, growth substrates 200 are carborundum；The doping of N-shaped GaN
Concentration is that 5E17 is per cubic centimeter, and thickness is 1 micron.
Second step, as shown in Figure 3 B, by the method for dry etching through hole 220, through hole 220 is made on epitaxial layer 210
Through whole epitaxial layer 210.
3rd step, as shown in Figure 3 C, on the surface of p-type semiconductor layer 211 P type contact layer 300 is prepared, and P type contact layer 300 is
Metal laminated silver/platinum
4th step, as shown in Figure 3 D, deposition medium insulating barrier 400, its material be silica, silica blanket p-type
The surface of contact layer 300 and side wall, and the side wall of the epitaxial layer of the position of through hole 200.Cover without silica in via bottoms.
5th step, as shown in FIGURE 3 E, in whole surface n-contact layer 500 and bonding metal layer 510 is sequentially depositing.N-shaped connects
Contact layer 500 is metal laminated chrome goldBonding metal layer 510 is gold-tin alloy, and thickness is 2 microns.
Structure this area derived above is referred to as epitaxial wafer.
6th step, as illustrated in Figure 3 F, by wafer bond techniques, by epitaxial wafer obtained in above-mentioned steps conduction is bonded to
On silicon substrate 520, and the method combined by mechanical lapping and dry etching removes growth substrates 200, exposes n-type GaN layer
213, and n-type GaN layer is thinned to into 0.5 micron by dry etching or wet etching.
7th step, as shown in Figure 3 G, on the surface of n-type GaN layer 213 transparency conducting layer 600 is deposited, and its material is tin indium oxide
（ITO）, thickness is
8th step, as shown in figure 3h, window 230 is made by the method for dry etching or wet etching on ITO surfaces,
Window penetrates whole epitaxial layer 210, exposes P type contact layer 300.P-electrode 310 is made in window area, is carried on the back in conductive substrates 520
Face prepares n-electrode 530, and electrode material is all metal laminated titanium/gold
9th step, cutting crystal wafer is fabricated to independent luminescence chip.
The semiconductor light-emitting diode chip of the present embodiment, after electric current enters n-electrode, can enter electric conductivity good first
N-contact layer, transparency conducting layer the inside is injected by each through hole, transparency conducting layer realizes the good horizontal expansion of electric current
Exhibition, n-type GaN layer also functions to the effect extending transversely of certain electric current, and ultimate current is uniformly injected in vertical direction InGaN work
Property layer, it is to avoid the reduction of luminous efficiency caused by current crowding benefit.The light that active layer sends upwards transmit during,
Absorption of the thin n-type semiconductor layer to light is little, is conducive to the effusion of light, improves the light extraction efficiency of chip.Relative to same
The existing chip of Fig. 2 structures of specification, the semiconductor light-emitting diode chip light extraction efficiency of the present embodiment improves more than 5%.
Embodiment 2：
As described in Example 1, except that, the depth of through hole 220 only reaches to n-type semiconductor layer middle part, such as Fig. 4 institutes
Show.Whole epitaxial layer is not run through, n-contact layer 500 is contacted with n-type semiconductor layer 213.Electrically conducting transparent layer material is zinc oxide
（ZnO）, thickness is
Comparative example：
Shown in chip structure and Fig. 4, except that, without transparency conducting layer 600.
The light extraction efficiency of the chip of the structure of embodiment 2 does not have the light extraction of the chip of transparency conducting layer compared to comparative example
Efficiency improves 8%, and voltage reduces 0.2V（Chip size is 1 square millimeter of specification, and Injection Current is 350 milliamperes）.
Embodiment 3：
As described in Example 1, except that be that conductive substrates 520 are changed to into dielectric substrate 521, dielectric substrate is indigo plant
Jewel, chip surface has two windows, and one of window 230 is p-electrode window, and p-electrode is contacted with P type contact layer, realizes p
The electrical connection of electrode and p-type semiconductor layer；Another window 240 is n-electrode window, and making in n-contact layer has n electric
Pole, realizes the electrical connection of n-electrode and n-type semiconductor layer.P, n-electrode are located at chip the same side.Structure is as shown in Figure 5.
Preparation method：
The first step is same as Example 1 to the 5th step；
6th step, by wafer bonding to dielectric substrate 521, and the side combined by mechanical lapping and dry etching
Method removes substrate 200.Expose n-type GaN layer 213 and be thinned to 0.8 micron.
7th step, it is same as Example 1.
8th step, after removing growth substrates, by dry or wet etching technique two windows is made on epitaxial layer
230th, 240, n-contact layer 500 and P type contact layer 300 are exposed respectively, n-electrode 530 is prepared in n-contact layer 500, in p-type
P-electrode 310 is prepared on contact layer 300.P, n-electrode are all located at the top of dielectric substrate 521.
9th step, with embodiment 1.
Relative to the existing chip of Fig. 1 structures of same specification, the light of the semiconductor light-emitting diode chip of the present embodiment
Extraction efficiency improves more than 10%.
Claims (9)
1. a kind of semiconductor light-emitting diode chip, its structure include successively from top to bottom transparency conducting layer, n-type semiconductor layer,
Active layer, p-type semiconductor layer, P type contact layer, dielectric insulation layer, bonding metal layer, conductive substrates, n-electrode；Wherein, it is described
Transmitance of the bright conductive in the wave band of the semiconductor diode chip launching light is more than 90%；Transparency conducting layer be
The growth substrates of growing n-type semiconductor layer are deposited in n-type semiconductor layer after removing；
N-contact layer is provided between dielectric insulation layer and bonding metal layer, n-contact layer is by through the logical of each layer in its top
Realize being contacted with n-type semiconductor layer in the through n-type semiconductor layer in hole, realize the electrical connection of n-electrode and n semiconductor layers；Or
The through hole is realized being contacted with transparency conducting layer through whole n-type semiconductor layer；
Chip surface has window, and p-electrode is located at window area, and p-electrode is contacted with P type contact layer, realizes that p-electrode and p-type are partly led
The electrical connection of body layer；
Through hole endosexine deposition in the n-contact layer has n-contact layer material；
N-type semiconductor layer thickness is thinned to 0.5~1 micron；
The doping content of n-type semiconductor layer is that 1E17 ~ 1E19 is per cubic centimeter.
2. a kind of semiconductor light-emitting diode chip of dielectric substrate, its structure includes successively from top to bottom transparency conducting layer, N-shaped
Semiconductor layer, active layer, p-type semiconductor layer, P type contact layer, dielectric insulation layer, bonding metal layer, dielectric substrate；Wherein, institute
Transmitance of the electrically conducting transparent layer material in the wave band of the semiconductor diode chip launching light is stated more than 90%；Transparency conducting layer
It is to deposit in n-type semiconductor layer after the growth substrates of growing n-type semiconductor layer are removed；
N-contact layer is provided between dielectric insulation layer and bonding metal layer, n-contact layer is by through the logical of each layer in its top
Realize being contacted with n-type semiconductor layer in the through n-type semiconductor layer in hole, or the through hole is realized through whole n-type semiconductor layer
Contact with transparency conducting layer；
Chip surface has two windows, and one of window is p-electrode window, and p-electrode is contacted with P type contact layer, realizes p-electrode
With the electrical connection of p-type semiconductor layer；Another window is n-electrode window, and making in n-contact layer has n-electrode, realizes n
The electrical connection of electrode and n-type semiconductor layer；
N-type semiconductor layer thickness is thinned to 0.5~1 micron；
The doping content of n-type semiconductor layer is that 1E17 ~ 1E19 is per cubic centimeter.
3. semiconductor light-emitting diode chip as claimed in claim 1 or 2, the n-contact layer is provided with multiple through holes, institute
The distance between through hole is stated in 50-200 microns.
4. semiconductor light-emitting diode chip as claimed in claim 1 or 2, the electrically conducting transparent layer material be tin indium oxide or
Zinc oxide, thickness is 50~500 nanometers.
5. semiconductor light-emitting diode chip as claimed in claim 1 or 2, the doping content of n-type semiconductor layer be 1E17 ~
1E18 is per cubic centimeter.
6. semiconductor light-emitting diode chip as claimed in claim 1 or 2, the P type contact layer be Ni, Ag, Al, Ti, Au,
One of Pt or combination；N-contact layer is one of Cr, Ni, Al, Au, Ge, Ti or combination.
7. semiconductor light-emitting diode chip as claimed in claim 1 or 2, the dielectric insulation layer is silica or nitridation
Silicon or silicon oxynitride, thickness is 0.1~1 micron.
8. the preparation method of semiconductor light-emitting diode chip as claimed in claim 1, comprises the following steps：
（1）Epitaxial growth n-type semiconductor layer, active layer, p-type semiconductor layer successively in growth substrates；
（2）Multiple through holes are made on epitaxial layer by dry or wet etching technique, the depth of through hole reaches n-type semiconductor layer
Or completely penetrate through epitaxial layer and reach growth substrates；
（3）P type contact layer, dielectric insulation layer, n-contact layer, bonding metal layer are made successively；Will be outer by wafer bond techniques
Prolong chip to bond with another conductive substrates；
（4）Growth substrates are removed by mechanical lapping, polishing, dry method or wet etch technique, exposes n-type semiconductor layer；It is logical
Cross dry etching or wet etching and n-type semiconductor layer is thinned to into 0.5~1 micron；
（5）Transparency conducting layer is made in n-type semiconductor layer surface；
（6）Window is made in epitaxial layer life by dry or wet etching technique, exposes P type contact layer, prepare p-electrode and p-type
Contact layer connects；N-electrode is prepared at the conductive substrates back side；
（7）Cutting crystal wafer, is fabricated to independent luminescence chip.
9. the preparation method of the semiconductor light-emitting diode chip of dielectric substrate as claimed in claim 2, comprises the following steps：
1）Epitaxial growth n-type semiconductor layer, active layer, p-type semiconductor layer successively in growth substrates；
2）Multiple through holes are made on epitaxial layer by dry or wet etching technique, the depth of through hole reaches n-type semiconductor layer
Or completely penetrate through epitaxial layer and reach growth substrates；
3）P type contact layer, dielectric insulation layer, n-contact layer, bonding metal layer are made successively；Will be outer by wafer bond techniques
Prolong piece to bond with another dielectric substrate；
4）Growth substrates are removed by technologies such as mechanical lapping, polishing, dry method or wet etchings, exposes n-type semiconductor layer；It is logical
Cross dry etching or wet etching and n-type semiconductor layer is thinned to into 0.5~1 micron；
5）Transparency conducting layer is made in n-type semiconductor layer surface；
6）Two windows are made on epitaxial layer by dry or wet etching technique, n-contact layer and p-type contact are exposed respectively
Layer, prepares n-electrode in n-contact layer, and p-electrode is prepared in P type contact layer；P, n-electrode are all located at dielectric substrate top；
7）Cutting crystal wafer, is fabricated to independent luminescence chip.
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| CN106409997A (en) * | 2016-11-23 | 2017-02-15 | 映瑞光电科技(上海)有限公司 | LED chip and formation method thereof |
| WO2018129696A1 (en) * | 2017-01-12 | 2018-07-19 | 苏州晶湛半导体有限公司 | Semiconductor component and manufacturing method therefor |
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| CN109671828B (en) * | 2018-11-30 | 2021-04-23 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer and manufacturing method thereof |
| CN109728137A (en) * | 2018-12-28 | 2019-05-07 | 映瑞光电科技(上海)有限公司 | The method and light emitting diode (LED) chip with vertical structure of LED substrate transfer |
| CN109994578B (en) * | 2019-01-09 | 2020-12-11 | 南京邮电大学 | Blue light-emitting diode with vertical structure and preparation method thereof |
| WO2020151014A1 (en) * | 2019-01-25 | 2020-07-30 | 厦门市三安光电科技有限公司 | Light-emitting diode device |
| CN109994583B (en) * | 2019-04-19 | 2020-05-01 | 厦门乾照光电股份有限公司 | High-power ultraviolet light-emitting diode and manufacturing method thereof |
| CN110265520A (en) * | 2019-07-02 | 2019-09-20 | 华南理工大学 | Optimize the embedded electrode structure LED chip and preparation method thereof of current distribution |
| CN113421953B (en) * | 2021-06-24 | 2022-12-13 | 马鞍山杰生半导体有限公司 | Deep ultraviolet light-emitting diode and manufacturing method thereof |
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