CN109994583B - High-power ultraviolet light-emitting diode and manufacturing method thereof - Google Patents

High-power ultraviolet light-emitting diode and manufacturing method thereof Download PDF

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CN109994583B
CN109994583B CN201910316241.XA CN201910316241A CN109994583B CN 109994583 B CN109994583 B CN 109994583B CN 201910316241 A CN201910316241 A CN 201910316241A CN 109994583 B CN109994583 B CN 109994583B
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layer
conductive
semiconductor layer
type semiconductor
hole
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CN109994583A (en
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林志伟
陈凯轩
卓祥景
曲晓东
蔡建九
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Xiamen Changelight Co Ltd
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Xiamen Changelight Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Abstract

The invention provides a high-power ultraviolet light-emitting diode and a manufacturing method thereof.A conductive layer is electrically connected with a first conductive semiconductor layer through the arrangement of a plurality of N-type through holes, so that the current expansion capability of the ultraviolet light-emitting diode is effectively improved; secondly, a plurality of uniformly distributed extended through holes are formed in the transparent conducting layer, so that the transparent conducting layer, the metal reflector and the second conducting type semiconductor layer form ohmic contact; meanwhile, each N-type through hole and each expansion through hole are arranged in a staggered mode in the vertical direction of the transparent conducting layer; the number of the N-type through holes can be effectively reduced while the current expansion effect is guaranteed, and active layer area loss caused by more N-type through holes is avoided.

Description

High-power ultraviolet light-emitting diode and manufacturing method thereof
Technical Field
The invention belongs to the field of light emitting diodes, and particularly relates to a high-power ultraviolet light emitting diode and a manufacturing method thereof.
Background
With the technology of the light emitting diode changing day by day, the deep ultraviolet light emitting diode is becoming a major hot technology in the light emitting diode. The deep ultraviolet light-emitting diode has wide application fields and has great application value in the fields of illumination, sterilization, medical treatment, printing, biochemical detection, high-density information storage, secret communication and the like.
In order to solve the problems that the incorporation efficiency of P-type doping is low and the incorporation efficiency of N-type doping is not high due to the fact that a deep ultraviolet light emitting diode is composed of AlGaN III-V compounds with high Al components, part of deep ultraviolet LED devices are of a vertical structure at present and are provided with a large number of N-type through holes to solve the problems. For example, patent CN105914277A discloses a flip chip type high power ultraviolet LED chip and a method for manufacturing the same, which sequentially comprises, from bottom to top, a heat conducting substrate, an electroplated metal layer, a first electroplated seed layer, an insulating layer, a p-type reflective electrode layer, a p-type gallium nitride layer, an active layer, and an n-type gallium nitride layer; etching a partial region on the upper side of the p-type reflecting electrode layer to expose the p-type reflecting electrode layer, wherein a p-type metal electrode is arranged on the exposed partial region; a plurality of n-type through holes are etched from the p-type reflecting electrode layer to the n-type gallium nitride layer, the insulating layer is deposited on the side walls of the p-type reflecting electrode layer and the n-type through holes, a first electroplating seed layer is deposited in the n-type through holes and on the insulating layer, and the first electroplating seed layer is in contact with the n-type gallium nitride layer of the n-type through holes.
However, the increased number of n-type vias results in a greater loss of active area, resulting in a lower internal quantum efficiency of the deep ultraviolet light emitting diode; the reduction in the number of through holes results in a weak current spreading effect. Therefore, the conventional deep ultraviolet light emitting diode must make a trade-off between the area loss of the active region and the current spreading effect.
In view of the above, the present inventors have specially designed a high power ultraviolet light emitting diode and a method for manufacturing the same.
Disclosure of Invention
The invention aims to provide a high-power ultraviolet light-emitting diode and a manufacturing method thereof, and in order to realize the purpose, the invention adopts the following technical scheme:
a high power ultraviolet light emitting diode comprising:
a conductive substrate having a front surface and a back surface;
a light emitting structure flip-chip bonded on the front surface of the conductive substrate through a metal bonding layer; the light emitting structure comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, a transparent conductive layer, a metal reflector, an isolation layer and a conductive layer which are sequentially stacked on the surface of a substrate; the first conductive type semiconductor layer, the active layer and the second conductive type semiconductor layer form an epitaxial layer of the ultraviolet light emitting diode; a plurality of uniformly distributed expansion through holes are formed in the transparent conducting layer, and part of the surface of the second conducting type semiconductor layer is exposed out of each expansion through hole; depositing the metal reflector on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive type semiconductor layer to form ohmic contact between the transparent conductive layer, the metal reflector and the second conductive type semiconductor layer; the metal reflector is provided with a plurality of uniformly distributed N-shaped through holes, and each N-shaped through hole penetrates through the metal reflector to at least part of the first conductive semiconductor layer; each N-type through hole and each expansion through hole are arranged along the vertical direction of the transparent conducting layer in a staggered mode; the isolation layer is deposited on the surface of the metal reflector and the side wall of each N-type through hole; the conducting layer is deposited on the surface of the isolating layer and fills the N-type through holes; the metal bonding layer is used for bonding the conductive layer and the conductive substrate;
a first electrode laminated on the opposite surface of the conductive substrate;
a second electrode laminated on a partial region of the transparent conductive layer or a partial region of the second conductive type semiconductor layer;
and the insulating layer is arranged between the side wall of the epitaxial layer and the second electrode.
Preferably, each of the N-type vias penetrates the metal mirror to a portion of the first conductive type semiconductor layer and exposes a portion of the first conductive type semiconductor layer.
Preferably, a second transparent conductive layer is arranged on one side of the first conductive type semiconductor layer, which faces away from the active layer; each N-type through hole penetrates through the metal reflector to the first conductive type semiconductor layer and exposes the surface of the second transparent conductive layer.
Preferably, a plurality of grooves are formed in the surface of the second conductive type semiconductor layer, which faces away from the active layer, and each groove forms an ion implantation region and is arranged around the periphery of each N-type through hole and away from the edge of the expansion through hole adjacent to the N-type through hole.
Preferably, at least the surface of the second conductive type semiconductor layer facing away from the active layer or the surface of the transparent conductive layer facing away from the second conductive type semiconductor layer is provided with a plurality of protrusions, and each protrusion forms a current blocking region and is arranged around the periphery of each N-type through hole and far away from the edge of the expansion through hole adjacent to the N-type through hole.
Preferably, a buffer layer is further provided between the substrate and the first conductive type semiconductor layer.
Preferably, the first conductive type semiconductor layer is an N-type semiconductor layer.
Preferably, the second conductive type semiconductor layer is a P-type semiconductor layer.
Preferably, the first electrode and the second electrode are both ITO electrodes.
The invention also provides a manufacturing method of the high-power ultraviolet light-emitting diode, which comprises the following steps:
step S1, providing a substrate, and sequentially growing a buffer layer, a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the substrate, wherein the buffer layer, the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer form an epitaxial layer of the ultraviolet light emitting diode;
step S2, growing a transparent conducting layer on the epitaxial structure;
step S3, forming a plurality of uniformly distributed expansion through holes on the transparent conducting layer through standard photoetching, masking and corrosion processes, wherein each expansion through hole exposes a part of the surface of the second conducting type semiconductor layer;
step S4, depositing a metal mirror on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive semiconductor layer to form ohmic contact between the transparent conductive layer, the metal mirror and the second conductive semiconductor layer;
step S5, forming a plurality of N-type through holes uniformly distributed on the metal reflector through standard photoetching, masking and etching processes, wherein each N-type through hole penetrates through the metal reflector to a part of the first conductive type semiconductor layer and exposes a part of the first conductive type semiconductor layer;
step S6, depositing isolation layers on the surface of the metal reflector and the side walls of the N-type through holes, and removing the insulation material contacting the first conductive type semiconductor layer of each N-type through hole;
step S7, depositing a conductive layer on the surface of the isolation layer, wherein the conductive layer fills each of the N-type through holes, and the conductive layer is electrically connected to the first conductive semiconductor layer through each of the N-type through holes;
step S8, forming a light-emitting structure after the steps;
step S9, bonding the light-emitting structure and the front surface of the conductive substrate through a metal bonding layer;
step S10, removing the substrate and the buffer layer by utilizing a laser stripping or wet etching or dry etching process for the structure;
step S11, etching and exposing a partial region of the second conductive type semiconductor layer or a partial region of the transparent conductive layer on a portion of the epitaxial layer of the structure by using a plasma technique, and forming a second electrode on the partial exposed region of the second conductive type semiconductor layer or the partial exposed region of the transparent conductive layer by using an evaporation or sputtering process; growing an insulating layer between the etched epitaxial layer side wall and the second electrode;
and step S12, forming a first electrode on the reverse side of the conductive substrate by adopting an evaporation or sputtering process.
The invention also provides another manufacturing method of the high-power ultraviolet light-emitting diode, which comprises the following steps:
step S1, providing a substrate, and sequentially growing a buffer layer, a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the substrate, wherein the buffer layer, the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer form an epitaxial layer of the ultraviolet light emitting diode;
step S2, growing a transparent conducting layer on the epitaxial structure;
step S3, forming a plurality of uniformly distributed expansion through holes on the transparent conducting layer through standard photoetching, masking and corrosion processes, wherein each expansion through hole exposes a part of the surface of the second conducting type semiconductor layer;
step S4, depositing a metal mirror on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive semiconductor layer to form ohmic contact between the transparent conductive layer, the metal mirror and the second conductive semiconductor layer;
step S5, forming a plurality of N-type through holes uniformly distributed on the metal reflector through standard photoetching, masking and corrosion processes, wherein each N-type through hole penetrates through the metal reflector to the first conductive semiconductor layer and exposes the surface of the buffer layer;
step S6, depositing isolation layers on the surface of the metal reflector and the side walls of the N-type through holes, and removing the insulation material contacting the first conductive type semiconductor layer of each N-type through hole;
step S7, depositing a conductive layer on the surface of the isolation layer, wherein the conductive layer fills each of the N-type through holes, and the conductive layer is electrically connected to the first conductive semiconductor layer through each of the N-type through holes;
step S8, forming a light-emitting structure after the steps;
step S9, bonding the light-emitting structure and the front surface of the conductive substrate through a metal bonding layer;
step S10, removing the substrate, the buffer layer, and the first conductive semiconductor layer with a certain thickness by laser lift-off, wet etching, or dry etching process;
step S11, depositing a second transparent conducting layer on the surface of the first conducting type semiconductor layer, wherein the second transparent conducting layer is electrically connected with the conducting layer in each N-type through hole;
step S12, etching and exposing a partial region of the second conductive type semiconductor layer or a partial region of the transparent conductive layer on a portion of the epitaxial layer of the structure by using a plasma technique, and forming a second electrode on the partial exposed region of the second conductive type semiconductor layer or the partial exposed region of the transparent conductive layer by using an evaporation or sputtering process; growing an insulating layer between the etched epitaxial layer side wall and the second electrode;
and step S13, forming a first electrode on the reverse side of the conductive substrate by adopting an evaporation or sputtering process.
Preferably, step S1 of the above two manufacturing methods further includes presetting N-type via through regions and extended via exposed regions on a surface of the second conductive type semiconductor layer away from the active layer; masking and etching the surface of one side, away from the active layer, of the second conductive type semiconductor layer to form a plurality of grooves, and forming ion implantation areas in the grooves through ion implantation, wherein the ion implantation areas cover the N-type through hole penetrating areas and extend outwards; the radius of the ion implantation area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposure area adjacent to the expanded through hole.
Preferably, step S1 of the above two manufacturing methods further includes presetting N-type via through regions and extended via exposed regions on a surface of the second conductive type semiconductor layer away from the active layer; after a dielectric layer is evaporated on the surface of one side, away from the active layer, of the second conductive type semiconductor layer, photoresist is removed and stripping is carried out to form a plurality of current blocking regions, and each current blocking region covers each N-type through hole penetrating region and extends outwards; the radius of the current blocking area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposed area adjacent to the extended through hole. Preferably, step S2 of the above two manufacturing methods further includes presetting N-type via penetrating regions and extended via penetrating regions on a surface of the transparent conductive layer away from the second conductive type semiconductor layer; after a dielectric layer is evaporated on the surface of one side, away from the second conductive semiconductor layer, of the transparent conductive layer, photoresist is removed and the transparent conductive layer is stripped to form a plurality of current blocking regions, and each current blocking region covers each N-type through hole penetrating region and extends outwards; the radius of the current blocking area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposed area adjacent to the extended through hole.
According to the technical scheme, firstly, the metal reflector is provided with a plurality of uniformly distributed N-shaped through holes, each N-shaped through hole penetrates through the metal reflector at least to part of the first conductive type semiconductor layer, and the isolation layer is deposited on the surface of the metal reflector and the side wall of each N-shaped through hole; the conducting layer is deposited on the surface of the isolating layer and fills the N-type through holes; through the arrangement of the N-type through holes, the conductive layer is electrically connected with the first conductive type semiconductor layer, and the current expansion capability of the ultraviolet light-emitting diode is effectively improved; secondly, a plurality of uniformly distributed expansion through holes are formed in the transparent conducting layer, and part of the surface of the second conducting type semiconductor layer is exposed out of each expansion through hole; depositing the metal reflector on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive type semiconductor layer to form ohmic contact between the transparent conductive layer, the metal reflector and the second conductive type semiconductor layer; meanwhile, each N-type through hole and each expansion through hole are arranged in a staggered mode in the vertical direction of the transparent conducting layer; the number of the N-type through holes can be effectively reduced while the current expansion effect is guaranteed, and active layer area loss caused by more N-type through holes is avoided.
In addition, an ion implantation area is formed on the surface, away from the active layer, of the second conduction type semiconductor layer, and the ion implantation area surrounds the edge, distributed on the periphery of each N-type through hole, of the expansion through hole far away from the adjacent N-type through hole; or forming a current blocking region on at least the surface of the second conductive type semiconductor layer, which is far away from the active layer, or the surface of the transparent conductive layer, which is far away from the second conductive type semiconductor layer, wherein the current blocking region surrounds the edge of the expansion through hole which is arranged at the periphery of each N-type through hole and is far away from the adjacent N-type through hole. Certain current blocking is formed, N-type current is guided to be distributed around the expansion through hole, and the current expansion capability of the chip is further improved, so that the light emitting efficiency of the ultraviolet light emitting diode is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an ultraviolet light emitting diode provided in embodiment 1 of the present invention;
FIG. 2 is a schematic cross-sectional view of the UV LED shown in FIG. 1 along line AA;
fig. 3.1 to fig. 3.11 are schematic structural diagrams corresponding to the method for manufacturing the ultraviolet light emitting diode shown in embodiment 1;
fig. 4 is another schematic structural diagram of an ultraviolet light emitting diode provided in embodiment 2 of the present invention;
FIG. 5 is a schematic cross-sectional view of the UV LED shown in FIG. 4 along line AA;
fig. 6.1 to 6.11 are schematic structural diagrams corresponding to the method for manufacturing the ultraviolet light emitting diode shown in embodiment 2;
fig. 7 is another schematic structural diagram of the ultraviolet light emitting diode provided in this embodiment 3;
FIG. 8 is a schematic cross-sectional view of the UV LED shown in FIG. 7 along line AA;
fig. 9.1 to 9.11 are schematic structural diagrams corresponding to the method for manufacturing the ultraviolet light emitting diode shown in embodiment 3;
fig. 10 is another schematic structural diagram of the ultraviolet light emitting diode provided in this embodiment 4;
FIG. 11 is a schematic cross-sectional view of the UV LED shown in FIG. 10 along line AA;
fig. 12.1 to 12.11 are schematic structural diagrams corresponding to the method for manufacturing the ultraviolet light emitting diode shown in embodiment 4;
the symbols in the drawings illustrate that: 101. the semiconductor device comprises a substrate, 102, a buffer layer, 103, a first conductive type semiconductor layer, 104, an active layer, 105, a second conductive type semiconductor layer, 106, a transparent conductive layer, 107, a metal mirror, 108, an isolation layer, 109, a conductive layer, 110, a metal bonding layer, 111, a conductive substrate, 112, an N-type through hole, 113, an extended through hole, 114, a first electrode, 115, a second electrode, 116, an insulation layer, 117, a second transparent conductive layer, 118, an ion implantation region, 119 and a current blocking region.
Detailed Description
For the clarity of the disclosure, the following description will be made with reference to the accompanying drawings. The invention is not limited to this specific embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The embodiment provides a high-power ultraviolet light-emitting diode, as shown in fig. 1 and 2, comprising a conductive substrate 111 having a front surface and a back surface; a light emitting structure flip-chip bonded on the front surface of the conductive substrate 111 through the metal bonding layer 110; the light emitting structure includes a first conductive type semiconductor layer 103, an active layer 104, a second conductive type semiconductor layer 105, a transparent conductive layer 106, a metal mirror 107, an isolation layer 108, and a conductive layer 109 stacked in this order on a surface of a substrate 101; the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 constitute an epitaxial layer of the ultraviolet light emitting diode; a plurality of uniformly distributed expanded through holes 113 are formed in the transparent conductive layer 106, and each expanded through hole 113 exposes a part of the surface of the second conductive type semiconductor layer 105; depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact; the metal reflector 107 is provided with a plurality of evenly distributed N-type through holes 112, each N-type through hole 112 penetrates through the metal reflector 107 to a part of the first conductive type semiconductor layer 103 and exposes a part of the first conductive type semiconductor layer 103; each N-type through hole 112 and each expansion through hole 113 are arranged along the vertical direction of the transparent conducting layer 106 in a staggered mode; the isolation layer 108 is deposited on the surface of the metal reflector 107 and the sidewall of each N-type via 112; a conductive layer 109 is deposited on the surface of the isolation layer 108 and fills each N-type via 112; the metal bonding layer 110 is used for bonding the conductive layer 109 and the conductive substrate 111;
a first electrode 114 laminated on the opposite surface of the conductive substrate 111;
a second electrode 115 laminated on a partial region of the transparent conductive layer 106;
and an insulating layer 116 disposed between the epitaxial layer sidewalls and the second electrode 115.
The surface of the second conductive type semiconductor layer 105 away from the active layer 104 is provided with a plurality of grooves, each of which forms an ion implantation region 118 and is disposed around the periphery of each N-type via 112 and away from the edge of the extended via 113 adjacent to the N-type via 112.
A buffer layer 102 is further provided between the substrate 101 and the first conductive type semiconductor layer 103.
The first conductive type semiconductor layer 103 is an N-type semiconductor layer.
The second conductive type semiconductor layer 105 is a P-type semiconductor layer.
The first electrode 114 and the second electrode 115 are ITO electrodes.
As shown in fig. 3.1 to fig. 3.11, the method for manufacturing a high-power ultraviolet light emitting diode provided by this embodiment includes the following steps:
step S1, providing a substrate 101, sequentially growing a buffer layer 102, a first conductive type semiconductor layer 103, an active layer 104, and a second conductive type semiconductor layer 105 on the substrate 101, wherein the buffer layer 102, the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 form an epitaxial layer of the ultraviolet light emitting diode, and a surface of the second conductive type semiconductor layer 105 away from the active layer 104 is provided with a penetrating region of each N-type via 112 and an exposed region of each extended via 113; masking and etching the surface of the second conductive type semiconductor layer 105, which is away from the active layer 104, to form a plurality of grooves, and forming ion implantation regions 118 in the grooves by ion implantation, wherein each ion implantation region 118 covers the penetrating region of each N-type through hole 112 and extends outwards; the radius of the ion implantation region 118 does not exceed the shortest distance from the center of the penetrating region of the N-type through hole 112 to the edge of the exposed region adjacent to the expanded through hole 113;
step S2, growing a transparent conductive layer 106 on the epitaxial structure;
step S3, forming a plurality of uniformly distributed expansion vias 113 on the transparent conductive layer 106 through standard photolithography, masking, and etching processes, wherein each expansion via 113 exposes a portion of the surface of the second conductive semiconductor layer 105;
step S4, depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact;
step S5, forming a plurality of N-type through holes 112 uniformly distributed on the metal mirror 107 by standard photolithography, masking and etching processes, wherein each N-type through hole 112 penetrates through the metal mirror 107 to a portion of the first conductive type semiconductor layer 103 and exposes a portion of the first conductive type semiconductor layer 103;
step S6, depositing an isolation layer 108 on the surface of the metal mirror 107 and the sidewalls of the N-type vias 112, and removing the insulation material of the N-type vias 112 contacting the first conductive type semiconductor layer 103;
step S7, depositing a conductive layer 109 on the surface of the isolation layer 108, wherein the conductive layer 109 fills each N-type via 112, and the conductive layer 109 is electrically connected to the first conductive type semiconductor layer 103 through each N-type via 112;
step S8, forming a light-emitting structure after the steps;
step S9, forming a bond between the light emitting structure and the front surface of the conductive substrate 111 through the metal bonding layer 110;
step S10, removing the substrate 101 and the buffer layer 102 by using laser lift-off or wet etching or dry etching process for the structure;
step S11, etching a partial region of the exposed transparent conductive layer 106 on a partial epitaxial layer of the structure by using a plasma technique, and forming a second electrode 115 on the partial exposed region of the transparent conductive layer 106 by using an evaporation or sputtering process; and an insulating layer 116 is grown between the etched epitaxial layer sidewall and the second electrode 115;
in step S12, a first electrode 114 is formed on the reverse side of the conductive substrate 111 by evaporation or sputtering.
Example 2
The present embodiment provides another high power ultraviolet led, as shown in fig. 4 and 5, which includes a conductive substrate 111 having a front surface and a back surface; a light emitting structure flip-chip bonded on the front surface of the conductive substrate 111 through the metal bonding layer 110; the light emitting structure includes a first conductive type semiconductor layer 103, an active layer 104, a second conductive type semiconductor layer 105, a transparent conductive layer 106, a metal mirror 107, an isolation layer 108, and a conductive layer 109 stacked in this order on a surface of a substrate 101; the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 constitute an epitaxial layer of the ultraviolet light emitting diode; a plurality of uniformly distributed expanded through holes 113 are formed in the transparent conductive layer 106, and each expanded through hole 113 exposes a part of the surface of the second conductive type semiconductor layer 105; depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact; the metal reflector 107 is provided with a plurality of evenly distributed N-type through holes 112, and each N-type through hole 112 penetrates through the metal reflector 107 to the first conductive type semiconductor layer 103 and exposes the surface of the second transparent conductive layer 117; a second transparent conductive layer 117 is provided on a side of the first conductive type semiconductor layer 103 facing away from the active layer 104; each N-type through hole 112 and each expansion through hole 113 are arranged along the vertical direction of the transparent conducting layer 106 in a staggered mode; the isolation layer 108 is deposited on the surface of the metal reflector 107 and the sidewall of each N-type via 112; a conductive layer 109 is deposited on the surface of the isolation layer 108 and fills each N-type via 112; the metal bonding layer 110 is used for bonding the conductive layer 109 and the conductive substrate 111;
a first electrode 114 laminated on the opposite surface of the conductive substrate 111;
a second electrode 115 laminated on a partial region of the transparent conductive layer 106;
and an insulating layer 116 disposed between the epitaxial layer sidewalls and the second electrode 115.
A plurality of grooves are formed in the surface, away from the active layer, of the second conductive type semiconductor layer 105; each groove forms an ion implantation region 118 and is arranged around the periphery of each N-type through hole 112 and away from the edge of the expansion through hole 113 adjacent to the N-type through hole 112.
A buffer layer 102 is further provided between the substrate 101 and the first conductive type semiconductor layer 103.
The first conductive type semiconductor layer 103 is an N-type semiconductor layer.
The second conductive type semiconductor layer 105 is a P-type semiconductor layer.
The first electrode 114 and the second electrode 115 are ITO electrodes.
As shown in fig. 6.1 to 6.11, the method for manufacturing a high-power ultraviolet light emitting diode provided by this embodiment includes the following steps:
step S1, providing a substrate 101, and sequentially growing a buffer layer 102, a first conductive type semiconductor layer 103, an active layer 104, and a second conductive type semiconductor layer 105 on the substrate 101, wherein the buffer layer 102, the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 form an epitaxial layer of the ultraviolet light emitting diode; presetting penetrating areas of the N-type through holes 112 and exposed areas of the extended through holes 113 on the surface of the second conductive type semiconductor layer 105, which is far away from the active layer 104; masking and etching the surface of the second conductive type semiconductor layer 105, which is away from the active layer 104, to form a plurality of grooves, and forming ion implantation regions 118 in the grooves by ion implantation, wherein each ion implantation region 118 covers the penetrating region of each N-type through hole 112 and extends outwards; the radius of the ion implantation region 118 does not exceed the shortest distance from the center of the penetrating region of the N-type through hole 112 to the edge of the exposed region adjacent to the expanded through hole 113;
step S2, growing a transparent conductive layer 106 on the epitaxial structure;
step S3, forming a plurality of uniformly distributed expansion vias 113 on the transparent conductive layer 106 through standard photolithography, masking, and etching processes, wherein each expansion via 113 exposes a portion of the surface of the second conductive semiconductor layer 105;
step S4, depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact;
step S5, forming a plurality of N-type through holes 112 uniformly distributed on the metal mirror 107 by standard photolithography, masking, and etching processes, wherein each N-type through hole 112 penetrates through the metal mirror 107 to the first conductive semiconductor layer 103 and exposes the surface of the buffer layer 102;
step S6, depositing an isolation layer 108 on the surface of the metal mirror 107 and the sidewalls of the N-type vias 112, and removing the insulation material of the N-type vias 112 contacting the first conductive type semiconductor layer 103;
step S7, depositing a conductive layer 109 on the surface of the isolation layer 108, wherein the conductive layer 109 fills each N-type via 112, and the conductive layer 109 is electrically connected to the first conductive type semiconductor layer 103 through each N-type via 112;
step S8, forming a light-emitting structure after the steps;
step S9, forming a bond between the light emitting structure and the front surface of the conductive substrate 111 through the metal bonding layer 110;
step S10, removing the substrate 101, the buffer layer 102, and the first conductive type semiconductor layer 103 with a certain thickness by laser lift-off, wet etching, or dry etching process for the above structure;
step S11, depositing a second transparent conductive layer 117 on the surface of the first conductive semiconductor layer 103, wherein the second transparent conductive layer 117 is electrically connected to the conductive layer in each N-type via 112;
step S12, etching a partial region of the exposed transparent conductive layer 106 on a partial epitaxial layer of the structure by using a plasma technique, and forming a second electrode 115 on the partial exposed region of the transparent conductive layer 106 by using an evaporation or sputtering process; and an insulating layer 116 is grown between the etched epitaxial layer sidewall and the second electrode 115;
in step S13, a first electrode 114 is formed on the reverse side of the conductive substrate 111 by evaporation or sputtering.
Example 3
The present embodiment provides another high power ultraviolet led, as shown in fig. 7 and 8, which includes a conductive substrate 111 having a front surface and a back surface; a light emitting structure flip-chip bonded on the front surface of the conductive substrate 111 through the metal bonding layer 110; the light emitting structure includes a first conductive type semiconductor layer 103, an active layer 104, a second conductive type semiconductor layer 105, a transparent conductive layer 106, a metal mirror 107, an isolation layer 108, and a conductive layer 109 stacked in this order on a surface of a substrate 101; the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 constitute an epitaxial layer of the ultraviolet light emitting diode; a plurality of uniformly distributed expanded through holes 113 are formed in the transparent conductive layer 106, and each expanded through hole 113 exposes a part of the surface of the second conductive type semiconductor layer 105; depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact; the metal reflector 107 is provided with a plurality of evenly distributed N-type through holes 112, each N-type through hole 112 penetrates through the metal reflector 107 to a part of the first conductive type semiconductor layer 103 and exposes a part of the first conductive type semiconductor layer 103; each N-type through hole 112 and each expansion through hole 113 are arranged along the vertical direction of the transparent conducting layer 106 in a staggered mode; the isolation layer 108 is deposited on the surface of the metal reflector 107 and the sidewall of each N-type via 112; a conductive layer 109 is deposited on the surface of the isolation layer 108 and fills each N-type via 112; the metal bonding layer 110 is used for bonding the conductive layer 109 and the conductive substrate 111;
a first electrode 114 laminated on the opposite surface of the conductive substrate 111;
a second electrode 115 laminated on a partial region of the transparent conductive layer 106;
and an insulating layer 116 disposed between the epitaxial layer sidewalls and the second electrode 115.
A plurality of protrusions are arranged on the surface of the transparent conductive layer 106, which is far away from the second conductive type semiconductor layer 105, and the surface of the second conductive type semiconductor layer 105, which is far away from the active layer 104; each protrusion forms a current blocking region 119 and is disposed around the periphery of each N-type via 112 and away from the edge of the extended via 113 adjacent to the N-type via 112.
A buffer layer 102 is further provided between the substrate 101 and the first conductive type semiconductor layer 103.
The first conductive type semiconductor layer 103 is an N-type semiconductor layer.
The second conductive type semiconductor layer 105 is a P-type semiconductor layer.
The first electrode 114 and the second electrode 115 are ITO electrodes.
As shown in fig. 9.1 to 9.11, the method for manufacturing a high-power ultraviolet light emitting diode provided by this embodiment includes the following steps:
step S1, providing a substrate 101, and sequentially growing a buffer layer 102, a first conductive type semiconductor layer 103, an active layer 104, and a second conductive type semiconductor layer 105 on the substrate 101, wherein the buffer layer 102, the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 form an epitaxial layer of the ultraviolet light emitting diode; presetting penetrating areas of the N-type through holes 112 and exposed areas of the extended through holes 113 on the surface of the second conductive type semiconductor layer 105, which is far away from the active layer 104; after a dielectric layer is evaporated on the surface of one side, away from the active layer 104, of the second conductive type semiconductor layer 105, photoresist is removed and a plurality of current blocking regions 119 are formed, and each current blocking region 119 covers each penetrating region of the N-type through hole 112 and extends outwards; the radius of the current blocking region 119 does not exceed the shortest distance from the center of the penetrating region of the N-type through hole 112 to the edge of the exposed region adjacent to the expanded through hole 113;
step S2, growing a transparent conductive layer 106 on the epitaxial structure, performing evaporation on the dielectric layer on the surface of the side of the transparent conductive layer 106 away from the second conductive semiconductor layer 105, removing the photoresist and stripping to form a plurality of current blocking regions 119, wherein each current blocking region 119 covers each penetrating region of the N-type through hole 112 and extends outward; the radius of the current blocking region 119 does not exceed the shortest distance from the center of the penetrating region of the N-type through hole 112 to the edge of the exposed region adjacent to the expanded through hole 113;
step S3, forming a plurality of uniformly distributed expansion vias 113 on the transparent conductive layer 106 through standard photolithography, masking, and etching processes, wherein each expansion via 113 exposes a portion of the surface of the second conductive semiconductor layer 105;
step S4, depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact;
step S5, forming a plurality of N-type through holes 112 uniformly distributed on the metal mirror 107 by standard photolithography, masking and etching processes, wherein each N-type through hole 112 penetrates through the metal mirror 107 to a portion of the first conductive type semiconductor layer 103 and exposes a portion of the first conductive type semiconductor layer 103;
step S6, depositing an isolation layer 108 on the surface of the metal mirror 107 and the sidewalls of the N-type vias 112, and removing the insulation material of the N-type vias 112 contacting the first conductive type semiconductor layer 103;
step S7, depositing a conductive layer 109 on the surface of the isolation layer 108, wherein the conductive layer 109 fills each N-type via 112, and the conductive layer 109 is electrically connected to the first conductive type semiconductor layer 103 through each N-type via 112;
step S8, forming a light-emitting structure after the steps;
step S9, forming a bond between the light emitting structure and the front surface of the conductive substrate 111 through the metal bonding layer 110;
step S10, removing the substrate 101 and the buffer layer 102 by using laser lift-off or wet etching or dry etching process for the structure;
step S11, etching a partial region of the exposed transparent conductive layer 106 on a partial epitaxial layer of the structure by using a plasma technique, and forming a second electrode 115 on the partial exposed region of the transparent conductive layer 106 by using an evaporation or sputtering process; and an insulating layer 116 is grown between the etched epitaxial layer sidewall and the second electrode 115;
in step S12, a first electrode 114 is formed on the reverse side of the conductive substrate 111 by evaporation or sputtering.
Example 4
The present embodiment provides another high power ultraviolet led, as shown in fig. 10 and 11, which includes a conductive substrate 111 having a front surface and a back surface; a light emitting structure flip-chip bonded on the front surface of the conductive substrate 111 through the metal bonding layer 110; the light emitting structure includes a first conductive type semiconductor layer 103, an active layer 104, a second conductive type semiconductor layer 105, a transparent conductive layer 106, a metal mirror 107, an isolation layer 108, and a conductive layer 109 stacked in this order on a surface of a substrate 101; the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 constitute an epitaxial layer of the ultraviolet light emitting diode; a plurality of uniformly distributed expanded through holes 113 are formed in the transparent conductive layer 106, and each expanded through hole 113 exposes a part of the surface of the second conductive type semiconductor layer 105; depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact; the metal reflector 107 is provided with a plurality of evenly distributed N-type through holes 112, and each N-type through hole 112 penetrates through the metal reflector 107 to the first conductive type semiconductor layer 103 and exposes the surface of the second transparent conductive layer 117; a second transparent conductive layer 117 is provided on a side of the first conductive type semiconductor layer 103 facing away from the active layer 104; each N-type through hole 112 and each expansion through hole 113 are arranged along the vertical direction of the transparent conducting layer 106 in a staggered mode; the isolation layer 108 is deposited on the surface of the metal reflector 107 and the sidewall of each N-type via 112; a conductive layer 109 is deposited on the surface of the isolation layer 108 and fills each N-type via 112; the metal bonding layer 110 is used for bonding the conductive layer 109 and the conductive substrate 111;
a first electrode 114 laminated on the opposite surface of the conductive substrate 111;
a second electrode 115 laminated on a partial region of the transparent conductive layer 106;
and an insulating layer 116 disposed between the epitaxial layer sidewalls and the second electrode 115.
A plurality of protrusions are arranged on the surface of the transparent conductive layer 106, which is far away from the second conductive type semiconductor layer 105, and the surface of the second conductive type semiconductor layer 105, which is far away from the active layer 104; each protrusion forms a current blocking region 119 and is disposed around the periphery of each N-type via 112 and away from the edge of the extended via 113 adjacent to the N-type via 112.
A buffer layer 102 is further provided between the substrate 101 and the first conductive type semiconductor layer 103.
The first conductive type semiconductor layer 103 is an N-type semiconductor layer.
The second conductive type semiconductor layer 105 is a P-type semiconductor layer.
The first electrode 114 and the second electrode 115 are ITO electrodes.
As shown in fig. 12.1 to 12.11, the method for manufacturing a high-power ultraviolet light emitting diode provided by this embodiment includes the following steps:
step S1, providing a substrate 101, and sequentially growing a buffer layer 102, a first conductive type semiconductor layer 103, an active layer 104, and a second conductive type semiconductor layer 105 on the substrate 101, wherein the buffer layer 102, the first conductive type semiconductor layer 103, the active layer 104, and the second conductive type semiconductor layer 105 form an epitaxial layer of the ultraviolet light emitting diode; presetting penetrating areas of the N-type through holes 112 and exposed areas of the extended through holes 113 on the surface of the second conductive type semiconductor layer 105, which is far away from the active layer 104; after a dielectric layer is evaporated on the surface of one side, away from the active layer 104, of the second conductive type semiconductor layer 105, photoresist is removed and a plurality of current blocking regions 119 are formed, and each current blocking region 119 covers each penetrating region of the N-type through hole 112 and extends outwards; the radius of the current blocking region 119 does not exceed the shortest distance from the center of the penetrating region of the N-type through hole 112 to the edge of the exposed region adjacent to the expanded through hole 113;
step S2, growing a transparent conductive layer 106 on the epitaxial structure, performing evaporation on the dielectric layer on the surface of the side of the transparent conductive layer 106 away from the second conductive semiconductor layer 105, removing the photoresist and stripping to form a plurality of current blocking regions 119, wherein each current blocking region 119 covers each penetrating region of the N-type through hole 112 and extends outward; the radius of the current blocking region 119 does not exceed the shortest distance from the center of the penetrating region of the N-type through hole 112 to the edge of the exposed region adjacent to the expanded through hole 113;
step S3, forming a plurality of uniformly distributed expansion vias 113 on the transparent conductive layer 106 through standard photolithography, masking, and etching processes, wherein each expansion via 113 exposes a portion of the surface of the second conductive semiconductor layer 105;
step S4, depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact;
step S5, forming a plurality of N-type through holes 112 uniformly distributed on the metal mirror 107 by standard photolithography, masking, and etching processes, wherein each N-type through hole 112 penetrates through the metal mirror 107 to the first conductive semiconductor layer 103 and exposes the surface of the buffer layer 102;
step S6, depositing an isolation layer 108 on the surface of the metal mirror 107 and the sidewalls of the N-type vias 112, and removing the insulation material of the N-type vias 112 contacting the first conductive type semiconductor layer 103;
step S7, depositing a conductive layer 109 on the surface of the isolation layer 108, wherein the conductive layer 109 fills each N-type via 112, and the conductive layer 109 is electrically connected to the first conductive type semiconductor layer 103 through each N-type via 112;
step S8, forming a light-emitting structure after the steps;
step S9, forming a bond between the light emitting structure and the front surface of the conductive substrate 111 through the metal bonding layer 110;
step S10, removing the substrate 101, the buffer layer 102, and the first conductive type semiconductor layer 103 with a certain thickness by laser lift-off, wet etching, or dry etching process for the above structure;
step S11, depositing a second transparent conductive layer 117 on the surface of the first conductive semiconductor layer 103, wherein the second transparent conductive layer 117 is electrically connected to the conductive layer in each N-type via 112;
step S12, etching a partial region of the exposed transparent conductive layer 106 on a partial epitaxial layer of the structure by using a plasma technique, and forming a second electrode 115 on the partial exposed region of the transparent conductive layer 106 by using an evaporation or sputtering process; and an insulating layer 116 is grown between the etched epitaxial layer sidewall and the second electrode 115;
in step S13, a first electrode 114 is formed on the reverse side of the conductive substrate 111 by evaporation or sputtering.
In addition, examples 3 and 4 of the present specification disclose: meanwhile, a current blocking region 119 is provided on a surface of the second conductive type semiconductor layer 105 facing away from the active layer 104 and on a surface of the transparent conductive layer 106 facing away from the second conductive type semiconductor layer 105; in some modified embodiments, the current blocking region 119 may be disposed only on the surface of the second conductive type semiconductor layer 105 facing away from the active layer 104, or the current blocking region 119 may be disposed only on the surface of the transparent conductive layer 106 facing away from the second conductive type semiconductor layer 105, and the specific structure and manufacturing method thereof can refer to embodiments 3 and 4.
In summary, the embodiment of the present application provides a high power ultraviolet light emitting diode and a method for manufacturing the same, first, a plurality of N-type through holes 112 are uniformly distributed on a metal reflector 107, each N-type through hole 112 penetrates through the metal reflector 107 to at least a portion of a first conductive type semiconductor layer 103, and an isolation layer 108 is deposited on the surface of the metal reflector 107 and the sidewall of each N-type through hole 112; a conductive layer 109 is deposited on the surface of the isolation layer 108 and fills each N-type via 112; through the arrangement of the N-type through holes 112, the conductive layer 109 is electrically connected with the first conductive type semiconductor layer 103, so that the current expansion capability of the ultraviolet light emitting diode is effectively improved; secondly, a plurality of uniformly distributed extended through holes 113 are formed in the transparent conductive layer 106, and each extended through hole 113 exposes a part of the surface of the second conductive type semiconductor layer 105; depositing a metal mirror 107 on the surface of the transparent conductive layer 106 and the exposed surface of the second conductive type semiconductor layer 105, so that the transparent conductive layer 106, the metal mirror 107 and the second conductive type semiconductor layer 105 form ohmic contact; meanwhile, each N-type through hole 112 and each extended through hole 113 are arranged along the vertical direction of the transparent conductive layer 106 in a staggered manner; the number of the N-type through holes 112 can be effectively reduced while the current spreading effect is ensured, and the area loss of the active layer 104 caused by more N-type through holes 112 is avoided.
In addition, by forming the ion implantation region 118 on the surface of the second conductive type semiconductor layer 105 away from the active layer 104, the ion implantation region 118 surrounds the edge of the extended via 113 which is arranged at the periphery of each N-type via 112 and is far away from the adjacent N-type via 112; or by forming a current blocking region 119 at least on a surface of the second conductive type semiconductor layer 105 facing away from the active layer 104 or a surface of the transparent conductive layer 106 facing away from the second conductive type semiconductor layer 105, the current blocking region 119 surrounds an edge of the extended via 113 disposed at the periphery of each N-type via 112 and away from the N-type via 112. Certain current blocking is formed, and N-type current is guided to be distributed around the expansion through hole 113, so that the current expansion capability of the chip is further improved, and the light emitting efficiency of the ultraviolet light emitting diode is improved.
The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications thereof by those skilled in the art should be considered as not departing from the scope of the present invention.

Claims (13)

1. A high power ultraviolet light emitting diode comprising:
a conductive substrate having a front surface and a back surface;
a light emitting structure flip-chip bonded on the front surface of the conductive substrate through a metal bonding layer; the light emitting structure comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, a transparent conductive layer, a metal reflector, an isolation layer and a conductive layer which are sequentially stacked; the first conductive type semiconductor layer, the active layer and the second conductive type semiconductor layer form an epitaxial layer of the ultraviolet light emitting diode; a plurality of uniformly distributed expansion through holes are formed in the transparent conducting layer, and part of the surface of the second conducting type semiconductor layer is exposed out of each expansion through hole; depositing the metal reflector on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive semiconductor layer; the metal reflector is provided with a plurality of uniformly distributed N-shaped through holes, and each N-shaped through hole penetrates through the metal reflector to at least part of the first conductive semiconductor layer; each N-type through hole and each expansion through hole are arranged along the vertical direction of the transparent conducting layer in a staggered mode; the isolation layer is deposited on the surface of the metal reflector and the side wall of each N-type through hole; the conducting layer is deposited on the surface of the isolating layer and fills the N-type through holes; the metal bonding layer is used for bonding the conductive layer and the conductive substrate;
a first electrode laminated on the opposite surface of the conductive substrate;
a second electrode laminated on a partial region of the transparent conductive layer or a partial region of the second conductive type semiconductor layer;
and the insulating layer is arranged between the side wall of the epitaxial layer and the second electrode.
2. The high power ultraviolet light emitting diode of claim 1, wherein: each N-type through hole penetrates through the metal reflector to a part of the first conductive type semiconductor layer, and a part of the first conductive type semiconductor layer is exposed.
3. The high power ultraviolet light emitting diode of claim 1, wherein: a second transparent conducting layer is arranged on one side, away from the active layer, of the first conducting type semiconductor layer; each N-type through hole penetrates through the metal reflector to the first conductive type semiconductor layer and exposes the surface of the second transparent conductive layer.
4. The high power ultraviolet light emitting diode of claim 1, wherein: a plurality of grooves are formed in the surface, away from the active layer, of the second conductive type semiconductor layer; each groove forms an ion implantation area and is arranged around the periphery of each N-type through hole and far away from the edge of the expansion through hole adjacent to the N-type through hole.
5. The high power ultraviolet light emitting diode of claim 1, wherein: at least the surface of the second conductive type semiconductor layer, which is far away from the active layer, or the surface of the transparent conductive layer, which is far away from the second conductive type semiconductor layer, is provided with a plurality of bulges; each bulge forms a current blocking area and is arranged around the periphery of each N-shaped through hole and far away from the edge of the expansion through hole adjacent to the N-shaped through hole.
6. A manufacturing method of a high-power ultraviolet light-emitting diode, which is used for preparing the high-power ultraviolet light-emitting diode as claimed in any one of claims 1 and 2, and is characterized by comprising the following steps:
step S1, providing a substrate, and sequentially growing a buffer layer, a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the substrate, wherein the buffer layer, the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer form an epitaxial layer of the ultraviolet light emitting diode;
step S2, growing a transparent conducting layer on the epitaxial structure;
step S3, forming a plurality of uniformly distributed expansion through holes on the transparent conducting layer through standard photoetching, masking and corrosion processes, wherein each expansion through hole exposes a part of the surface of the second conducting type semiconductor layer;
step S4, depositing a metal mirror on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive semiconductor layer;
step S5, forming a plurality of N-type through holes uniformly distributed on the metal reflector through standard photoetching, masking and etching processes, wherein each N-type through hole penetrates through the metal reflector to a part of the first conductive type semiconductor layer and exposes a part of the first conductive type semiconductor layer;
step S6, depositing isolation layers on the surface of the metal reflector and the side walls of the N-type through holes, and removing the insulation material contacting the first conductive type semiconductor layer of each N-type through hole;
step S7, depositing a conductive layer on the surface of the isolation layer, wherein the conductive layer fills each N-type through hole;
step S8, forming a light-emitting structure after the steps;
step S9, bonding the light-emitting structure and the front surface of the conductive substrate through a metal bonding layer;
step S10, removing the substrate and the buffer layer by utilizing a laser stripping or wet etching or dry etching process for the structure;
step S11, etching and exposing a partial region of the second conductive type semiconductor layer or a partial region of the transparent conductive layer on a portion of the epitaxial layer of the structure by using a plasma technique, and forming a second electrode on the partial exposed region of the second conductive type semiconductor layer or the partial exposed region of the transparent conductive layer by using an evaporation or sputtering process; growing an insulating layer between the etched epitaxial layer side wall and the second electrode;
and step S12, forming a first electrode on the reverse side of the conductive substrate by adopting an evaporation or sputtering process.
7. The method as claimed in claim 6, wherein the step S1 further includes presetting N-type via through regions and extended via exposed regions on a surface of the second conductive type semiconductor layer away from the active layer; masking and etching the surface of one side, away from the active layer, of the second conductive type semiconductor layer to form a plurality of grooves, and forming ion implantation areas in the grooves through ion implantation, wherein the ion implantation areas cover the N-type through hole penetrating areas and extend outwards; the radius of the ion implantation area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposure area adjacent to the expanded through hole.
8. The method as claimed in claim 6, wherein the step S1 further includes presetting N-type via through regions and extended via exposed regions on a surface of the second conductive type semiconductor layer away from the active layer; after a dielectric layer is evaporated on the surface of one side, away from the active layer, of the second conductive type semiconductor layer, photoresist is removed and stripping is carried out to form a plurality of current blocking regions, and each current blocking region covers each N-type through hole penetrating region and extends outwards; the radius of the current blocking area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposed area adjacent to the extended through hole.
9. The method according to claim 6, wherein the step S2 further includes presetting N-type through hole penetrating regions and extended through hole penetrating regions on the surface of the transparent conductive layer away from the second conductive type semiconductor layer; after a dielectric layer is evaporated on the surface of one side, away from the second conductive semiconductor layer, of the transparent conductive layer, photoresist is removed and the transparent conductive layer is stripped to form a plurality of current blocking regions, and each current blocking region covers each N-type through hole penetrating region and extends outwards; the radius of the current blocking area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposed area adjacent to the extended through hole.
10. A manufacturing method of a high-power ultraviolet light-emitting diode, which is used for preparing the high-power ultraviolet light-emitting diode as claimed in any one of claims 1 and 3, and is characterized by comprising the following steps:
step S1, providing a substrate, and sequentially growing a buffer layer, a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the substrate, wherein the buffer layer, the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer form an epitaxial layer of the ultraviolet light emitting diode;
step S2, growing a transparent conducting layer on the epitaxial structure;
step S3, forming a plurality of uniformly distributed expansion through holes on the transparent conducting layer through standard photoetching, masking and corrosion processes, wherein each expansion through hole exposes a part of the surface of the second conducting type semiconductor layer;
step S4, depositing a metal mirror on the surface of the transparent conductive layer and the exposed part of the surface of the second conductive semiconductor layer;
step S5, forming a plurality of N-type through holes uniformly distributed on the metal reflector through standard photoetching, masking and corrosion processes, wherein each N-type through hole penetrates through the metal reflector to the first conductive semiconductor layer and exposes the surface of the buffer layer;
step S6, depositing isolation layers on the surface of the metal reflector and the side walls of the N-type through holes, and removing the insulation material contacting the first conductive type semiconductor layer of each N-type through hole;
step S7, depositing a conductive layer on the surface of the isolation layer, wherein the conductive layer fills each N-type through hole;
step S8, forming a light-emitting structure after the steps;
step S9, bonding the light-emitting structure and the front surface of the conductive substrate through a metal bonding layer;
step S10, removing the substrate, the buffer layer, and the first conductive semiconductor layer with a certain thickness by laser lift-off, wet etching, or dry etching process;
step S11, depositing a second transparent conducting layer on the surface of the first conducting type semiconductor layer, wherein the second transparent conducting layer is electrically connected with the conducting layer in each N-type through hole;
step S12, etching and exposing a partial region of the second conductive type semiconductor layer or a partial region of the transparent conductive layer on a portion of the epitaxial layer of the structure by using a plasma technique, and forming a second electrode on the partial exposed region of the second conductive type semiconductor layer or the partial exposed region of the transparent conductive layer by using an evaporation or sputtering process; growing an insulating layer between the etched epitaxial layer side wall and the second electrode;
and step S13, forming a first electrode on the reverse side of the conductive substrate by adopting an evaporation or sputtering process.
11. The method of claim 10, wherein the step S1 further includes presetting N-type via through regions and extended via exposed regions on a surface of the second conductive type semiconductor layer away from the active layer; masking and etching the surface of one side, away from the active layer, of the second conductive type semiconductor layer to form a plurality of grooves, and forming ion implantation areas in the grooves through ion implantation, wherein the ion implantation areas cover the N-type through hole penetrating areas and extend outwards; the radius of the ion implantation area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposure area adjacent to the expanded through hole.
12. The method of claim 10, wherein the step S1 further includes presetting N-type via through regions and extended via exposed regions on a surface of the second conductive type semiconductor layer away from the active layer; after a dielectric layer is evaporated on the surface of one side, away from the active layer, of the second conductive type semiconductor layer, photoresist is removed and stripping is carried out to form a plurality of current blocking regions, and each current blocking region covers each N-type through hole penetrating region and extends outwards; the radius of the current blocking area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposed area adjacent to the extended through hole.
13. The method according to claim 10, wherein the step S2 further includes presetting N-type via penetrating regions and extended via penetrating regions on a surface of the transparent conductive layer away from the second conductive type semiconductor layer; after a dielectric layer is evaporated on the surface of one side, away from the second conductive semiconductor layer, of the transparent conductive layer, photoresist is removed and the transparent conductive layer is stripped to form a plurality of current blocking regions, and each current blocking region covers each N-type through hole penetrating region and extends outwards; the radius of the current blocking area does not exceed the shortest distance from the center of the N-type through hole penetrating area to the edge of the exposed area adjacent to the extended through hole.
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