CN113421953B

CN113421953B - Deep ultraviolet light-emitting diode and manufacturing method thereof

Info

Publication number: CN113421953B
Application number: CN202110707101.2A
Authority: CN
Inventors: 姚禹; 郑远志; 康建; 陈向东
Original assignee: Maanshan Jiesheng Semiconductor Co ltd
Current assignee: Maanshan Jiesheng Semiconductor Co ltd
Priority date: 2021-06-24
Filing date: 2021-06-24
Publication date: 2022-12-13
Anticipated expiration: 2041-06-24
Also published as: CN113421953A

Abstract

The invention provides a deep ultraviolet light-emitting diode and a manufacturing method thereof, and relates to the technical field of LEDs. Wherein, dark ultraviolet emitting diode includes: the semiconductor device comprises a first semiconductor layer, an active layer, a second semiconductor layer, a second current expansion layer, a bonding metal layer and a substrate which are arranged in a stacked mode, a first current expansion layer arranged on the first semiconductor layer on the same layer as the active layer, a first insulating protection layer formed on the first current expansion layer, a first electrode penetrating through the first semiconductor layer and electrically connected with the first current expansion layer, and a second electrode electrically connected with the second current expansion layer. The manufacturing method of the deep ultraviolet light-emitting diode comprises the following steps: sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer; laminating a first current spreading layer on the first semiconductor layer not covered by the active layer; laminating a second current spreading layer on the second semiconductor layer; and carrying out high-temperature annealing on the first current spreading layer or the second current spreading layer. Therefore, the metal bonding effect can be prevented from being influenced by high-temperature annealing.

Description

Deep ultraviolet light-emitting diode and manufacturing method thereof

Technical Field

The invention relates to a deep ultraviolet light-emitting diode and a manufacturing method thereof, belonging to the technical field of LEDs.

Background

The light emitting diode is called LED for short, can efficiently convert electric energy into light energy, is a common light emitting device, and has wide application in modern society, such as illumination, flat panel display, medical devices and the like. The light emitting diode consists of a PN junction and has one-way conductivity, and when a forward voltage is applied to the light emitting diode, holes injected from the P region to the N region and electrons injected from the N region to the P region are respectively recombined with the electrons in the N region and the holes in the P region within a few microns near the PN junction to generate spontaneous emission fluorescence.

In the related art, a general LED generally adopts a vertical structure including a conductive substrate, a bonding metal layer, a first current spreading layer, a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a second current spreading layer, and a metal electrode, which are stacked. During preparation, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a first current expansion layer and a first metal bonding layer are sequentially grown on a temporary substrate from bottom to top, then the first bonding metal layer is subjected to metal bonding with a second metal bonding layer on a conductive substrate, the temporary substrate is removed, a second current expansion layer is grown on the N-type semiconductor layer, and finally a metal electrode is grown on the second current expansion layer.

However, with the development of technology, the existing common LED has not been able to meet the demand of the industry, and in recent years, deep ultraviolet light emitting diodes (UVC LEDs) based on iii-nitride materials have received more and more attention and attention due to the advantages of environmental protection, small size, portability, low power consumption, low voltage, and the like. However, since a deep ultraviolet light emitting diode (UVC LED) needs to use a semiconductor material based on group iii-nitride, and the contact resistance between the material and a metal electrode is large, a high temperature annealing process needs to be used to reduce the contact resistance, and if a vertical structure and a manufacturing process of an existing general LED are used, a metal bonding structure that does not endure high temperature may melt during high temperature annealing, thereby causing performance degradation of a metal bonding layer. Therefore, it is an urgent problem in the industry to provide a structure and a manufacturing method suitable for a deep ultraviolet light emitting diode.

Disclosure of Invention

The invention provides a deep ultraviolet light-emitting diode and a manufacturing method thereof, which solve the problem that bonding metal is melted and bonding performance is deteriorated due to high-temperature annealing when the deep ultraviolet LED with the existing vertical structure is manufactured based on the LED production process with the existing vertical structure in the prior art.

A first aspect of the present invention provides a deep ultraviolet light emitting diode, comprising:

a first semiconductor layer;

an active layer and a first current spreading layer formed on the first semiconductor layer, the active layer and the first current spreading layer being disposed on the same layer;

a first insulating protection layer formed on the first current spreading layer;

a second semiconductor layer, a second current spreading layer, a bonding metal layer, and a substrate stacked on the active layer;

a first electrode penetrating the first semiconductor layer and electrically connected to the first current spreading layer;

a second electrode electrically connected to the second current spreading layer.

Optionally, the substrate is a conductive substrate and serves as the second electrode, and the first electrode is in contact with the first current spreading layer.

Optionally, the substrate is a non-conductive substrate, and the first insulating protection layer extends between the second current spreading layer and the bonding metal layer and covers the second current spreading layer.

Optionally, the second electrode penetrates the first semiconductor layer, the active layer and the second semiconductor layer and is in contact with the second current spreading layer, and the second electrode is electrically insulated from the first electrode.

Optionally, a second insulating protection layer is disposed between the second electrode and the first semiconductor layer, the active layer and the second semiconductor layer.

Optionally, the first current spreading layer partially covers the first semiconductor layer, and the second current spreading layer partially covers the second semiconductor layer;

the bonding metal layer comprises a first bonding metal layer and a second bonding metal layer, the first bonding metal layer is positioned on a first part of the first insulating protective layer, the first part is opposite to the first current expansion layer, the second bonding metal layer is positioned on a second part of the first insulating protective layer, the second part is opposite to the second current expansion layer, and the first bonding metal layer is electrically insulated from the second bonding metal layer;

the first electrode is electrically connected with the first current spreading layer through the first bonding metal layer;

the second electrode is electrically connected to the second current spreading layer through the second bonding metal layer.

Optionally, a third electrode and a fourth electrode are further included;

the first electrode penetrates through the part, which is not covered by the first current expansion layer, of the first semiconductor layer, and the first insulating protection layer is in contact with the first bonding metal layer;

the third electrode penetrates through the first insulating protection layer and is in contact with the first bonding metal layer and the first current expansion layer;

the second electrode penetrates through the first semiconductor layer, the active layer and the part, not covered with the second current expansion layer, of the second semiconductor layer to be in contact with the second bonding metal layer, and a second insulating protection layer is arranged among the second electrode, the first semiconductor layer, the active layer and the second semiconductor layer;

the fourth electrode penetrates through the first insulating protection layer and is in contact with the second bonding metal layer and the second current spreading layer.

The invention provides a deep ultraviolet light-emitting diode, which comprises: a first semiconductor layer; an active layer and a first current spreading layer formed on the first semiconductor layer, the active layer and the first current spreading layer being disposed on the same layer; a first insulating protection layer formed on the first current spreading layer; a second semiconductor layer, a second current spreading layer, a bonding metal layer and a substrate laminated on the active layer; the first electrode penetrates through the first semiconductor layer and is electrically connected with the first current spreading layer; and the second electrode is electrically connected with the second current expansion layer. Because the procedure of laminating the first current spreading layer on the first semiconductor layer is before the procedure of metal bonding of the substrate and the bonding metal layer, the first current spreading layer is annealed at high temperature after being formed, and the first electrode penetrates through the first semiconductor layer and is electrically connected with the first current spreading layer, the high-temperature annealing operation can be advanced to the front of the metal bonding operation, and the bonding performance is prevented from being degraded.

The second aspect of the present invention provides a method for manufacturing a deep ultraviolet light emitting diode, comprising:

laminating an active layer and a second semiconductor layer on the first semiconductor layer;

patterning the second semiconductor layer and the active layer to expose a portion of the first semiconductor layer;

laminating a first current spreading layer on the exposed first semiconductor layer;

laminating a second current spreading layer on the second semiconductor layer;

performing high temperature annealing on the first current spreading layer or the second current spreading layer;

laminating a first insulating protection layer on the first current spreading layer;

laminating a metal bonding layer on the second current expansion layer and carrying out metal bonding with a substrate;

forming a first electrode electrically connected to the first current spreading layer and a second electrode electrically connected to the second current spreading layer.

Optionally, the first semiconductor layer is made of group iii nitride, and the first current spreading layer is subjected to high-temperature annealing at a first temperature, where the first temperature is 800-1100 ℃.

Optionally, annealing the second current spreading layer with a second temperature, where the second temperature is 400-600 ℃.

According to the deep ultraviolet light-emitting diode and the manufacturing method thereof, the current expansion layer can be subjected to high-temperature annealing before metal bonding operation, so that the contact resistance between the semiconductor layer and the current expansion layer is improved, and the problem that bonding metal is possibly melted after metal bonding due to high-temperature annealing is avoided.

Drawings

The above and other objects, features and advantages of embodiments of the present invention will become more readily understood by the following detailed description with reference to the accompanying drawings. Embodiments of the invention will be described by way of example and not limitation in the accompanying drawings, in which:

fig. 1 is a cross-sectional view of a first deep ultraviolet light emitting diode according to an embodiment of the present invention;

fig. 2-7 are schematic flow charts illustrating a method for manufacturing a deep ultraviolet light emitting diode according to a first embodiment of the present invention;

fig. 8 is a cross-sectional view of a second deep ultraviolet led according to an embodiment of the present invention;

fig. 9-14 are schematic flow charts illustrating a second method for fabricating a deep ultraviolet led according to an embodiment of the present invention;

fig. 15 a-20 b are schematic flow charts illustrating a method for fabricating a third deep ultraviolet light emitting diode according to an embodiment of the present invention;

fig. 21 is a partial top view of a third deep ultraviolet led according to an embodiment of the present invention.

Reference numerals:

11-a substrate;

12-a first semiconductor layer;

13-an active layer;

14-a second semiconductor layer;

21-a first current spreading layer;

22-a second current spreading layer;

31 — a first bonding metal layer;

32-a second bonding metal layer;

33-presetting a bonding metal layer;

41-a first insulating protection layer;

42-a second insulating protective layer;

51-a first electrode;

52-a second electrode;

53-a third electrode;

54-fourth electrode.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.

It should be understood that the following examples do not limit the order of execution of the steps of the claimed method. The various steps of the method of the invention can be performed in any possible order and in a round-robin fashion without contradicting each other.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be interconnected within two elements or in a relationship where two elements interact with each other unless otherwise specifically limited. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the second feature or the first and second features may be indirectly contacting each other through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

The gallium nitride (GaN), the aluminum nitride (AlN) and the indium nitride (InN) which are three-group nitride semiconductor materials are direct band gap semiconductor materials, the forbidden band widths of the materials are respectively 3.43 eV, 6.04 eV and 0.65eV, the light emission in the spectral range from 200 nm to 400nm can be realized by adjusting the alloy components of the materials, the wide spectral range from UVA to UVC is covered, and therefore, the material becomes an ideal semiconductor material for preparing the UVC LED. In addition, the nitride material itself can strongly absorb UVC Light, especially with multiple Quantum wells, P-AlGaN and P-GaN contact layers, so the deep ultraviolet led preferably adopts a vertical structure with more advantages in Light emission, heat dissipation and current flow, so that the ultraviolet Light can be emitted from one side of the substrate, thereby improving its Light Extraction Efficiency (LEE) and External Quantum Efficiency (EQE).

However, after the research, the inventors found that it is difficult to obtain an ideal ohmic contact between the group iii nitride semiconductor material and the current spreading layer (e.g., alxGaN1-xN (x > 0.45) with high aluminum composition), so that the current resistance between the group iii nitride semiconductor material layer and the metal electrode is large, thereby causing the deep ultraviolet diode to be difficult to directly follow the vertical structure of the above-mentioned general LED and the preparation method thereof.

The inventors have conducted extensive analyses on the above-mentioned phenomena, and have found that the above problems occur mainly due to: 1. the deep level defect increases with the Al component, so that the ionization energy of a Si donor is increased, the mobility is reduced, and the conductivity of n-AlGaN with high Al component is relatively poor; 2. the electron affinity is small, so that a Schottky barrier at a gold-half interface is high, the ohmic contact characteristic is poor, and particularly, after ICP etching, N vacancies are changed into deep energy level defects to exist, so that a Fermi energy level is far away from a conduction band, and the difficulty in preparing ohmic contact is further increased.

Therefore, the inventors considered that the group iii nitride semiconductor material layer and the metal electrode were annealed at a high temperature of about 1100 ℃ to reduce the current resistance between the group iii nitride semiconductor material and the metal material, thereby improving the ohmic contact performance therebetween. However, the addition of the high-temperature annealing step may cause a phenomenon that a metal bonding layer formed by metal bonding performed before the high-temperature annealing in the conventional process melts during the high-temperature annealing, so that the performance of the metal bonding is deteriorated, and the firmness of connection between the substrate and the semiconductor layer is deteriorated. Therefore, the inventor creatively provides a novel deep ultraviolet light emitting diode vertical structure so as to electrically connect the metal electrode with the current spreading layer before metal bonding, thereby ensuring that the performance of metal bonding is not influenced by high-temperature annealing.

Specifically, the deep ultraviolet light diode provided by the invention comprises: a first semiconductor layer; an active layer and a first current spreading layer formed on the first semiconductor layer, the active layer and the first current spreading layer being disposed on the same layer; a first insulating protection layer formed on the first current spreading layer; a second semiconductor layer, a second current spreading layer, a bonding metal layer and a substrate laminated on the active layer; the first electrode penetrates through the first semiconductor layer and is electrically connected with the first current spreading layer; and the second electrode is electrically connected with the second current spreading layer. During preparation, the first current extension layer is annealed at high temperature after being formed, ohmic contact performance between the first current extension layer and the first semiconductor layer is improved, and the first current extension layer is formed before metal bonding, so that the performance of metal bonding cannot be influenced by high-temperature annealing. After metal bonding, the first electrode penetrates through the first semiconductor layer and is electrically connected with the first current expansion layer, the first electrode and the first current expansion layer are both made of metal materials, the current impedance between the first electrode and the first current expansion layer is small, and the use requirement is met, so that the first electrode and the first semiconductor layer are electrically conducted, and the problem that the performance of metal bonding is influenced by high-temperature annealing is solved.

The present invention will be described in detail with reference to specific embodiments.

Example 1:

fig. 1 is a cross-sectional view of a deep ultraviolet light emitting diode provided in this embodiment.

As shown in fig. 1, the present embodiment provides a deep ultraviolet light emitting diode, including: a first semiconductor layer 12; an active layer 13 and a first current spreading layer 21 formed on the first semiconductor layer 12, the active layer 13 and the first current spreading layer 21 being disposed in the same layer; a first insulating protective layer 41 formed on the first current spreading layer 21; a second semiconductor layer 14, a second current spreading layer 22, a bonding metal layer, and a conductive substrate 11 stacked on the active layer 13; a first electrode 51 penetrating the first semiconductor layer 12 and electrically connected to the first current spreading layer 21; the second electrode 52 is electrically connected to the second current spreading layer 22. By contacting the conductive substrate 11 with the second current spreading layer 22 and contacting the first electrode 51 with the first current spreading layer 21, the layer structure of the deep ultraviolet light emitting diode can be reduced, so that the deep ultraviolet light emitting diode becomes thinner and lighter, and the current conducting area of the second current spreading layer 22 can also be increased.

Specifically, the first semiconductor layer 12 may be an N-type semiconductor layer made of a group iii nitride material, the second semiconductor layer 14 may be a P-type semiconductor layer, and the active layer 13 may be a light emitting layer, and it is understood that an electron blocking layer may be further formed between the active layer 13 and the second semiconductor layer 14. Of course, the first semiconductor layer 12 may be a P-type semiconductor layer, and the second semiconductor layer 14 may be an N-type semiconductor layer made of a group iii nitride material. The first semiconductor layer 12 is an N-type semiconductor layer, and the second semiconductor layer 14 is a P-type semiconductor layer, which should not be construed as a limitation to the scope of the present disclosure.

The substrate 11 may be made of a metal material such as molybdenum (Mo), copper (Cu), molybdenum-copper alloy (CuMo), copper-tungsten alloy (CuW), or silicon-aluminum alloy (AlSi), or other conductive non-metal materials, and the thickness of the substrate 11 is determined according to design requirements, for example, the thickness is 80um to 150um. A preset bonding metal layer 33 is formed on the substrate 11 in advance, and the preset bonding metal layer 33 is electrically connected to the substrate 11 to ensure that the substrate 11 can be electrically connected to the second current spreading layer 22 when serving as the conductive substrate 11, and the preset bonding metal layer 33 is used for being in metal bonding with the second bonding metal layer 32 on the second current spreading layer 22, so as to realize the current transmission in the vertical direction of the conductive substrate 11-the preset bonding metal layer 33-the second bonding metal layer 32-the second current spreading layer 22. The predetermined bonding metal layer 33 and the second bonding metal layer 32 are formed by stacking metals or alloys thereof, and the compositions of the two layers may be the same or different.

The second current spreading layer 22 may be made of zinc oxide, indium tin oxide, carbon nanotube, or other materials, or may be made of a metal material such as Ni, au, cr, W, ti, or a laminate of these materials. The gold-half interface between the second current spreading layer 22 and the second semiconductor layer 14 needs to be subjected to a rapid annealing process to obtain an ohmic contact. It is understood that the ohmic contact of the gold-half interface between the second current spreading layer 22 and the second semiconductor layer 14 is easily achieved, and the annealing temperature thereof is usually between 400 ℃ and 600 ℃.

The first current spreading layer 21 may be made of a laminate of one or more of titanium, gold, aluminum, platinum, silver, nickel, and the like. The gold-semiconductor interface between the first current spreading layer 21 and the first semiconductor layer 12 needs to be subjected to a high temperature rapid annealing process to obtain an ohmic contact, wherein the annealing temperature is in the range of 800-1100 ℃ depending on the metal species and the semiconductor doping concentration.

In the present embodiment, the first electrode 51 is formed in the first hole by forming the first hole on the first semiconductor layer 12, so that the first electrode 51 can be electrically contacted with the first current spreading layer 21. The cross section of the first holes is one or more of square, circular, fan-shaped, etc., and the number of the first holes is not limited, that is, the number of the first electrodes 51 is determined according to design requirements, and the invention is not particularly limited herein. The region where the first electrode 51 penetrates through the first semiconductor layer 12 is a region where the first semiconductor layer 12 is opposite to the first current spreading layer 21, and it is easy to understand that when the first electrode 51 is located at the edge of the first semiconductor layer 12, the sidewall of the first electrode 51 is exposed, that is, the first hole is in a form of a "unfilled corner".

Fig. 2-7 are schematic views of the manufacturing process of the deep ultraviolet light emitting diode.

The manufacturing method of the deep ultraviolet light emitting diode of the embodiment includes:

step one, an active layer 13 and a second semiconductor layer 14 are laminated on a first semiconductor layer 12.

Referring to fig. 2, a temporary substrate, which may be sapphire, is first provided. A first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 are sequentially grown from bottom to top on a first surface of a temporary substrate, wherein the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 may be collectively referred to as an epitaxial layer or an epitaxial stack.

For example, the first semiconductor layer 12 is an N-type semiconductor layer made of a group iii nitride material, the second semiconductor layer 14 is a P-type semiconductor layer, and the active layer 13 is a light emitting layer.

Alternatively, an electron blocking layer may be further laminated between the active layer 13 and the second semiconductor layer 14.

Step two, patterning the second semiconductor layer 14 and the active layer 13 to expose a portion of the first semiconductor layer 12.

Referring to fig. 2, a portion of the second semiconductor layer 14 and a portion of the active layer 13 are removed by a patterning method, so that a portion of the first semiconductor layer 12 is exposed, wherein the second semiconductor layer 14 and the active layer 13 may be aligned. For example, photolithography or ion etching is used to remove a portion of the second semiconductor layer 14 and the active layer 13 on the first semiconductor layer 12.

And step three, laminating a first current spreading layer 21 on the exposed first semiconductor layer 12, and performing high-temperature annealing on the first current spreading layer 21.

Referring to fig. 2, a first current spreading layer 21 electrically contacting the first semiconductor layer 12 is formed on the first semiconductor layer 12 by sputtering, evaporation, or the like, so that the first electrode 51 may be electrically connected to the first semiconductor layer 12. The first current spreading layer 21 may be formed of a laminate of one or at least two of titanium, gold, aluminum, platinum, silver, nickel, and the like.

After the first current spreading layer 21 is formed, a high temperature annealing temperature is selected according to the constituent metal species and the semiconductor doping concentration of the first current spreading layer 21, so as to perform high temperature annealing on the first current spreading layer 21, thereby improving the ohmic contact performance between the first current spreading layer 21 and the first semiconductor layer 12, wherein the high temperature annealing temperature may be 800-1100 ℃.

And fourthly, laminating a second current spreading layer 22 on the second semiconductor layer 14, and carrying out rapid annealing on the second current spreading layer 22.

Referring to fig. 2, a second current spreading layer 22 is formed on the second semiconductor layer 14 by sputtering, evaporation, or the like, and the second current spreading layer 22 is disposed on the second semiconductor layer 14 and electrically contacts the second semiconductor layer 14. The material of the second current spreading layer 22 may be zinc oxide, indium tin oxide, carbon nanotube, etc.; the metal material may be Ni, au, cr, W, ti, or an alloy of a plurality of materials.

After forming the second current spreading layer 22, a rapid anneal is performed for the second current spreading layer 22 using a temperature of 400-600 ℃ to improve the ohmic contact of the second current spreading layer 22 with the second semiconductor layer 14. It should be understood that when the first semiconductor layer 12 is a P-type semiconductor and the second semiconductor layer 14 is an N-type semiconductor, the first current spreading layer 21 is rapidly annealed at a temperature of 400-600 c and the second current spreading layer 22 is annealed at a high temperature of 800-1100 c. It is noted that the annealing step at a higher temperature needs to be preceded by the annealing step at a lower temperature to avoid damage to the current spreading layer that requires the higher temperature annealing process.

Step five, laminating a first insulating protection layer 41 on the first current spreading layer 21.

Referring to fig. 3, the first insulating protection layer 41 is formed by using a vapor chemical deposition, an electron beam evaporation, or a thermal resistance evaporation method, and the first insulating protection layer 41 completely covers the first insulating protection layer 41 to prevent the first current spreading layer 21 and the second current spreading layer 22 from being shorted. It is understood that the first insulating protection layer 41 may extend to cover a part of the second current spreading layer 22 after completely covering the first current spreading layer 21, wherein a method of partially covering the second current spreading layer 22 is: the second current spreading layer 22 is completely covered first, and then the first insulating protection layer 41 is patterned, so that a portion of the second current spreading layer 22 is exposed, so that the second current spreading layer 22 is electrically connected to the second bonding metal layer 32. The material of the first insulating protective layer 41 may be made of silicon oxide.

Referring to fig. 3, further, the exposed regions of the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 between the first current spreading layer 21 and the second current spreading layer 22 may also be covered.

And step six, laminating a metal bonding layer on the second current expansion layer 2221 and carrying out metal bonding with the substrate 11.

Referring to fig. 3, a second bonding metal layer 32 is formed on the surface of the exposed second current spreading layer 22, and the second current spreading layer 22 is electrically connected to the second bonding metal layer 32. Wherein the second bonding metal layer 32 covers at least the exposed second current spreading layer 22. It should be understood that the second bonding metal layer 32 may also cover a part or all of the first insulating protection layer 41, and the second bonding metal layer 32 covers a part or all of the first insulating protection layer 41, in order to maximize the bonding area and improve the bonding strength, but due to the obstruction of the first insulating protection layer 41, the second bonding metal layer 32 can only form an electrical connection with the exposed second current spreading layer 22, and does not participate in other formed electrical connections;

then, a conductive substrate 11 is provided, a predetermined bonding metal layer 33 is formed on the first surface of the conductive substrate 11 in advance, and the predetermined bonding metal layer 33 is electrically connected to the conductive substrate 11. The conductive substrate 11 is made of a metal material such as molybdenum (Mo), copper (Cu), molybdenum-copper alloy (CuMo), copper-tungsten alloy (CuW), or silicon-aluminum alloy (AlSi), or other conductive non-metal materials. The bonding metal layer 33 and the second bonding metal layer 32 are stacked by metal or alloy thereof, and the components of the two layers may be the same or different;

referring to fig. 4, the prearranged bonding metal layer 33 is metal-bonded to the second bonding metal layer 32, so that the conductive substrate 11 is bonded to the epitaxial layer as a whole;

referring to fig. 5, the temporary substrate is removed by laser lift-off or other means so that the surface of the first semiconductor layer 12 on the side in contact with the temporary substrate is entirely exposed.

And step six, forming a first electrode 51 electrically connected with the first current spreading layer 21.

Referring to fig. 6 and 7, forming the first electrode 51 electrically connected to the first current spreading layer 21 includes the steps of:

depositing a masking layer on the surface of the first semiconductor layer 12 away from the active layer 13 by chemical or vapor deposition; then, removing part of the masking layer through photoetching and etching, and reserving H first openings; completely removing the first semiconductor layer 12 in the first opening by adopting a plasma dry etching mode until the first current spreading layer 21 is exposed in the first opening; removing the residual masking layer after the dry etching in a wet etching mode; finally, a first electrode 51 in contact with the first current spreading layer 21 is formed within the first hole.

It should be noted that the vertical projection of the first opening corresponds to the position in the first current spreading layer 21 above the first semiconductor layer 12, and the position is limited to the projection range where the first current spreading layer 21 is laid. The first opening may be in the shape of a square, a circle, a sector, etc., and may have a size at most equal to the first current spreading layer 21, for example, may be one or more circles having a diameter of 80-100 um. The side wall of the first opening is a masking layer. The sidewall of the first hole is the first semiconductor layer 12, and the bottom thereof is the first current spreading layer 21.

And seventhly, thinning and cutting the light emitting diode by a conventional method to obtain a final finished product. The thinning and cutting method may be an existing method, and this embodiment does not limit this.

Example 2:

fig. 8 is a cross-sectional view of the deep ultraviolet light emitting diode provided in this embodiment.

As shown in fig. 8, the present embodiment provides a deep ultraviolet light emitting diode, including: a first semiconductor layer 12; an active layer 13 and a first current spreading layer 21 formed on the first semiconductor layer 12, the active layer 13 and the first current spreading layer 21 being disposed in the same layer; a first insulating protective layer 41 formed on the first current spreading layer 21; a second semiconductor layer 14, a second current spreading layer 22, a bonding metal layer, and a substrate 11 stacked on the active layer 13; a first electrode 51 penetrating the first semiconductor layer 12 and electrically connected to the first current spreading layer 21; the second electrode 52 penetrates the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 and is in contact with the second current spreading layer 22, the second electrode 52 being electrically insulated from the first electrode 51; the substrate 11 is a non-conductive substrate 11 and the first insulating protection layer 41 extends between the second current spreading layer 22 and the bonding metal layer and covers the second current spreading layer 22.

Specifically, the first semiconductor layer 12 may be an N-type semiconductor layer made of a group iii nitride material, the second semiconductor layer 14 is a P-type semiconductor layer, and the active layer 13 is a light emitting layer, and it is understood that an electron blocking layer may be further formed between the active layer 13 and the second semiconductor layer 14. Of course, the first semiconductor layer 12 may be a P-type semiconductor layer, and the second semiconductor layer 14 may be an N-type semiconductor layer made of a group iii nitride material. The following description will take the first semiconductor layer 12 as an N-type semiconductor layer and the second semiconductor layer 14 as a P-type semiconductor layer as an example to illustrate the embodiments of the present disclosure, but it should not be construed as limiting the scope of the present disclosure.

The substrate 11 may be made of silicon carbide, aluminum nitride, or the like having excellent thermal conductivity. The first insulating protective layer 41 may be made of silicon oxide, and the thickness of the substrate 11 is determined according to design requirements. The substrate is used as a non-conductive substrate 11, and the first insulating protection layer 41 extends to between the second current spreading layer 22 and the second bonding metal layer 32 and covers the second current spreading layer 22, so that the second current spreading layer 22 and the second bonding metal layer 32 cannot be electrically connected, and the non-conductive substrate is prevented from being damaged.

The first insulating protective layer 41 covers at least the first semiconductor layer 12 and the second semiconductor layer 14, and insulates the first semiconductor layer 12 and the second semiconductor layer 14 from each other and the second current spreading layer 22 from the second bonding metal layer 32. Or, while the first insulating protection layer 41 covers the first semiconductor layer 12 and the second semiconductor layer 14, the active layer 13, the second semiconductor layer 14 and the first exposed region on the first semiconductor layer 12 are covered, where the first exposed region is an exposed region on one side surface of the first semiconductor layer 12 on which the active layer 13 and the first current spreading layer 21 are disposed.

The second current spreading layer 22 may be made of zinc oxide, indium tin oxide, carbon nanotube, or other materials, or may be made of a metal material such as Ni, au, cr, W, ti, or a laminate of these materials. The gold-half interface between the second current spreading layer 22 and the second semiconductor layer 14 needs to be subjected to a rapid annealing process to obtain an ohmic contact. It is understood that the ohmic contact at the gold-half interface between the second current spreading layer 22 and the second semiconductor layer 14 is easily achieved, and thus the annealing temperature is usually between 400 ℃ and 600 ℃.

The bonding metal layer of the embodiment includes a first bonding metal layer 31 and a second bonding metal layer 32, a predetermined bonding metal layer 33 is formed on the substrate 11, and the first bonding metal layer 31 and the second bonding metal layer 32 are respectively metal-bonded to the predetermined bonding metal layer 33. The first bonding metal layer 31 covers at least a first region of the first insulating protective layer 41 facing the first current spreading layer 21, and the second bonding metal layer 32 covers at least a second region of the first insulating protective layer 41 facing the second current spreading layer 22. The first bonding metal layer 31 and the second bonding metal layer 32 are simultaneously metal-bonded to the predetermined bonding metal layer 33, so as to increase the bonding area and improve the bonding strength. Of course, the first bonding metal layer 31 and the second bonding metal layer 32 may entirely cover the first insulating protection layer 41, so as to maximize the bonding area, but due to the blocking of the first insulating protection layer 41, the first bonding metal layer 31 is not electrically connected to the first current spreading layer 21, and the second bonding metal layer 32 is not electrically connected to the second current spreading layer 22. The first bonding metal layer 31 or the second bonding metal layer 32 and the predetermined bonding metal layer 33 are formed by stacking metals or alloys thereof, and the compositions of the two layers may be the same or different.

In the present embodiment, the second hole is formed through the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14, and the second electrode 52 is formed in the second hole, so that the second electrode 52 is electrically contacted with the second current spreading layer 22, and the first electrode 51 and the second electrode 52 are located on the same side. The cross section of the second holes is one or more of square, round, fan-shaped, etc., and the number of the second holes is not limited, that is, the number of the second electrodes 52 is determined according to the design requirement, and the invention is not limited in detail herein. The second electrode 52 is provided in a region where the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 are opposed to the second current spreading layer 22.

In order to avoid short-circuiting the second electrode 52 with the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14, a second insulating protective layer 42 is provided between the second electrode 52 and the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14. It is understood that the second insulating protection layer 42 covers at least the hole wall of the second hole to ensure that the second electrode 52 is insulated from the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14. Of course, the second insulating protection layer 42 may also cover the surface of the first semiconductor layer 12 away from the first current spreading layer 21 and the hole wall of the first hole.

The second electrode 52 penetrates through the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14 and is in contact with the second current spreading layer 22, the first electrode 51 penetrates through the first semiconductor layer 12 and is electrically connected with the first current spreading layer 21, and the first electrode 51 and the second electrode 52 can be led out from the same side, so that the deep ultraviolet light emitting diode is a composite structure of a vertical structure and a horizontal structure.

Fig. 9-14 are schematic flow charts of the manufacturing method of the deep ultraviolet light emitting diode.

Referring to fig. 9, a temporary substrate, which may be sapphire, is first provided. A first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 are sequentially grown from bottom to top on a first surface of a temporary substrate, wherein the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 may be collectively referred to as an epitaxial layer or an epitaxial stack.

Referring to fig. 9, a portion of the second semiconductor layer 14 and a portion of the active layer 13 are removed by a patterning method so that a portion of the first semiconductor layer 12 is exposed, wherein the second semiconductor layer 14 and the active layer 13 may be aligned. For example, photolithography or ion etching is used to remove a portion of the second semiconductor layer 14 and the active layer 13 on the first semiconductor layer 12.

Referring to fig. 9, the first current spreading layer 21 is formed by sputtering, evaporation, or the like, and the first current spreading layer 21 is disposed on the exposed first semiconductor layer 12 and is in electrical contact with the first semiconductor layer 12, so that the first electrode 51 may be electrically connected to the first semiconductor layer 12. The first current spreading layer 21 may be formed of a laminate of one or at least two of titanium, gold, aluminum, platinum, silver, nickel, and the like.

After the first current spreading layer 21 is formed, a high temperature annealing temperature is selected according to the constituent metal species and the semiconductor doping concentration of the first current spreading layer 21, so that the first temperature high temperature annealing is performed on the first current spreading layer 21 to improve the ohmic contact performance between the first current spreading layer 21 and the first semiconductor layer 12, wherein the high temperature annealing temperature may be 800-1100 ℃.

And step four, laminating a second current spreading layer 22 on the second semiconductor layer 14, and annealing the second current spreading layer 22.

Referring to fig. 9, a second current spreading layer 22 is formed by photolithography, evaporation, or the like, and the second current spreading layer 22 is disposed on the second semiconductor layer 14 and electrically contacts the second semiconductor layer 14. The material of the second current spreading layer 22 may be zinc oxide, indium tin oxide, carbon nanotube, etc.; the metal material may be Ni, au, cr, W, ti, or an alloy of a plurality of materials.

Step five, laminating a first insulating protection layer 41 on the first current spreading layer 21 and the second current spreading layer 22.

Referring to fig. 10, the first insulating protective layer 41 is obtained by a conventional method such as vapor chemical deposition, electron beam evaporation, or thermal resistance evaporation, and the first insulating protective layer 41 covers at least the first semiconductor layer 12 and the second semiconductor layer 14. It is understood that the first insulating protection layer 41 may cover the exposed regions of the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14 between the first current spreading layer 21 and the second current spreading layer 22, i.e. completely cover the exposed surface of the epitaxial layer. The material of the first insulating protective layer 41 may be silicon oxide.

Sixthly, after the first bonding metal layer 31 and the second bonding metal layer 32 are laminated on the first insulating protective layer 41, the first bonding metal layer 31 and the second bonding metal layer 32 are in metal bonding with the preset bonding metal layer 33 on the substrate 11.

Referring to fig. 10, a first bonding metal layer 31 and a second bonding metal layer 32 are formed on a surface of the first insulating protection layer 41, wherein the first bonding metal layer 31 and the second bonding metal layer 32 at least partially cover the first insulating protection layer 41. It is understood that the first bonding metal layer 31 and the second bonding metal layer 32 are covered on the whole first insulating protection layer 41, in order to maximize the bonding area and improve the bonding strength, since the first insulating protection layer 41 can cover the surface of the epitaxial layer, the first bonding metal layer 31 and the second bonding metal layer 32 are not electrically connected with the first current spreading layer 21 and the second current spreading layer 22;

then, an insulating substrate 11 is provided, and a predetermined bonding metal layer 33 is formed in advance on the insulating substrate 11. The insulating substrate 11 may be made of silicon carbide, aluminum nitride, or the like having an excellent thermal conductivity;

referring to fig. 11, the first bonding metal layer 31 and the second bonding metal layer 32 are respectively metal-bonded to the predetermined bonding metal layer 33, so that the insulating substrate 11 and the epitaxial layer are bonded as a whole;

referring to fig. 12, in a fourth step, the temporary substrate is removed by laser lift-off or other methods, so that the surface of the first semiconductor layer 12 on the side contacting the temporary substrate is completely exposed.

And a sixth step of forming a first electrode 51 electrically connected to the first current spreading layer 21 and a second electrode 52 electrically connected to the second current spreading layer 22.

Specifically, forming the first electrode 51 electrically connected to the first current spreading layer 21 and the second electrode 52 electrically connected to the second current spreading layer 22 includes the steps of:

depositing a masking layer on the surface of the first semiconductor layer 12 away from the active layer 13 by chemical or vapor deposition;

then, removing part of the masking layer through photoetching and etching to reserve second openings with the number of M and third openings with the number of N;

referring to fig. 13, the first semiconductor layer 12 in the second opening position and the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14 in the third opening position are completely removed by using a plasma dry etching method until the first current spreading layer 21 is exposed in the second opening and the second current spreading layer 22 is exposed in the third opening;

fourthly, removing the residual masking layer after the dry etching in a wet etching mode;

referring to fig. 14, a second insulating protection layer 42 at least covering the hole wall of the second hole is formed by conventional methods such as vapor chemical deposition, electron beam evaporation, or thermal resistance evaporation;

referring to fig. 14, finally, a first electrode 51 contacting the first current spreading layer 21 is formed in the first hole, and a second electrode 52 contacting the second current spreading layer 22 is formed in the second hole.

It should be noted that the vertical projection of the second opening corresponds to the position in the first current spreading layer 21 above the first semiconductor layer 12, and the position is limited to the projection range where the first current spreading layer 21 is laid; the projection of the third opening in the vertical direction corresponds to the second current spreading layer 22 located above the first semiconductor layer 12, and the position thereof is limited within the projection range where the second current spreading layer 22 is laid. The shape of the second or third opening may be various, such as square, circular, fan-shaped, etc., and the size thereof is at most equal to that of the first or second current spreading

layer

21 or 22, for example, one or more circles having a diameter of 80-100 um. The side walls of the second opening and the third opening are all the masking layers. The sidewall of the first hole is the first semiconductor layer 12, and the bottom thereof is the first current spreading layer 21. The sidewalls of the second hole are sequentially a first semiconductor layer 12, an active layer 13 and a second semiconductor layer 14 from top to bottom, and the bottom thereof is a second current spreading layer 22. Of course, the second insulating protection layer 42 can also cover the hole wall of the first hole and the exposed surface of the first semiconductor layer 12.

Example 3:

the deep ultraviolet light emitting diode provided by the embodiment comprises: a first semiconductor layer 12; an active layer 13 and a first current spreading layer 21 formed on the first semiconductor layer 12, the active layer 13 and the first current spreading layer 21 being disposed on the same layer; a first insulating protective layer 41 formed on the first current spreading layer 21; a second semiconductor layer 14, a second current spreading layer 22, a bonding metal layer, and a substrate 11 stacked on the active layer 13; the substrate 11 is a non-conductive substrate 11, the first insulating protection layer 41 extends between the second current spreading layer 22 and the bonding metal layer and covers the second current spreading layer 22; the first electrode 51 penetrates the first semiconductor layer 12 and is electrically connected to the first current spreading layer 21; the second electrode 52 is electrically connected to the second current spreading layer 22;

the first current spreading layer 21 partially covers the first semiconductor layer 12, and the second current spreading layer 22 partially covers the second semiconductor layer 14; the bonding metal layer comprises a first bonding metal layer 31 and a second bonding metal layer 32, the first bonding metal layer 31 is positioned on a first part of the first insulating protective layer 41, the first part is opposite to the first current spreading layer 21, the second bonding metal layer 32 is positioned on a second part of the first insulating protective layer 41, the second part is opposite to the second current spreading layer 22, and the first bonding metal layer 31 is electrically insulated from the second bonding metal layer 32; the first electrode 51 is electrically connected to the first current spreading layer 21 through the first bonding metal layer 31; the second electrode 52 is electrically connected to the second current spreading layer 22 through the second bonding metal layer 32. The first bonding metal layer 31 and the second bonding metal layer 32 allow the arrangement positions of the first electrode 51 and the second electrode 52 to be free from the restrictions of the first current spreading layer 21 and the second current spreading layer 22, and thus the present invention can satisfy diversified designs.

Specifically, the first semiconductor layer 12 may be an N-type semiconductor layer made of a group iii nitride material, the second semiconductor layer 14 may be a P-type semiconductor layer, and the active layer 13 may be a light emitting layer, and it is understood that an electron blocking layer may be further formed between the active layer 13 and the second semiconductor layer 14. Of course, the first semiconductor layer 12 may be a P-type semiconductor layer, and the second semiconductor layer 14 may be an N-type semiconductor layer made of a group iii nitride material. The following description will take the first semiconductor layer 12 as an N-type semiconductor layer and the second semiconductor layer 14 as a P-type semiconductor layer as an example to illustrate the embodiments of the present disclosure, but it should not be construed as limiting the scope of the present disclosure.

The substrate 11 may be made of a material having an excellent thermal conductivity, such as silicon carbide or aluminum nitride.

It is understood that the area of the first portion opposite to the first current spreading layer 21 is the entire area or a partial area of the first current spreading layer 21; the area of the second portion opposite to the second current spreading layer 22 is the entire area or a partial area of the second current spreading layer 22. The first bonding metal layer 31 may cover all or part of the first portion, and the second bonding metal layer 32 may cover all or part of the second portion.

In the present embodiment, the first hole is formed in the first semiconductor layer 12, and the first electrode 51 is formed in the first hole, so that the first electrode 51 can contact with the first bonding metal layer 31. The cross section of the first holes is one or more of square, circular, fan-shaped, etc., and the number of the first holes is not limited, that is, the number of the first electrodes 51 is determined according to design requirements, and the invention is not particularly limited herein. The region where the first electrode 51 penetrates through the first semiconductor layer 12 is a region where the first semiconductor layer 12 faces the first current spreading layer 21. It is easy to understand that when the first electrode 51 is located at the edge of the first semiconductor layer 12, the sidewall of the first electrode 51 is exposed, i.e. the first hole has a "unfilled corner" form.

In this embodiment, a second hole may be formed through the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14, and the second electrode 52 is formed in the second hole, such that the second electrode 52 is in contact with the second bonding metal layer 32, and the first electrode 51 and the second electrode 52 are located on the same side. The cross section of the second holes is one or more of square, round, fan-shaped, etc., and the number of the second holes is not limited, that is, the number of the second electrodes 52 is determined according to the design requirement, and the invention is not limited in detail herein.

The second insulating protection layer 42 can prevent the second electrode 52 from short-circuiting the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14, and the second insulating protection layer 42 at least covers the hole wall of the second hole to ensure that the second electrode 52 is insulated from the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14. It is understood that the second insulating protection layer 42 may also cover the surface of the first semiconductor layer 12 facing away from the first current spreading layer 21 and the wall of the first hole.

The substrate 11 is made of a non-conductive material such as silicon carbide or aluminum nitride. A patterned pre-bonding metal layer 33 is formed on the surface of the substrate 11 in advance, and the pre-bonding metal layer 33 is bonded to the first bonding metal layer 31 and the second bonding metal layer 32.

Fig. 21 is a partial top view schematic diagram of the deep ultraviolet light emitting diode provided in this embodiment.

As shown in fig. 21, in an alternative embodiment, a third electrode 53 and a fourth electrode 54 are further included; the first electrode 51 penetrates through the portion of the first semiconductor layer 12 not covered with the first current spreading layer 21 and the first insulating protective layer 41 to be in contact with the first bonding metal layer 31; the third electrode 53 penetrates the first insulating protective layer 41 and is in contact with the first bonding metal layer 31 and the first current spreading layer 21; the second electrode 52 penetrates through the first semiconductor layer 12, the active layer 13 and the part of the second semiconductor layer 14 which is not covered with the second current spreading layer 22 to be in contact with the second bonding metal layer 32, and a second insulating protection layer 42 is arranged between the second electrode 52 and the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14; the fourth electrode 54 penetrates the first insulating protective layer 41 and is in contact with the second bonding metal layer 32 and the second current spreading layer 22. The third electrode 53 and the fourth electrode 54 are disposed such that the first current spreading layer 21 is electrically connected to the first bonding metal layer 31, so that the first electrode 51 can be electrically conducted with the first current spreading layer 21; the second current spreading layer 22 is electrically connected to the second bonding metal layer 32 so that the second electrode 52 can be electrically conducted to the second current spreading layer 22.

The first bonding metal layer 31 is electrically connected to the first current spreading layer 21 and the second bonding metal layer 32 is electrically connected to the second current spreading layer 22 via the third electrode 53 and the fourth electrode 54, so that the arrangement positions of the first electrode 51 and the second electrode 52 are not limited by the first current spreading layer 21 and the second current spreading layer 22, and diversified designs can be satisfied.

Fig. 15 a-20 b are schematic flow charts of the manufacturing method of the deep ultraviolet light emitting diode.

Referring to fig. 15a, a temporary substrate, which may be sapphire, is first provided. A first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 are sequentially grown from bottom to top on a first surface of the temporary substrate, wherein the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 may be collectively referred to as an epitaxial layer or an epitaxial stack.

Referring to fig. 15a and 15b, a portion of the second semiconductor layer 14 and a portion of the active layer 13 are removed by a patterning method so that a portion of the first semiconductor layer 12 is exposed, wherein the second semiconductor layer 14 and the active layer 13 may be aligned. For example, photolithography or ion etching is used to remove a portion of the second semiconductor layer 14 and the active layer 13 on the first semiconductor layer 12.

Referring to fig. 15a, a first current spreading layer 21 is formed by sputtering or evaporation, and the first current spreading layer 21 is disposed on the exposed first semiconductor layer 12 and electrically contacts the first semiconductor layer 12, so that the first electrode 51 may be electrically connected to the first semiconductor layer 12. The first current spreading layer 21 may be formed of a laminate of one or at least two of titanium, gold, aluminum, platinum, silver, nickel, and the like.

And fourthly, laminating a second current spreading layer 22 on the second semiconductor layer 14, and annealing the second current spreading layer 22.

Referring to fig. 15a, a second current spreading layer 22 is formed by sputtering, evaporation, or the like, and the second current spreading layer 22 is disposed on the second semiconductor layer 14 and electrically contacts the second semiconductor layer 14. The material of the second current spreading layer 22 may be zinc oxide, indium tin oxide, carbon nanotube, etc.; the metal material may be Ni, au, cr, W, ti, or an alloy of a plurality of materials.

And step five, laminating a first insulating protection layer 41 on the first current spreading layer 21 and the second current spreading layer 22.

Referring to fig. 16a and 16b, the first insulating protection layer 41 is obtained by using a conventional method such as vapor chemical deposition, electron beam evaporation, or thermal resistance evaporation, and the first insulating protection layer 41 at least covers the first current spreading layer 21 and the second current spreading layer 22. It is understood that the first insulating protection layer 41 may cover the exposed regions of the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14 between the first current spreading layer 21 and the second current spreading layer 22, i.e. completely cover the exposed surface of the epitaxial layer. The material of the first insulating protective layer 41 may be made of silicon oxide.

Step six, patterning the first insulating protection layer 41, so that a plurality of windows are formed on the first insulating protection layer 41, and a portion of the first current spreading layer 21 and a portion of the second current spreading layer 22 are exposed.

Referring to fig. 16a and 16b, a patterning manner is adopted to expose a portion of the first current spreading layer 21 and a portion of the second current spreading layer 22, so that the first current spreading layer 21 and the second current spreading layer 22 are electrically connected with the first semiconductor layer 12 and the second semiconductor layer 14, respectively. Here, the third electrode 53 or the fourth electrode 54 is provided in the window, the first bonding metal layer 31 and the first current spreading layer 21 are electrically connected through the third electrode 53, and the second bonding metal layer 32 and the second current spreading layer 22 are electrically connected through the fourth electrode 54.

And step seven, bonding the epitaxial layer with the insulating substrate 11.

Referring to fig. 16a, a first bonding metal layer 31 and a second bonding metal layer 32 are stacked on a first insulating protective layer 41, and the first bonding metal layer 31 and the second bonding metal layer 32 are provided in the same layer. The first bonding metal layer 31 and the second bonding metal layer 32 are electrically connected with the exposed first current spreading layer 21 and the exposed second current spreading layer 22, respectively, wherein the number of the first bonding metal layers 31 is X, the number of the second bonding metal layers 32 is Y, and X and Y may be opposite or different; it should be understood that the first and second bonding metal layers 31 and 32 cover at least the exposed first and second current spreading

layers

21 and 22;

then, an insulating substrate 11 is provided, and a predetermined bonding metal layer 33 is formed in advance on a first surface of the insulating substrate 11. The insulating substrate 11 may be made of silicon carbide, aluminum nitride, or other materials having excellent thermal conductivity;

referring to fig. 17a and 17b, the first bonding metal layer 31 and the second bonding metal layer 32 are respectively metal-bonded to the predetermined bonding metal layer 33, so that the insulating substrate 11 is bonded to the epitaxial layer as a whole. The first bonding metal layer 31, the second bonding metal layer 32 and the predetermined bonding metal layer 33 are all formed by stacking metals or alloys thereof, and the components of the three layers may be the same or different;

referring to fig. 18a and 18b, the temporary substrate is removed by laser lift-off or other means so that the surface of the first semiconductor layer 12 on the side in contact with the temporary substrate is entirely exposed.

And step eight, forming a first electrode 51 electrically connected with the first current spreading layer 21 and a second electrode 52 electrically connected with the second current spreading layer 22.

a first step of depositing a masking layer on the surface of the first semiconductor layer 12 away from the active layer 13 by chemical or vapor deposition;

then, removing part of the masking layer through photoetching and etching, and reserving P fourth holes and K fifth holes;

referring to fig. 19a and 19b, completely removing the first semiconductor layer 12 in the fourth opening position and the first semiconductor layer 12, the active layer 13 and the second semiconductor layer 14 in the fifth opening position by using a plasma dry etching method until the first bonding metal layer 31 is exposed in the fourth opening and the second bonding metal layer 32 is exposed in the fifth opening;

fifthly, forming a second insulating protection layer 42 at least covering the hole wall of the second hole by adopting conventional methods such as vapor chemical deposition, electron beam evaporation or thermal resistance evaporation;

referring to fig. 20a and 20b, finally, a first electrode 51 contacting the first bonding metal layer 31 is formed in the first hole, and a second electrode 52 contacting the second bonding metal layer 32 is formed in the second hole.

It should be noted that the projection of the fourth opening in the vertical direction corresponds to the projection of the first bonding metal layer 31 on the first semiconductor layer 12, and the position of the fourth opening is limited to the projection range where the first bonding metal layer 31 is laid; the vertical projection of the fifth opening corresponds to the second bonding metal layer 32 on the first semiconductor layer 12, and the position of the fifth opening is limited within the projection range of the second bonding metal layer 32. The shape of the fourth opening or the fifth opening may be various, such as square, circle, fan, etc., and the size thereof is at most equal to that of the first bonding metal layer 31 or the second bonding metal layer 32, for example, the shape may be one or more circles having a diameter of 80-100 um. And the side walls of the fourth opening and the fifth opening are all masking layers. The sidewall of the first hole is the first semiconductor layer 12, and the bottom thereof is the first bonding metal layer 31. The sidewalls of the second hole are sequentially a first semiconductor layer 12, an active layer 13 and a second semiconductor layer 14 from top to bottom, and the bottom of the second hole is a second bonding metal layer 32. It should be understood that the second insulating protection layer 42 may also cover the hole wall of the first hole and the exposed surface of the first semiconductor layer 12.

And step nine, thinning and cutting the light emitting diode by a conventional method to obtain a final finished product. The thinning and cutting method may be an existing method, and this embodiment does not limit this.

In a second aspect, the present invention provides a method for manufacturing a deep ultraviolet light emitting diode, including:

A temporary substrate, which may be sapphire, is first provided. A first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 are sequentially grown from bottom to top on a first surface of the temporary substrate, wherein the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14 may be collectively referred to as an epitaxial layer or an epitaxial stack.

A portion of the second semiconductor layer 14 and a portion of the active layer 13 are removed by a patterning method so that a portion of the first semiconductor layer 12 is exposed, wherein the second semiconductor layer 14 and the active layer 13 may be aligned. For example, photolithography or ion etching is used to remove a portion of the second semiconductor layer 14 and the active layer 13 on the first semiconductor layer 12.

And step three, laminating a first current spreading layer 21 on the exposed first semiconductor layer 12.

The first current spreading layer 21 is formed by sputtering, evaporation, or the like, and the first current spreading layer 21 is disposed on the exposed first semiconductor layer 12 and is in electrical contact with the first semiconductor layer 12, so that the first electrode 51 can be electrically connected to the first semiconductor layer 12. The first current spreading layer 21 may be made of one or a laminate of at least two of titanium, gold, aluminum, platinum, silver, nickel, and the like.

And step four, laminating a second current spreading layer 22 on the second semiconductor layer 14.

The second current spreading layer 22 is formed by sputtering, evaporation, or the like, and the second current spreading layer 22 is provided on the second semiconductor layer 14 and is in electrical contact with the second semiconductor layer 14. The material of the second current spreading layer 22 may be zinc oxide, indium tin oxide, carbon nanotube, etc.; the metal material may be Ni, au, cr, W, ti, or an alloy of a plurality of materials.

And step five, performing high-temperature annealing on the first current spreading layer 21, and performing rapid annealing on the second current spreading layer 22.

And step six, laminating a first insulating protection layer 41 on the first current spreading layer 21.

The first insulating protective layer 41 may be formed by vapor chemical deposition, electron beam evaporation, or thermal resistance evaporation.

And step seven, laminating a metal bonding layer on the second current spreading layer 22 and carrying out metal bonding with the substrate 11.

A second bonding metal layer 32 firstly laminated on the second current spreading layer 22 is connected with a preset bonding metal layer 33 formed on the substrate 11 in a metal bonding mode, so that the epitaxial layer is bonded with the substrate 11;

finally, the temporary substrate is removed by laser lift-off or other means, so that the surface of the first semiconductor layer 12 on the side away from the active layer 13 is exposed.

Depositing a masking layer on the surface of the first semiconductor layer 12 away from the active layer 13 by chemical or vapor deposition; then, removing part of the masking layer through photoetching and etching, and reserving a number D of sixth openings; completely removing the first semiconductor layer 12 in the sixth opening by adopting a plasma dry etching mode until the first current spreading layer 21 is exposed in the sixth opening; removing the residual masking layer after the dry etching in a wet etching mode; finally, a first electrode 51 in contact with the first current spreading layer 21 is formed within the first hole.

The substrate 11 is made of a conductive material so that the substrate 11 is a conductive substrate 11 and serves as the second electrode 52, or the second electrode 52 is provided on the substrate 11 and electrically connected to the second current spreading layer 22.

The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the details of the above embodiments, and various features described in the above embodiments may be combined in any suitable manner, or various different embodiments may be combined in any suitable manner or simply modified within the technical concept of the present invention, and the combination or the modification is within the protection scope of the present invention.

Claims

1. A deep ultraviolet light emitting diode comprising:

a first semiconductor layer;

a second semiconductor layer, a second current spreading layer, a bonding metal layer, and a substrate stacked on the active layer; performing high temperature annealing on the first current spreading layer and the second current spreading layer before laminating the bonding metal layer;

the first insulating protection layer extends to between the second current spreading layer and the bonding metal layer and covers the second current spreading layer;

the first current spreading layer partially covers the first semiconductor layer, and the second current spreading layer partially covers the second semiconductor layer;

2. The deep ultraviolet light emitting diode of claim 1, wherein the substrate is a conductive substrate and serves as the second electrode, and the first electrode is in contact with the first current spreading layer.

3. The deep ultraviolet light emitting diode of claim 1, wherein the substrate is a non-conductive substrate.

4. The deep ultraviolet light emitting diode of claim 3, wherein the second electrode extends through the first semiconductor layer, the active layer, and the second semiconductor layer and contacts the second current spreading layer, the second electrode being electrically insulated from the first electrode.

5. The deep ultraviolet light emitting diode of claim 4, wherein a second insulating protection layer is disposed between the second electrode and the first semiconductor layer, the active layer and the second semiconductor layer.

6. The deep ultraviolet light emitting diode of claim 3, wherein;

7. The deep ultraviolet light emitting diode of claim 6, further comprising a third electrode and a fourth electrode;

the second electrode penetrates through the first semiconductor layer, the active layer and the part, which is not covered by the second current expansion layer, of the second semiconductor layer to be in contact with the second bonding metal layer, and a second insulating protection layer is arranged between the second electrode and the first semiconductor layer as well as between the second electrode and the active layer as well as between the second electrode and the second semiconductor layer;

8. A manufacturing method of a deep ultraviolet light emitting diode is characterized by comprising the following steps:

laminating a second current spreading layer on the second semiconductor layer;

laminating a first insulating protection layer on the first current spreading layer; the first insulating protection layer extends and covers the second current spreading layer; the first current spreading layer partially covers the first semiconductor layer, and the second current spreading layer partially covers the second semiconductor layer;

9. The method according to claim 8, wherein the first semiconductor layer is made of group iii nitride, and the first current spreading layer is annealed at a first temperature of 800-1100 ℃.

10. The method of claim 8, wherein the second current spreading layer is annealed at a second temperature, wherein the second temperature is 400-600 ℃.