CN104576854A - LED (light-emitting diode) chip and forming method thereof - Google Patents
LED (light-emitting diode) chip and forming method thereof Download PDFInfo
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- CN104576854A CN104576854A CN201310499374.8A CN201310499374A CN104576854A CN 104576854 A CN104576854 A CN 104576854A CN 201310499374 A CN201310499374 A CN 201310499374A CN 104576854 A CN104576854 A CN 104576854A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 173
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims description 45
- 238000009792 diffusion process Methods 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 230000013011 mating Effects 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 7
- 230000008901 benefit Effects 0.000 abstract description 8
- 238000009434 installation Methods 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 description 17
- 239000011248 coating agent Substances 0.000 description 14
- 238000000576 coating method Methods 0.000 description 14
- 238000002347 injection Methods 0.000 description 13
- 239000007924 injection Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 230000000717 retained effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention discloses an LED (light-emitting diode) chip and a forming method thereof. The LED chip comprises a substrate, an N-type semi-conductor layer, multiple quantum wells, an electron blocking layer, a P-type semi-conductor layer, an N electrode, a P electrode and an isolation layer, wherein the area of the multiple quantum wells is smaller than that of the N-type semi-conductor layer, so that an N electrode installation area can be formed on the N-type semi-conductor layer; the P-type semi-conductor layer is provided with a linear opening, and the bottom of the linear opening is contacted with the electron blocking layer; the N electrode is formed on the N electrode installation area; the P electrode comprises a P electrode wire part, a P electrode end part and a P electrode connection part, the bottom of the linear opening is filled with the P electrode wire part, the P electrode end part is located on the P-type semi-conductor layer and at one end of an upper edge of the linear opening, and the P electrode connection part connects the P electrode end part and one end of the P electrode wire part; the isolation layer is located between the P electrode end part and the P-type semi-conductor layer and is matched with the P electrode end part in shape. The LED chip has the advantages of low drive voltage, high luminance and the like.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of LED chip and forming method thereof.
Background technology
Because LED has the advantages such as environmental protection, energy-conservation, the life-span is long, the application widely obtained.Fig. 1 is the structural representation of horizontal structure LED chip of the prior art.As shown in Figure 1, this LED chip has following feature: in (1) this epitaxial slice structure, growth has conventional n type semiconductor layer 2 '; (2) P electrode 8 ' is deposited directly on the current-diffusion layer (Current Diffusion Layer, CDL) 7 ' of the ITO material on P type semiconductor 5 ' surface, and P electrode 8 ' below is provided with SiO
2the current barrier layer (Current Blocking Layer, CBL) 6 ' of material; (3) N electrode 5 ' directly contacts n type semiconductor layer 2 '.
In this LED chip, due to the good conductivity of ITO material, and transmission diffusion is carried out in the path that electric current can select resistance minimum, so electric current can be diffused rapidly to stepped area along current-diffusion layer 7 ' surface after P electrode 8 ' is injected, and then directly under successively through p type semiconductor layer 5 ', electronic barrier layer (Electron Blocking Layer, EBL) 4 ', N electrode is entered after Multiple Quantum Well (Multiple Quantum Wells, MQW) 3 '.This phenomenon causes a series of harmful effect to LED chip.First, the current density of p type semiconductor layer 5 ' step edge and the neighbouring position of the middle N electrode of n type semiconductor layer 2 ' 5 ' is very strong, easily occurs current-crowding effect, thus causes voltage higher.Secondly, because most current is that Multiple Quantum Well 3 ' is passed through downwards by the step edge place that current barrier layer 6 ' is formed, the current density of other region (particularly central area immediately below current barrier layer 6 ') the middle injection of Multiple Quantum Well 3 ' is very low, seldom luminous, cause the luminosity of integral LED chip on the low side.
Summary of the invention
The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or at least provides a kind of useful business to select.For this reason, one object of the present invention is to propose the LED chip that a kind of driving voltage is low, luminosity is high.Another object of the present invention is the formation method proposing the LED chip that a kind of driving voltage is low, luminosity is high.
According to the LED chip of the embodiment of the present invention, can comprise with lower part: substrate; N type semiconductor layer, described n type semiconductor layer is positioned at described substrate; Multiple Quantum Well, described Multiple Quantum Well is positioned on described n type semiconductor layer, and the area of described Multiple Quantum Well is less than the area of described n type semiconductor layer, to form N electrode installing zone on described n type semiconductor layer; Electronic barrier layer, described electronic barrier layer is positioned on described Multiple Quantum Well; P type semiconductor layer, described p type semiconductor layer is positioned on described electronic barrier layer, and described p type semiconductor layer has linear opening, and the bottom of described linear opening contacts with described electronic barrier layer; N electrode, described N electrode is formed on described N electrode installing zone; P electrode, described P electrode comprises: P electrode line portion, and the bottom of described linear opening is filled in described P electrode line portion; P electrode end, described P electrode end to be positioned on described p type semiconductor layer and to be positioned at one end of described linear open upper edge; With P electrode connecting portion, described P electrode connecting portion connects the one end in described P electrode end and described P electrode line portion; And separator, described separator between described P electrode end and described p type semiconductor layer, the shape of described separator and the mating shapes of described P electrode end.
LED chip according to the above embodiment of the present invention, at least tool has the following advantages:
(1) part that extraneous electrical connection is served as in the P electrode end in P electrode is retained in p type semiconductor layer surface, and this P electrode end base is designed with separator and organizes electric current to enter Multiple Quantum Well below P electrode end, that is electric current only can flow into Multiple Quantum Well from P electrode line portion.
(2) P electrode line portion is arranged in the electronic barrier layer on adjacent Multiple Quantum Well, therefore then foreign current is directly diffused into electronic barrier layer from injection rear guiding P electrode line portion, P electrode end and injects Multiple Quantum Well, without the need to the first half through whole p type semiconductor layer and electronic barrier layer, decrease driving voltage, improve the injection efficiency of electric current thus improve luminous efficiency.
(3) structure is simple, is applicable to producing in enormous quantities.
In addition, following additional technical feature can also be had according to the LED chip of the embodiment of the present invention:
In one embodiment of the invention, described N electrode comprises: N electrode line portion, described N electrode line portion and described linear opening parallel; With N electrode end, described N electrode end is connected with the one end in described N electrode line portion.
In one embodiment of the invention, described N electrode installing zone is near the side of described LED chip, and described line style opening is near the opposite side of described LED chip.
In one embodiment of the invention, described separator extends to the sidewall of described linear opening.
In one embodiment of the invention, described n type semiconductor layer comprises: the first n type semiconductor layer, and described first n type semiconductor layer is positioned at described substrate; And second n type semiconductor layer, described second n type semiconductor layer is positioned on described first n type semiconductor layer, the doping content of wherein said first n type semiconductor layer is greater than the doping content of described second n type semiconductor layer, the area of described first n type semiconductor layer is greater than the area of described second n type semiconductor layer, to form N electrode installing zone on described first n type semiconductor layer.
In one embodiment of the invention, also comprise: N electrode current-diffusion layer, described N electrode current-diffusion layer is between described N electrode and described n type semiconductor layer, and the shape of described N electrode current-diffusion layer and the mating shapes of described N electrode.
In one embodiment of the invention, also comprise: go out photosphere, described in go out photosphere and be positioned on the region do not covered by described P electrode of described p type semiconductor layer top surface.
The formation method of the LED chip of embodiment according to a further aspect of the invention, can comprise the following steps: provide substrate; N type semiconductor layer is formed in described substrate; Multiple Quantum Well is formed on described n type semiconductor layer; Electronic barrier layer is formed on described Multiple Quantum Well; P type semiconductor layer is formed on described electronic barrier layer; Local etching is carried out to described p type semiconductor layer, electronic barrier layer and multiple quantum well layer, to expose a part for described n type semiconductor layer as N electrode installing zone; In described p type semiconductor layer, form a linear opening, the bottom of described linear opening contacts with described electronic barrier layer; On described p type semiconductor layer and the position being positioned at one end of described linear open upper edge forms patterned separator; And forming N electrode and P electrode, wherein said N electrode is positioned on described N electrode installing zone, and described P electrode comprises: P electrode line portion, and the bottom of described linear opening is filled in described P electrode line portion; P electrode end, described P electrode end to be positioned on described separator and the shape of described P electrode end and the mating shapes of described separator; With P electrode connecting portion, described P electrode connecting portion connects the one end in described P electrode end and described P electrode line portion.
The formation method of LED chip according to the above embodiment of the present invention, at least tool has the following advantages:
(1) the P electrode end in obtained LED chip in P electrode is served as the part be electrically connected with the external world and is retained in p type semiconductor layer surface, and this P electrode end base is designed with separator and organizes electric current to enter Multiple Quantum Well below P electrode end, that is electric current only can flow into Multiple Quantum Well from P electrode line portion.
(2) P electrode line portion is arranged in the electronic barrier layer on adjacent Multiple Quantum Well, therefore then foreign current is directly diffused into electronic barrier layer from injection rear guiding P electrode line portion, P electrode end and injects Multiple Quantum Well, without the need to the first half through whole p type semiconductor layer and electronic barrier layer, decrease driving voltage, improve the injection efficiency of electric current thus improve luminous efficiency.
(3) technique is simple, is applicable to producing in enormous quantities.
In addition, following additional technical feature can also be had according to the formation method of the LED chip of the embodiment of the present invention:
In one embodiment of the invention, described N electrode comprises: N electrode line portion, described N electrode line portion and described linear opening parallel; With N electrode end, described N electrode end is connected with the one end in described N electrode line portion.
In one embodiment of the invention, described N electrode installing zone is near the side of described LED chip, and described line style opening is near the opposite side of described LED chip.
In one embodiment of the invention, described separator extends to the sidewall of described linear opening.
In one embodiment of the invention, describedly form n type semiconductor layer in described substrate and comprise the following steps: form the first n type semiconductor layer in described substrate; And formed on the second n type semiconductor layer on described first n type semiconductor layer, the doping content of wherein said first n type semiconductor layer is greater than the doping content of described second n type semiconductor layer, the area of described first n type semiconductor layer is greater than the area of described second n type semiconductor layer, and described N electrode is formed on described first n type semiconductor layer.
In one embodiment of the invention, also comprise step: between described N electrode and described n type semiconductor layer, form N electrode current-diffusion layer, the shape of described N electrode current-diffusion layer and the mating shapes of described N electrode.
In one embodiment of the invention, also comprise step: described p type semiconductor layer top surface, form out photosphere on the region that do not covered by described P electrode.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is the structural representation of the LED chip of conventional flat structure;
Fig. 2 is the structural representation of the LED chip of first embodiment of the invention;
Fig. 3 a and Fig. 3 b is the electrode lay-out schematic diagram of the LED chip of one embodiment of the invention;
Fig. 4 is the structural representation of the LED chip of second embodiment of the invention;
Fig. 5 a and Fig. 5 b is structural representation and the schematic top plan view of the LED chip of third embodiment of the invention;
Fig. 6 a and Fig. 6 b is structural representation and the schematic top plan view of the LED chip of fourth embodiment of the invention;
Fig. 7 is the flow chart of the formation method of LED chip according to the embodiment of the present invention; With
Fig. 8 to Figure 13 is the detailed process schematic diagram of the formation method of LED chip according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", orientation or the position relationship of the instruction such as " counterclockwise " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise one or more these features.In describing the invention, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
LED chip of the present invention and forming method thereof is introduced in detail below in conjunction with Fig. 2 to Figure 13.
Fig. 2 is the structural representation of the LED chip of first embodiment of the invention.As shown in the figure, this LED chip can comprise with lower part: substrate 100, resilient coating 110, n type semiconductor layer 200, Multiple Quantum Well 300, electronic barrier layer 400, p type semiconductor layer 500, N electrode 600, P electrode 700 and separator 800.Resilient coating 110 is located on substrate 100.N type semiconductor layer 200 is located on resilient coating 110.Multiple Quantum Well 300 is formed on n type semiconductor layer 200, and the area of this Multiple Quantum Well 300 is less than the area of n type semiconductor layer 200, to form N electrode installing zone on n type semiconductor layer 200.Electronic barrier layer 400 is positioned on Multiple Quantum Well 300.P type semiconductor layer 500 is positioned on electronic barrier layer 400, and p type semiconductor layer 500 has linear opening, and the bottom of linear opening contacts with electronic barrier layer 400.N electrode 600 is formed in P electrode 700 on N electrode installing zone and comprises P electrode line portion 710, P electrode end 720 and P electrode connecting portion 730.Wherein, the bottom of linear opening is filled in P electrode line portion 710, and shape is long and narrow; P electrode end 720 to be positioned on p type semiconductor layer 500 and to be positioned at one end of linear open upper edge, and shape is not limit but area is unsuitable excessive, may be used for being connected with metal wire extraction electrode; P electrode connecting portion 730 is positioned at the sidewall of linear opening and P electrode end 720 is connected to the one end in P electrode line portion 710.Separator 800 between P electrode end 720 and p type semiconductor layer 500, the shape of separator 800 and the mating shapes of P electrode end 720.
It should be noted that, the material of substrate 100, resilient coating 110, n type semiconductor layer 200, Multiple Quantum Well 300, electronic barrier layer 400, p type semiconductor layer 500, N electrode 600, P electrode 700 and separator 800 and thickness, can select flexibly according to the performance of target LED chip, this technology belongs to the known of those skilled in the art, does not repeat herein.And it should be noted that, the resilient coating 110 in this embodiment is for optional and nonessential, and the resilient coating 110 hereinafter in other embodiments is like this equally.
LED chip according to the above embodiment of the present invention, at least tool has the following advantages:
(1) the P electrode end in P electrode is served as the part be electrically connected with the external world and is retained in p type semiconductor layer surface, and this P electrode end base is designed with separator and organizes electric current to enter Multiple Quantum Well below P electrode end, that is electric current only can flow into Multiple Quantum Well from P electrode line portion.
(2) P electrode line portion is arranged in the electronic barrier layer on adjacent Multiple Quantum Well, therefore then foreign current is directly diffused into electronic barrier layer from injection rear guiding P electrode line portion, P electrode end and injects Multiple Quantum Well, without the need to the first half through whole p type semiconductor layer and electronic barrier layer, decrease driving voltage, improve the injection efficiency of electric current thus improve luminous efficiency.
(3) structure is simple, is applicable to producing in enormous quantities.
Illustrated by background technology, because conventional LED chip exists the uneven situation of current spread, very easily press current-crowding effect in territory, N polar region, cause the driving voltage of LED chip higher, luminosity is on the low side.Be directed to this, the present invention designs N electrode 600 and the technical scheme of P electrode 700 in elongated shape layout and the two parallel interval comes in a kind of LED chip, diffuses to N electrode 600 equably to enable electric current from P electrode 700.For this reason, in one embodiment of the invention, N electrode 600 comprises N electrode line portion 610 and N electrode end 620.Wherein, N electrode line portion 610 and linear opening parallel, shape is long and narrow; N electrode end 620 is connected with the one end in N electrode line portion 610, and shape is not limit but area is unsuitable excessive, may be used for being connected with metal wire extraction electrode.The electrode lay-out schematic diagram of the LED chip of this embodiment can as shown in Fig. 3 a or Fig. 3 b, and in figure, arrow represents the sense of current.Preferably, adopt that electrode symmetry is better, the more uniform electrode lay-out mode shown in Fig. 3 a of current spread.Electrode lay-out entirety takes mode parallel up and down, and electric current can diffuse to N electrode line portion from P electrode line portion more equably, is not easy to occur electric current local congestion effect, avoids driving voltage higher.
In one embodiment of the invention, N electrode installing zone is near the side of LED chip, and line style opening is near the opposite side of LED chip.In the vertical view of the LED chip of this embodiment, N electrode 600 and P electrode 700 lay respectively at the not homonymy of LED chip, and electric current can be made to flow through most chip area, improve luminosity.
Fig. 4 is the structural representation of the LED chip of second embodiment of the invention.As shown in the figure, separator 800 extends to the sidewall of linear opening.Separator 800 in the LED chip of this embodiment not only prevents P electrode end 720 to Injection Current in p type semiconductor layer 500, also prevent P electrode connecting portion 730 to Injection Current in p type semiconductor layer 500, avoid electric current through p type semiconductor layer 500, be conducive to reducing driving voltage.
Fig. 5 a and Fig. 5 b is structural representation and the schematic top plan view of the LED chip of third embodiment of the invention, and in Fig. 5 a, arrow represents the sense of current.As shown in the figure, the n type semiconductor layer 200 in LED chip can comprise the first n type semiconductor layer 210 and the second n type semiconductor layer 220.First n type semiconductor layer 210 can be positioned on substrate 100.When LED chip comprises resilient coating 110, then the first n type semiconductor layer 210 is positioned on resilient coating 110.Second n type semiconductor layer 220 is positioned on the first n type semiconductor layer 210.The doping content of the first n type semiconductor layer 210 is greater than the doping content of the second n type semiconductor layer 220.The area of the first n type semiconductor layer 210 is greater than the area 220 of the second n type semiconductor layer, to form N electrode installing zone on the first n type semiconductor layer.
State on the invention in embodiment, the first n type semiconductor layer 210 can be made to be heavy dopant concentration, and the second n type semiconductor layer 220 is common doping content, and concrete concentration can be selected as required.By arranging the first n type semiconductor layer 210, electric current longitudinal (namely vertical) can be made through after Multiple Quantum Well 400 and the second n type semiconductor layer 220, by high conductive heavily doped first n type semiconductor layer 210 rapidly laterally (i.e. level) be diffused into the position of N electrode 600, minimizing voltage loss.
Fig. 6 a and Fig. 6 b is structural representation and the schematic top plan view of the LED chip of fourth embodiment of the invention, and in Fig. 6 a, arrow represents the sense of current.As shown in the figure, also can comprise N electrode current-diffusion layer 900 in LED chip and/or go out photosphere 1000.This N electrode current-diffusion layer 900 can between N electrode 600 and n type semiconductor layer 200, and the mating shapes of the shape of N electrode current-diffusion layer 900 and N electrode 600.This N electrode current-diffusion layer 900 can be made up of materials such as ITO.Go out photosphere 1000 can be positioned on the region do not covered by P electrode 700 of p type semiconductor layer 500 top surface.Go out photosphere 1000 to be made up of materials such as ITO equally.Preferably, N electrode current-diffusion layer 900 can be made and go out photosphere 1000 all to adopt ITO material, and be processed to form N electrode current-diffusion layer 900 simultaneously and go out photosphere 1000.
In LED chip according to the above embodiment of the present invention, set up N electrode current-diffusion layer 900 can make CURRENT DISTRIBUTION evenly.And the square resistance of ITO material is little, it is one of conventional EDL layer material.It should be noted that, because electric current does not flow through p type semiconductor layer 500, therefore this without the need to arranging P electrode current-diffusion layer on p type semiconductor layer 500.In this embodiment, the ITO material layer on p type semiconductor layer 500 is used as another purposes---as going out photosphere 1000.The refractive index (refractive index is about 1.8-2.0) of ITO material is between p type semiconductor layer 500(such as GaN refractive index 2.5) and surrounding air (refractive index about 1.0) between, light can be reduced and going out the total reflection on optical interface, play the effect of anti-reflection film, increase LED chip luminosity.
As shown in Figure 7, according to the formation method of the LED chip of the embodiment of the present invention, can comprise the following steps:
S1. substrate is provided.
S2. resilient coating is formed in substrate.
S3. on resilient coating, n type semiconductor layer is formed.
S4. on n type semiconductor layer, Multiple Quantum Well is formed.
S5. on Multiple Quantum Well, electronic barrier layer is formed.
S6. on electronic barrier layer, p type semiconductor layer is formed.
S7. local etching is carried out to p type semiconductor layer, electronic barrier layer and multiple quantum well layer, to expose a part for n type semiconductor layer as N electrode installing zone.
S8. in p type semiconductor layer, form a linear opening, the bottom of linear opening contacts with electronic barrier layer.
S9. on p type semiconductor layer and the position being positioned at one end of linear open upper edge forms patterned separator.
S10. N electrode and P electrode is formed.N electrode is positioned on N electrode installing zone.P electrode comprises P electrode line portion, P electrode end and P electrode connecting portion.The bottom of linear opening is filled in P electrode line portion.P electrode end to be positioned on separator and the shape of P electrode end and the mating shapes of separator.P electrode connecting portion in linear opening sidewall and P electrode end is connected to the one end in P electrode line portion.
It should be noted that, the material of substrate, resilient coating, n type semiconductor layer, Multiple Quantum Well, electronic barrier layer, p type semiconductor layer, N electrode, P electrode and separator and thickness, can select flexibly according to the performance of target LED chip, this technology belongs to the known of those skilled in the art, does not repeat herein.And it should be noted that: step S102 is optional and nonessential, if do not carry out step S102, then step S103 for directly to form n type semiconductor layer on substrate.
It should be noted that, the execution sequence of step S107, step S108 and step S109 can adjust flexibly, as required successively or perform afterwards, can not change essence of the present invention first.
The formation method of LED chip according to the above embodiment of the present invention, at least tool has the following advantages:
(1) the P electrode end in obtained LED chip in P electrode is served as the part be electrically connected with the external world and is retained in p type semiconductor layer surface, and this P electrode end base is designed with separator and organizes electric current to enter Multiple Quantum Well below P electrode end, that is electric current only can flow into Multiple Quantum Well from P electrode line portion.
(2) P electrode line portion is arranged in the electronic barrier layer on adjacent Multiple Quantum Well, therefore then foreign current is directly diffused into electronic barrier layer from injection rear guiding P electrode line portion, P electrode end and injects Multiple Quantum Well, without the need to the first half through whole p type semiconductor layer and electronic barrier layer, decrease driving voltage, improve the injection efficiency of electric current thus improve luminous efficiency.
(3) technique is simple, is applicable to producing in enormous quantities.
In one embodiment of the invention, N electrode comprises: N electrode line portion, N electrode line portion and linear opening parallel; With N electrode end, N electrode end is connected with the one end in N electrode line portion.Electrode lay-out entirety takes mode parallel up and down, and electric current can diffuse to N electrode line portion from P electrode line portion more equably, is not easy to occur electric current local congestion effect, avoids driving voltage higher.
In one embodiment of the invention, N electrode installing zone is near the side of LED chip, and line style opening is near the opposite side of LED chip.In the vertical view of the LED chip of this embodiment, N electrode and P electrode lay respectively at the not homonymy of LED chip, and electric current can be made to flow through most chip area, improve luminosity.
In one embodiment of the invention, separator extends to the sidewall of linear opening.Separator in the LED chip of this embodiment not only prevents P electrode end to Injection Current in p type semiconductor layer, also prevents P electrode connecting portion to Injection Current in p type semiconductor layer, avoids electric current through p type semiconductor layer, is conducive to reducing driving voltage.
In one embodiment of the invention, step S3 comprises the following steps: first form the first n type semiconductor layer in substrate when resilient coating (have then on resilient coating); Then formed on the second n type semiconductor layer on the first n type semiconductor layer.Wherein, the doping content of the first n type semiconductor layer is greater than the doping content of the second n type semiconductor layer, and the area of the first n type semiconductor layer is greater than the area of the second n type semiconductor layer.N electrode is formed on the first n type semiconductor layer.
In one embodiment of the invention, the formation method of LED chip can also comprise step: between N electrode and n type semiconductor layer, form N electrode current-diffusion layer, the shape of N electrode current-diffusion layer and the mating shapes of N electrode.Wherein, N electrode current-diffusion layer can be made up of ITO.Arrange N electrode current-diffusion layer can make N electrode near zone CURRENT DISTRIBUTION evenly, avoid generation current crowding effect.
In one embodiment of the invention, the formation method of LED chip also comprises step: p type semiconductor layer top surface, form out photosphere on the region that do not covered by P electrode.Wherein, go out photosphere to be made up of ITO.Setting out photosphere can make the fairing profit in LED chip derive.
It should be noted that, N electrode current-diffusion layer is set and set out photosphere can successively, rear first or carry out simultaneously, do not change essence of the present invention.When N electrode current-diffusion layer is identical with setting out photosphere material, N electrode current-diffusion layer is preferably set simultaneously and sets out photosphere.
For making those skilled in the art understand the present invention better, introduce the forming process of a GaN base LED chip in detail below in conjunction with Fig. 8 to Figure 13.
A. provide Sapphire Substrate 100, by MOCVD technique, the AlN forming ideal thickness is successively 10 as resilient coating 110, doping Si concentration
19cm
3n++GaN be 10 as the first n type semiconductor layer 210, doping Si concentration
18cm
3n-GaN be 10 as Multiple Quantum Well 300, AlGaN as electronic barrier layer 400, doped with Mg concentration as the second n type semiconductor layer 220, five cycle InGaN/GaN
17cm
3p-GaN as p type semiconductor layer 500.As shown in Figure 8, Fig. 8 is structural representation.
B. by the technique such as photoetching and etching, remove the Part portions of p type semiconductor layer 500, electronic barrier layer 400 and multiple quantum well layer 300 and the second n type semiconductor layer 220, to expose the Part portions of the first n type semiconductor layer 210, the default installation site of this part and N electrode.As shown in figures 9 a and 9b, wherein, Fig. 9 a is structural representation, and Fig. 9 b is schematic top plan view.
C. by the technique such as photoetching and etching, in p type semiconductor layer 500, form a linear opening 510, linear opening 510, near the opposite side of LED chip, contacts with electronic barrier layer 400 with the bottom of linear opening 510.The default installation site in this linear opening and P electrode line portion.As as-shown-in figures 10 a and 10b, wherein, Figure 10 a is structural representation, and Figure 10 b is schematic top plan view.
D. SiO is deposited
2material also carries out the technique such as photoetching and etching, and form separator 800 in the default installation site of P electrode end, as shown in fig. lla, Figure 11 a is structural representation.Preferably, the sidewall locations that this separator 800 can also extend to linear opening 510 (namely retains the SiO of sidewall locations
2and be not etched away), as shown in figure lib, Figure 11 b is structural representation.The schematic top plan view of device now as shown in fig. live.
E. deposit ITO material and carry out the technique such as photoetching and etching, form patterned N electrode current-diffusion layer 900 in the default installation site of N electrode, and the region above p type semiconductor layer outside P electrode predeterminated position forming out photosphere 1000.As depicted in figs. 12 a and 12b, wherein, Figure 12 a is structural representation, and Figure 12 b is schematic top plan view.
F. deposition of electrode material processing, forms N electrode (comprising N electrode line portion 610 and N electrode end 620) and P electrode (comprising P electrode line portion 710, P electrode end 720 and P electrode connecting portion 730).As shown in figure 13, Figure 13 is structural representation.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.Although illustrate and describe embodiments of the invention above, but above-described embodiment can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention when not departing from principle of the present invention and aim, revising, replacing and modification.
Claims (14)
1. a LED chip, is characterized in that, comprising:
Substrate;
N type semiconductor layer, described n type semiconductor layer is positioned at described substrate;
Multiple Quantum Well, described Multiple Quantum Well is positioned on described n type semiconductor layer, and the area of described Multiple Quantum Well is less than the area of described n type semiconductor layer, to form N electrode installing zone on described n type semiconductor layer;
Electronic barrier layer, described electronic barrier layer is positioned on described Multiple Quantum Well;
P type semiconductor layer, described p type semiconductor layer is positioned on described electronic barrier layer, and described p type semiconductor layer has linear opening, and the bottom of described linear opening contacts with described electronic barrier layer;
N electrode, described N electrode is formed on described N electrode installing zone;
P electrode, described P electrode comprises:
P electrode line portion, the bottom of described linear opening is filled in described P electrode line portion;
P electrode end, described P electrode end to be positioned on described p type semiconductor layer and to be positioned at one end of described linear open upper edge; With
P electrode connecting portion, described P electrode connecting portion connects the one end in described P electrode end and described P electrode line portion; And
Separator, described separator between described P electrode end and described p type semiconductor layer, the shape of described separator and the mating shapes of described P electrode end.
2. LED chip as claimed in claim 1, it is characterized in that, described N electrode comprises:
N electrode line portion, described N electrode line portion and described linear opening parallel; With
N electrode end, described N electrode end is connected with the one end in described N electrode line portion.
3. LED chip as claimed in claim 1, it is characterized in that, described N electrode installing zone is near the side of described LED chip, and described line style opening is near the opposite side of described LED chip.
4. LED chip as claimed in claim 1, it is characterized in that, described separator extends to the sidewall of described linear opening.
5. LED chip as claimed in claim 1, it is characterized in that, described n type semiconductor layer comprises:
First n type semiconductor layer, described first n type semiconductor layer is positioned at described substrate; And
Second n type semiconductor layer, described second n type semiconductor layer is positioned on described first n type semiconductor layer, wherein
The doping content of described first n type semiconductor layer is greater than the doping content of described second n type semiconductor layer, the area of described first n type semiconductor layer is greater than the area of described second n type semiconductor layer, to form N electrode installing zone on described first n type semiconductor layer.
6. LED chip as claimed in claim 1, is characterized in that, also comprise:
N electrode current-diffusion layer, described N electrode current-diffusion layer is between described N electrode and described n type semiconductor layer, and the shape of described N electrode current-diffusion layer and the mating shapes of described N electrode.
7. the LED chip according to any one of claim 1-6, is characterized in that, also comprises:
Go out photosphere, described in go out photosphere and be positioned on the region do not covered by described P electrode of described p type semiconductor layer top surface.
8. a formation method for LED chip, is characterized in that, comprise the following steps:
Substrate is provided;
N type semiconductor layer is formed in described substrate;
Multiple Quantum Well is formed on described n type semiconductor layer;
Electronic barrier layer is formed on described Multiple Quantum Well;
P type semiconductor layer is formed on described electronic barrier layer;
Local etching is carried out to described p type semiconductor layer, electronic barrier layer and multiple quantum well layer, to expose a part for described n type semiconductor layer as N electrode installing zone;
In described p type semiconductor layer, form a linear opening, the bottom of described linear opening contacts with described electronic barrier layer;
On described p type semiconductor layer and the position being positioned at one end of described linear open upper edge forms patterned separator; And
Form N electrode and P electrode, wherein said N electrode is positioned on described N electrode installing zone, and described P electrode comprises:
P electrode line portion, the bottom of described linear opening is filled in described P electrode line portion;
P electrode end, described P electrode end to be positioned on described separator and the shape of described P electrode end and the mating shapes of described separator; With
P electrode connecting portion, described P electrode connecting portion connects the one end in described P electrode end and described P electrode line portion.
9. the formation method of LED chip as claimed in claim 8, it is characterized in that, described N electrode comprises:
N electrode line portion, described N electrode line portion and described linear opening parallel; With
N electrode end, described N electrode end is connected with the one end in described N electrode line portion.
10. the formation method of LED chip as claimed in claim 8, it is characterized in that, described N electrode installing zone is near the side of described LED chip, and described line style opening is near the opposite side of described LED chip.
The formation method of 11. LED chips as claimed in claim 8, it is characterized in that, described separator extends to the sidewall of described linear opening.
The formation method of 12. LED chips as claimed in claim 8, is characterized in that, describedly forms n type semiconductor layer in described substrate and comprises the following steps:
The first n type semiconductor layer is formed in described substrate; And
Formed on described first n type semiconductor layer on the second n type semiconductor layer, wherein
The doping content of described first n type semiconductor layer is greater than the doping content of described second n type semiconductor layer, the area of described first n type semiconductor layer is greater than the area of described second n type semiconductor layer, and described N electrode is formed on described first n type semiconductor layer.
The formation method of 13. LED chips as claimed in claim 8, is characterized in that, also comprise step:
N electrode current-diffusion layer is formed, the shape of described N electrode current-diffusion layer and the mating shapes of described N electrode between described N electrode and described n type semiconductor layer.
The formation method of 14. LED chips according to any one of claim 8-13, is characterized in that, also comprise step:
Described p type semiconductor layer top surface, form out photosphere on the region that do not covered by described P electrode.
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| CN201310499374.8A CN104576854B (en) | 2013-10-22 | 2013-10-22 | LED chip and forming method thereof |
| PCT/CN2014/086543 WO2015058598A1 (en) | 2013-10-22 | 2014-09-15 | Led chip and method of forming same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694095A (en) * | 2011-03-22 | 2012-09-26 | 广东银雨芯片半导体有限公司 | Improved LED chip having current blocking layer and preparation method thereof |
| KR20130014692A (en) * | 2013-01-03 | 2013-02-08 | 전남대학교산학협력단 | Led chip with curvature board and led package using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694095A (en) * | 2011-03-22 | 2012-09-26 | 广东银雨芯片半导体有限公司 | Improved LED chip having current blocking layer and preparation method thereof |
| KR20130014692A (en) * | 2013-01-03 | 2013-02-08 | 전남대학교산학협력단 | Led chip with curvature board and led package using the same |
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