CN104576651A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
- Publication number
- CN104576651A CN104576651A CN201310483888.4A CN201310483888A CN104576651A CN 104576651 A CN104576651 A CN 104576651A CN 201310483888 A CN201310483888 A CN 201310483888A CN 104576651 A CN104576651 A CN 104576651A
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- capacitor
- film transistor
- insulating barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention discloses an array substrate and a preparation method thereof. The array substrate comprises a substrate, a buffer layer, a semiconductor pattern layer, a first grid electrode insulation layer, a second grid electrode insulation layer, a first conductive pattern layer, an interlayer insulation layer and a second conductive pattern layer, wherein the substrate comprises a thin-film transistor region and a capacitor region; the buffer layer is formed on the substrate; the semiconductor pattern layer is formed on the buffer layer and comprises a source and drain electrode region and a first electrode; the first grid electrode insulation layer is formed on the semiconductor pattern layer and correspondingly covers regions, except the first electrode, of the thin-film transistor region and the capacitor region; the second grid electrode insulation layer is formed on the first grid electrode insulation layer; the first conductive pattern layer is formed on the second grid electrode insulation layer and comprises a grid electrode and a second electrode; the interlayer insulation layer is formed on the first conductive pattern layer; the second conductive pattern layer is formed on the interlayer insulation layer and comprises a source electrode and a drain electrode which are coupled with the source and drain electrode region as well as a third electrode. With the adoption of the array substrate and the preparation method thereof, the capacitance of a capacitor is increased, film layer structures of the regions except the capacitor region are not changed, the signal line load is effectively decreased, and meanwhile, short-circuit risks of upper and lower film layers of the grid electrode insulation layers are reduced.
Description
Technical field
The present invention relates to a kind of low temperature polycrystalline silicon (LTPS) array base palte and preparation method thereof, particularly relate to a kind of can effective array base palte increasing electric capacity and preparation method thereof.
Background technology
The resolution requirement of people to display is more and more higher in recent years, the space correspondingly can connected up in pixel is more and more less, in pixel, capacitance size directly affects pixel electrology characteristic and then affects display characteristic, in limited layout space, therefore improves capacitance in pixel seem particularly important.
As shown in Figure 1 and Figure 2, for traditional approach forms the capacitor of array base palte and the viewgraph of cross-section of thin-film transistor film layer structure.Fig. 1 comprises glass substrate 11, is divided into thin film transistor region A and capacitor area B, and glass sinks to the bottom on 11 and forms resilient coating 12, and resilient coating 12 forms amorphous silicon layer, carries out crystallization and forms polysilicon layer, carry out P to polysilicon layer to amorphous silicon layer
-ion implantation forms semiconductor layer.Utilize the method for photoetching to form TFT semiconductors layer at thin film transistor region A and form capacitor semiconductor layer at capacitor area B, utilize and P is carried out to the capacitor semiconductor layer of light shield to B region of electrode for capacitors ion implantation
+impurity mixes, form the first electrode 14 of capacitor, then top forms first grid insulating barrier 15 and the second grid insulating barrier 16 of corresponding cover film transistor area A and capacitor area B, form capacitor second electrode 18 and thin-film transistor gate electrode 17 again, then as barrier layer, P is carried out to TFT semiconductors layer using thin-film transistor gate electrode 17
+impurity mixes, formed source electrode district 13a, drain regions 13b and due to blocking of gate electrode 17 without P
+the channel region 13c of doping.Capacitive insulation layer thickness is first grid insulating barrier 15 and second grid insulating barrier 16 thickness sum.
Fig. 2 shows the method for conventional lift capacitance, namely on Fig. 1 film layer structure basis, interlayer insulating film 19 is formed, interlayer insulating film forms source electrode 20a, drain electrode 20b and third electrode 21, second electrode 18 and the first electrode 14 form capacitor C1, second electrode 18 forms capacitor C2 with third electrode 21, and final total capacitance is that C1 adds C2.
Although adopt method shown in Fig. 2 to promote capacitance, the reduction along with Pixel Dimensions still can not meet the requirement of design.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of the array base palte preparation method and the structure thereof that promote capacitor capacitance.
Array base palte provided by the invention, comprising:
Substrate, comprises thin film transistor region and capacitor area;
Resilient coating, is formed on described substrate, cover film transistor area and capacitor area;
Semiconductor pattern layer, is formed on described resilient coating, comprises: source, drain regions, above thin film transistor region; First electrode, above capacitor area;
First grid insulating barrier, is formed on semiconductor pattern layer, the corresponding covering region of substrate except the first electrode;
Second grid insulating barrier, is formed at above first grid insulating barrier, corresponding cover film transistor area and capacitor area;
First conductive pattern layer, is formed on second grid insulating barrier, comprises: gate electrode, above thin film transistor region; Second electrode, above capacitor area;
Interlayer insulating film, is formed in the first conductive pattern layer, corresponding cover film transistor area and capacitor area;
Second conductive pattern layer, be formed on described interlayer insulating film, comprise: source electrode and drain electrode, above thin film transistor region, wherein, source electrode and drain electrode are coupled with described source, drain regions by the through hole being formed at interlayer insulating film, second grid insulating barrier and first grid insulating barrier; Third electrode, above capacitor area.
As optimal technical scheme, described source, drain regions comprise source electrode district, channel region and drain regions, and described gate electrode correspondence is formed at the top of channel region, and described source electrode is coupled with source electrode district, and described drain electrode is coupled with drain regions.
As optimal technical scheme, described substrate is glass material; Described resilient coating is silicon dioxide layer, or described resilient coating is the double-decker be made up of silicon dioxide layer and silicon nitride layer; Described semiconductor pattern layer is polysilicon material; Described first grid insulating barrier is silicon dioxide or silicon nitride; Described second grid insulating barrier is silicon dioxide or silicon nitride; Described first conductive pattern layer and the second conductive pattern layer are metal material; Described interlayer insulating film is silicon dioxide layer, silicon nitride layer, or the double-decker be made up of silicon oxide layer and silicon nitride layer.
As optimal technical scheme, described resilient coating is the double-decker that silicon dioxide layer and silicon nitride layer are formed, and silicon nitride layer thickness is 500 ~ 1000, and silicon dioxide layer thickness is 1000 ~ 2000;
As optimal technical scheme, the thickness of described semiconductor pattern layer is 500 ~ 800.
As optimal technical scheme, the thickness of described first grid insulating barrier is 800 ~ 1000.
As optimal technical scheme, the thickness of described second grid insulating barrier is 400 ~ 1000.
As optimal technical scheme, described first conductive pattern layer is individual layer MO or MO/Al/MO three-layer metal structure.
As optimal technical scheme, described second conductive pattern layer is the three-layer metal structure of Ti/Al/Ti.
The invention provides the preparation method of above-mentioned array base palte, comprising:
1) on substrate, form resilient coating, resilient coating covers thin film transistor region and the capacitor area of substrate;
2) deposition of amorphous silicon layers on the buffer layer, this amorphous silicon layer forms polysilicon layer by crystallization, utilize photoetching to be formed corresponding to the thin-film transistor polysilicon layer above thin film transistor region with corresponding to the capacitor polysilicon layer above capacitor area, then P is carried out to thin-film transistor polysilicon layer and capacitor polysilicon layer
-ion doping, forms TFT semiconductors layer and the capacitor semiconductor layer of semiconductor pattern layer;
3) on semiconductor pattern layer, an insulating barrier is formed, corresponding cover film transistor area and capacitor area, adopt capacitor first electrode light shield to carry out exposure imaging, photoresistance covers the region of described insulating barrier except above capacitor semiconductor layer, carries out P to capacitor semiconductor layer
+ion doping, forms the first electrode, and then the part of etching this insulating barrier of removing on the first electrode, forms first grid insulating barrier;
4) on first grid insulating barrier, second grid insulating barrier is formed, corresponding cover film transistor area and capacitor area;
5) on second grid insulating barrier, the first conductive pattern layer is formed, comprise gate electrode and the second electrode, gate electrode correspondence is formed at above TFT semiconductors layer, the second electrode pair should be formed with the first electrode above, using gate electrode as barrier bed, P is carried out to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping;
6) in the first conductive pattern layer, interlayer insulating film is formed, corresponding cover film transistor area and capacitor area;
7) utilize the method for photoetching, interlayer insulating film, second grid insulating barrier and first grid insulator layer etch are gone out to manifest source, the source electrode district of drain regions and the through hole of drain regions;
8) on interlayer insulating film, the second conductive pattern layer is formed, this second conductive pattern layer comprises correspondence and is formed at source electrode above thin film transistor region and drain electrode, and correspondence is formed at the third electrode above capacitor area, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
As optimal technical scheme, the insulating barrier of step 3) is silica.
As optimal technical scheme, step 5) is:
Second grid insulating barrier is formed a conductive material layer, corresponding cover film transistor area and capacitor area, then the method for photoetching is utilized to form gate electrode and second electrode of the first conductive pattern layer, gate electrode correspondence is formed at above TFT semiconductors layer, second electrode pair should be formed with the first electrode above, using gate electrode as barrier bed, P is carried out to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping.
As optimal technical scheme, step 8) is:
Interlayer insulating film is formed a conductive material layer, corresponding cover film transistor area and capacitor area, by the method for photoetching, form the second conductive pattern layer, this second conductive pattern layer comprises correspondence and is formed at source electrode above thin film transistor region and drain electrode, and correspondence is formed at the third electrode above capacitor area, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
The present invention separately provides a kind of preparation method of described array base palte, comprising:
1) on substrate, form resilient coating, resilient coating covers thin film transistor region and the capacitor area of substrate;
2) deposition of amorphous silicon layers on resilient coating, this amorphous silicon layer forms polysilicon layer by crystallization, utilize photoetching to be formed corresponding to the thin-film transistor polysilicon layer above thin film transistor region with corresponding to the capacitor polysilicon layer above capacitor area, then P is carried out to thin-film transistor polysilicon layer and capacitor polysilicon layer
-ion doping, forms TFT semiconductors layer and the capacitor semiconductor layer of semiconductor pattern layer;
3) on semiconductor pattern layer, form photoresist layer, adopt capacitor first electrode light shield to carry out exposure imaging, photoresist layer covers the region except capacitor semiconductor layer, carries out P to capacitor semiconductor layer
+ion doping forms the first electrode; After removing this photoresist layer, semiconductor pattern layer is formed an insulating barrier, corresponding thin film transistor region and the capacitor area covering substrate, adopts capacitor first electrode light shield to carry out the part of exposure imaging etching this insulating barrier of removing on the first electrode, forms first grid insulating barrier;
4) on first grid insulating barrier, second grid insulating barrier is formed, corresponding cover film transistor area and capacitor area;
5) on second grid insulating barrier, the first conductive pattern layer is formed, comprise gate electrode and the second electrode, gate electrode correspondence is formed at above TFT semiconductors layer, the second electrode pair should be formed with the first electrode above, using gate electrode as barrier bed, P is carried out to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping;
6) in the first conductive pattern layer, interlayer insulating film is formed, corresponding cover film transistor area and capacitor area;
7) utilize the method for photoetching, interlayer insulating film, second grid insulating barrier and first grid insulator layer etch are gone out to manifest source, the source electrode district of drain regions and the through hole of drain regions;
8) on interlayer insulating film, the second conductive pattern layer is formed, this second conductive pattern layer comprises correspondence and is formed at source electrode above thin film transistor region and drain electrode, and correspondence is formed at the third electrode above capacitor area, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
As optimal technical scheme, the insulating barrier of step 3) is silica or silicon nitride.
As optimal technical scheme, step 5) is:
Second grid insulating barrier is formed a conductive material layer, corresponding cover film transistor area and capacitor area, then the method for photoetching is utilized to form gate electrode and second electrode of the first conductive pattern layer, gate electrode correspondence is formed at above TFT semiconductors layer, second electrode pair should be formed with the first electrode above, carry out P using gate electrode as barrier bed to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping.
As optimal technical scheme, step 8) is:
Interlayer insulating film is formed a conductive material layer, corresponding cover film transistor area and capacitor area, by the method for photoetching, form the second conductive pattern layer, this second conductive pattern layer comprises correspondence and is formed at source electrode above thin film transistor region and drain electrode, and correspondence is formed at the third electrode above capacitor area, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
The present invention can reach following technique effect:
1, array base palte of the present invention, the light shield utilizing capacitor first electrode impurities to mix adopts the mode of single exposure or double exposure to be fallen by the region etch of corresponding for first grid insulating barrier capacitor first electrode, also the thickness of insulating layer namely reduced between the first electrode and the second electrode plays the object increasing electric capacity, can reduce the wiring space shared by electric capacity when guarantee capacitance is constant.Not only can promote the capacitance of electric capacity but also the film layer structure in other regions except capacitor regions can not be changed, the load of holding wire can be effectively reduced, the upper and lower two-layer rete short-circuit risks of gate insulator can be reduced simultaneously.
2, the preparation method of array base palte of the present invention, carries out P using gate electrode as barrier layer to source, drain regions
+ion doping, method is easier, the shortcoming that the deviation utilizing exposure imaging technology to cause in the prior art simultaneously avoided is high, precision is low.
Accompanying drawing explanation
Fig. 1 forms the capacitor of array base palte and the viewgraph of cross-section of thin-film transistor film layer structure in prior art;
Fig. 2 is the capacitor of the array base palte promoting capacitance in prior art and the viewgraph of cross-section of thin-film transistor film layer structure;
Fig. 3 A is the array base palte preparation process schematic diagram one of the embodiment of the present invention 1;
Fig. 3 B is the array base palte preparation process schematic diagram two of the embodiment of the present invention 1;
Fig. 3 C is the array base palte preparation process schematic diagram three of the embodiment of the present invention 1;
Fig. 4 A is the array base palte preparation process schematic diagram one of the embodiment of the present invention 2;
Fig. 4 B is the array base palte preparation process schematic diagram two of the embodiment of the present invention 2;
Fig. 5 is the structural representation of array base palte of the present invention.
Accompanying drawing illustrates:
11, substrate; A, thin film transistor region; B, capacitor area; 12, resilient coating; 13 ', TFT semiconductors layer; 13, source, drain regions; 13a, source electrode district; 13b, drain regions; 13c, channel region; 14 ', capacitor semiconductor layer; 14, the first electrode; 15 ', insulating barrier; 15, first grid insulating barrier; 16, second grid insulating barrier; 17, gate electrode; 18, the second electrode; 19, interlayer insulating film; 20a, source electrode; 20b, drain electrode; 21, third electrode.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, can better understand the present invention and can be implemented, but illustrated embodiment is not as a limitation of the invention to make those skilled in the art.
Below enumerate the preparation method of embodiment to array base palte of the present invention to be described.
Embodiment 1
Fig. 3 A, 3B, 3C realize for adopting single exposure mode the pixel sectional view etched away corresponding to the preparation method of first grid insulating barrier.
1) as shown in Figure 3A, substrate 11 is formed and covers the thin film transistor region A of substrate and the resilient coating 12 of capacitor area B, resilient coating 12 can by silicon dioxide (SiO
2) layer formation, can also be formed by silicon dioxide and silicon nitride (SiNx) double-layer bumper layer.
2) deposition of amorphous silicon layers on resilient coating 12, this amorphous silicon layer forms polysilicon layer by crystallization, utilize photoetching to be formed corresponding to the thin-film transistor polysilicon layer above thin film transistor region with corresponding to the capacitor polysilicon layer above capacitor area, then P is carried out to thin-film transistor polysilicon layer and capacitor polysilicon layer
-ion doping, forms TFT semiconductors layer 13 ' and the capacitor semiconductor layer 14 ' of semiconductor pattern layer.
3) on semiconductor pattern layer, an insulating barrier 15 ' is formed, corresponding cover film transistor area A and capacitor area B, adopt the light shield mixed for capacitor first electrode impurities to carry out exposure imaging and (photoresistance is applied to insulating barrier 15 ', light shield covers the region of photoresistance except capacitor semiconductor layer 14 ' top, after illumination, etching removing insulating barrier 15 ' is in the region of capacitor semiconductor layer 14 ' top), the photoresistance 31 of a-quadrant, thin-film transistor portion retains, the region of the corresponding capacitor semiconductor layer 14 ' top of insulating barrier 15 ' exposes, then P is carried out to capacitor semiconductor layer 14 '
+ion doping, forms the first electrode 14 of capacitor, then etches, etched away the insulating barrier 15 ' corresponding region above the first electrode 14, then formed as the first grid insulating barrier 15 in Fig. 3 B.
4) then carry out photoresistance stripping, be deposited on afterwards on first grid insulating barrier 15 and deposit second grid insulating barrier 16, second grid insulating barrier 16 corresponding cover film transistor area A and capacitor area B.
5) on second grid insulating barrier 16, the first conductive pattern layer is formed, it the second electrode 18 comprising the gate electrode 17 above corresponding to thin film transistor region A and correspond to above the B of capacitor area, as shown in Figure 3 C.First grid insulating barrier can be silicon dioxide (SiO
2) or other insulating layer material, second grid insulating barrier can be silicon nitride (SiNx) or other insulating layer material.Capacitor second electrode 18 and gate electrode 17 can be the three-layer metal structures of individual layer MO or MO/Al/MO.Then gate electrode 17 is utilized to carry out P as barrier bed to TFT semiconductors layer 13 '
+ion implantation, forms source electrode district 13a, the drain regions 13b of thin film transistor region as shown in FIG. 3 C and does not carry out P due to blocking of gate electrode 17
+the channel region 13c of ion doping.
6) in the first conductive pattern layer, interlayer insulating film 19 is formed, corresponding thin film transistor region A and the capacitor area B covering substrate;
7) utilize the method for photoetching, interlayer insulating film 19, second grid insulating barrier 16 and first grid insulating barrier 15 are etched the source of manifesting, the source electrode district 13a of drain regions 13 and the through hole of drain regions 13b;
8) on interlayer insulating film 19, form the second conductive pattern layer (be preferably, the three-layer metal structure of Ti/Al/Ti), this second conductive pattern layer comprises correspondence and is formed at source electrode 20a above thin film transistor region and drain electrode 20b, and correspondence is formed at the third electrode 21 above capacitor area, wherein source electrode 20a is coupled to the source electrode district 13a of source, drain regions by through hole, and drain electrode 20b is coupled to the drain regions 13b of source, drain regions by through hole.
Embodiment 2
Fig. 4 A, Fig. 4 B show and adopt double exposure mode to realize the pixel sectional view etched away corresponding to the preparation method of first grid insulating barrier.Its preparation method is substantially with embodiment 1, and difference is: step 3) applies photoresistance on semiconductor pattern layer, then adopts the light shield exposure imaging of electric capacity doping, TFT regions photoresistance is retained.Form photoresist layer 41, photoresist layer 41 covers the region except capacitor semiconductor layer 14 ', carries out P to capacitor semiconductor layer 14 '
+ion doping forms the first electrode 14; After peeling off this photoresist layer 41, semiconductor pattern layer is formed an insulating barrier 15 ', corresponding thin film transistor region and the capacitor area covering substrate, insulating barrier 15 ' photoresistance coating afterwards, adopt identical electric capacity doping light shield exposure imaging, form cross section structure photoresistance 42 shown in Fig. 4 B, then carry out etching technics, etch away the insulating barrier 15 ' corresponding region above capacitor first electrode 14, form first grid insulating barrier 15.
As shown in Figure 5, be the cross-section structure of array base palte of the present invention, comprise:
Substrate 11, comprises thin film transistor region A and capacitor area B, and substrate is glass material;
Resilient coating 12, be formed on substrate 11, cover film transistor area A and capacitor area B, resilient coating 12 can single layer structure, i.e. silicon dioxide layer, or, resilient coating 12 also can for the double-decker be made up of silicon dioxide layer and silicon nitride layer, and preferred double-decker is silicon nitride layer thickness is 500 ~ 1000, and silicon dioxide layer thickness is 1000 ~ 2000, more preferably silicon nitride layer thickness is 500, and silicon dioxide layer thickness is 1000;
Semiconductor pattern layer, for the preferred thickness of polysilicon material is 500 ~ 800, more preferably thickness is 500, is formed on resilient coating 12, comprises: source, drain regions 13, above the A of thin film transistor region; First electrode 14, above the B of capacitor area;
First grid insulating barrier 15 is silicon dioxide or silicon nitride, is formed on semiconductor pattern layer, and on the region of the whole substrate of corresponding covering except the first electrode 14, preferred thickness is 800 ~ 1000, is more preferably 800;
Second grid insulating barrier 16, be silicon dioxide or silicon nitride, preferred thickness is 400 ~ 1000, is more preferably 400, is formed at above first grid insulating barrier 15, corresponding cover film transistor area A and capacitor area B;
First conductive pattern layer, is formed on second grid insulating barrier 16, comprises: gate electrode 17, above source, drain regions 13; Second electrode 18, above the first electrode 14, its preferred thickness is 2000 ~ 4000;
Interlayer insulating film 19, is formed in the first conductive pattern layer, corresponding cover film transistor area A and capacitor area B, and its preferred thickness is 3000 ~ 6000;
Second conductive pattern layer, be formed on interlayer insulating film 19, its preferred thickness is 3000 ~ 5000, comprise: source electrode 20a and drain electrode 20b, above the A of thin film transistor region, wherein, source electrode 20a and drain electrode 20b is by being formed at interlayer insulating film 19, the through hole of second grid insulating barrier 16 and first grid insulating barrier 15 and source, drain regions 13 is coupled, source, drain regions 13 comprises source electrode district 13a, channel region 13c and drain regions 13b, gate electrode 17 correspondence is formed at the top of channel region 13c, source electrode 20a is coupled with source electrode district 13a, drain electrode 20b is coupled with drain regions 13b, third electrode 21, above the B of capacitor area.
Fig. 5 shows a kind of pixel section structure adopting the inventive method to promote the array base palte of capacitance, wherein the first electrode 14, second grid insulating barrier 16 and the second electrode 18 form the first capacitor C1, second electrode 18, interlayer insulating film 23 form the second capacitor C2 with third electrode 21, C1, C2 form parallel-connection structure, therefore pixel total capacitance Cst=C1+C2.
Therefore, adopt method of the present invention, effectively can increase capacitance, improve pixel aperture ratio and resolution, and then improve the brightness of pixel, promote the image quality of panel.Such as, capacitor first grid thickness of insulating layer is 800, second grid thickness of insulating layer is 400, when size is in 42um x126um sub-pixel, when circuit comprises six thin-film transistors and two capacitors, when the surface area of capacitor is constant, the capacitance of capacitor is original 4 times, the voltage regulation performance of holding capacitor to the grid voltage of driving transistors is better, when capacitance is constant, the surface area of capacitor can reduce 75%, this can increasing opening rate greatly for end ray structure, and difficulty is decreased for high-resolution display floater design.
More than teach a kind of preparation method of low temperature polycrystalline silicon array base palte, example explanation has been carried out mainly for thin-film transistor position, pixel region and capacitor position, but be not limited only in pixel, this preparation method is also applicable to peripheral circuit, and is also applicable to N-type TFT device.
The above embodiment is only that protection scope of the present invention is not limited thereto in order to absolutely prove the preferred embodiment that the present invention lifts.The equivalent alternative or conversion that those skilled in the art do on basis of the present invention, all within protection scope of the present invention.Protection scope of the present invention is as the criterion with claims.
Claims (9)
1. an array base palte, is characterized in that, comprising:
Substrate, comprises thin film transistor region and capacitor area;
Resilient coating, is formed on described substrate, cover film transistor area and capacitor area;
Semiconductor pattern layer, is formed on described resilient coating, comprises: source, drain regions, above thin film transistor region; First electrode, above capacitor area;
First grid insulating barrier, is formed on semiconductor pattern layer, the corresponding covering region of substrate except the first electrode;
Second grid insulating barrier, is formed at above first grid insulating barrier, corresponding cover film transistor area and capacitor area;
First conductive pattern layer, is formed on second grid insulating barrier, comprises: gate electrode, above thin film transistor region; Second electrode, above capacitor area;
Interlayer insulating film, is formed in the first conductive pattern layer, corresponding cover film transistor area and capacitor area;
Second conductive pattern layer, be formed on described interlayer insulating film, comprise: source electrode and drain electrode, above thin film transistor region, wherein, source electrode and drain electrode are coupled with described source, drain regions by the through hole being formed at interlayer insulating film, second grid insulating barrier and first grid insulating barrier; Third electrode, above capacitor area.
2. array base palte according to claim 1, it is characterized in that, described source, drain regions comprise source electrode district, channel region and drain regions, and described gate electrode correspondence is formed at the top of channel region, described source electrode is coupled with source electrode district, and described drain electrode is coupled with drain regions.
3. array base palte according to claim 1, is characterized in that, described substrate is glass material; Described resilient coating is silicon dioxide layer, or described resilient coating is the double-decker be made up of silicon dioxide layer and silicon nitride layer; Described semiconductor pattern layer is polysilicon material; Described first grid insulating barrier is silicon dioxide or silicon nitride; Described second grid insulating barrier is silicon dioxide or silicon nitride; Described first conductive pattern layer and the second conductive pattern layer are metal material; Described interlayer insulating film is silicon dioxide layer, silicon nitride layer, or the double-decker be made up of silicon oxide layer and silicon nitride layer.
4. the preparation method of array base palte described in any one of claim 1-3, is characterized in that, comprising:
1) on substrate, form resilient coating, resilient coating covers thin film transistor region and the capacitor area of substrate;
2) deposition of amorphous silicon layers on the buffer layer, this amorphous silicon layer forms polysilicon layer by crystallization, utilize photoetching to be formed corresponding to the thin-film transistor polysilicon layer above thin film transistor region with corresponding to the capacitor polysilicon layer above capacitor area, then P is carried out to thin-film transistor polysilicon layer and capacitor polysilicon layer
-ion doping, forms TFT semiconductors layer and the capacitor semiconductor layer of semiconductor pattern layer;
3) on semiconductor pattern layer, an insulating barrier is formed, corresponding cover film transistor area and capacitor area, adopt capacitor first electrode light shield to carry out exposure imaging, photoresistance covers the region of described insulating barrier except above capacitor semiconductor layer, carries out P to capacitor semiconductor layer
+ion doping, forms the first electrode, and then the part of etching this insulating barrier of removing on the first electrode, forms first grid insulating barrier;
4) on first grid insulating barrier, second grid insulating barrier is formed, corresponding cover film transistor area and capacitor area;
5) on second grid insulating barrier, the first conductive pattern layer is formed, comprise gate electrode and the second electrode, gate electrode correspondence is formed at above TFT semiconductors layer, the second electrode pair should be formed with the first electrode above, using gate electrode as barrier bed, P is carried out to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping;
6) in the first conductive pattern layer, interlayer insulating film is formed, corresponding cover film transistor area and capacitor area;
7) utilize the method for photoetching, interlayer insulating film, second grid insulating barrier and first grid insulator layer etch are gone out to manifest source, the source electrode district of drain regions and the through hole of drain regions;
8) on interlayer insulating film, the second conductive pattern layer is formed, this second conductive pattern layer comprises correspondence and is formed at source electrode above thin film transistor region and drain electrode, and correspondence is formed at the third electrode above capacitor area, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
5. method according to claim 4, is characterized in that, the insulating barrier of step 3) is silica.
6. method according to claim 4, is characterized in that, step 5) is:
Second grid insulating barrier is formed a conductive material layer, corresponding cover film transistor area and capacitor area, then the method for photoetching is utilized to form gate electrode and second electrode of the first conductive pattern layer, gate electrode correspondence is formed at above TFT semiconductors layer, second electrode pair should be formed with the first electrode above, using gate electrode as barrier bed, P is carried out to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping.
7. the preparation method of array base palte described in any one of claim 1-3, is characterized in that, comprising:
1) on substrate, form resilient coating, resilient coating covers thin film transistor region and the capacitor area of substrate;
2) deposition of amorphous silicon layers on resilient coating, this amorphous silicon layer forms polysilicon layer by crystallization, utilize photoetching to be formed corresponding to the thin-film transistor polysilicon layer above thin film transistor region with corresponding to the capacitor polysilicon layer above capacitor area, then P is carried out to thin-film transistor polysilicon layer and capacitor polysilicon layer
-ion doping, forms TFT semiconductors layer and the capacitor semiconductor layer of semiconductor pattern layer;
3) on semiconductor pattern layer, form photoresist layer, adopt capacitor first electrode light shield to carry out exposure imaging, photoresist layer covers the region except capacitor semiconductor layer, carries out P to capacitor semiconductor layer
+ion doping forms the first electrode; After removing this photoresist layer, semiconductor pattern layer is formed an insulating barrier, corresponding thin film transistor region and the capacitor area covering substrate, adopts capacitor first electrode light shield to carry out the part of exposure imaging etching this insulating barrier of removing on the first electrode, forms first grid insulating barrier;
4) on first grid insulating barrier, second grid insulating barrier is formed, corresponding cover film transistor area and capacitor area;
5) on second grid insulating barrier, the first conductive pattern layer is formed, comprise gate electrode and the second electrode, gate electrode correspondence is formed at above TFT semiconductors layer, the second electrode pair should be formed with the first electrode above, using gate electrode as barrier bed, P is carried out to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping;
6) in the first conductive pattern layer, interlayer insulating film is formed, corresponding cover film transistor area and capacitor area;
7) utilize the method for photoetching, interlayer insulating film, second grid insulating barrier and first grid insulator layer etch are gone out to manifest source, the source electrode district of drain regions and the through hole of drain regions;
8) on interlayer insulating film, the second conductive pattern layer is formed, this second conductive pattern layer comprises correspondence and is formed at source electrode above thin film transistor region and drain electrode, and correspondence is formed at the third electrode above capacitor area, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
8. method according to claim 7, is characterized in that, the insulating barrier of step 3) is silica or silicon nitride.
9. method according to claim 7, is characterized in that, step 5) is:
Second grid insulating barrier is formed a conductive material layer, corresponding cover film transistor area and capacitor area, then the method for photoetching is utilized to form gate electrode and second electrode of the first conductive pattern layer, gate electrode correspondence is formed at above TFT semiconductors layer, second electrode pair should be formed with the first electrode above, carry out P using gate electrode as barrier bed to TFT semiconductors layer
+ion doping, source electrode district, the drain regions of formation source, drain regions and do not carry out P due to blocking of gate electrode
+the channel region of ion doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310483888.4A CN104576651A (en) | 2013-10-16 | 2013-10-16 | Array substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310483888.4A CN104576651A (en) | 2013-10-16 | 2013-10-16 | Array substrate and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104576651A true CN104576651A (en) | 2015-04-29 |
Family
ID=53092328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310483888.4A Pending CN104576651A (en) | 2013-10-16 | 2013-10-16 | Array substrate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104576651A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105226055A (en) * | 2015-11-03 | 2016-01-06 | 京东方科技集团股份有限公司 | Array base palte and manufacture method, display floater and display unit |
| CN106229296A (en) * | 2016-09-12 | 2016-12-14 | 昆山工研院新型平板显示技术中心有限公司 | The forming method of metal level and tft array substrate in array base palte |
| CN108364956A (en) * | 2018-01-19 | 2018-08-03 | 昆山国显光电有限公司 | A kind of display base plate and its manufacturing method, display device |
| CN109192737A (en) * | 2018-09-10 | 2019-01-11 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display panel |
| CN109712995A (en) * | 2019-01-30 | 2019-05-03 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| WO2022148260A1 (en) * | 2021-01-08 | 2022-07-14 | 华为技术有限公司 | Thin-film transistor array substrate and preparation method therefor, and display panel |
| WO2023070741A1 (en) * | 2021-10-29 | 2023-05-04 | 惠州华星光电显示有限公司 | Manufacturing method for tft substrate, and tft substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716635A (en) * | 2004-06-29 | 2006-01-04 | 三星Sdi株式会社 | Thin film transistor and method of fabricating the same |
| US20070296003A1 (en) * | 2006-06-08 | 2007-12-27 | Samsung Electronics Co., Ltd. | Thin Film Transistor Substrate and Method for Manufacturing the Same |
| CN101123223A (en) * | 2006-08-11 | 2008-02-13 | 三星Sdi株式会社 | Method of fabricating thin film transistor array substrate |
| US20110147757A1 (en) * | 2009-12-17 | 2011-06-23 | Samsung Mobile Display Co., Ltd. | Array substrate of display device |
| US20110255044A1 (en) * | 2010-04-16 | 2011-10-20 | Samsung Mobile Display Co., Ltd. | Display device and fabrication method of the same |
-
2013
- 2013-10-16 CN CN201310483888.4A patent/CN104576651A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716635A (en) * | 2004-06-29 | 2006-01-04 | 三星Sdi株式会社 | Thin film transistor and method of fabricating the same |
| US20070296003A1 (en) * | 2006-06-08 | 2007-12-27 | Samsung Electronics Co., Ltd. | Thin Film Transistor Substrate and Method for Manufacturing the Same |
| CN101123223A (en) * | 2006-08-11 | 2008-02-13 | 三星Sdi株式会社 | Method of fabricating thin film transistor array substrate |
| US20110147757A1 (en) * | 2009-12-17 | 2011-06-23 | Samsung Mobile Display Co., Ltd. | Array substrate of display device |
| US20110255044A1 (en) * | 2010-04-16 | 2011-10-20 | Samsung Mobile Display Co., Ltd. | Display device and fabrication method of the same |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017076260A1 (en) * | 2015-11-03 | 2017-05-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, display panel, and display device |
| CN105226055B (en) * | 2015-11-03 | 2018-06-01 | 京东方科技集团股份有限公司 | Array substrate and production method, display panel and display device |
| US10134778B2 (en) | 2015-11-03 | 2018-11-20 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display panel and display device |
| CN105226055A (en) * | 2015-11-03 | 2016-01-06 | 京东方科技集团股份有限公司 | Array base palte and manufacture method, display floater and display unit |
| CN106229296A (en) * | 2016-09-12 | 2016-12-14 | 昆山工研院新型平板显示技术中心有限公司 | The forming method of metal level and tft array substrate in array base palte |
| CN108364956B (en) * | 2018-01-19 | 2021-05-18 | 昆山国显光电有限公司 | Display substrate, manufacturing method thereof and display device |
| CN108364956A (en) * | 2018-01-19 | 2018-08-03 | 昆山国显光电有限公司 | A kind of display base plate and its manufacturing method, display device |
| CN109192737A (en) * | 2018-09-10 | 2019-01-11 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display panel |
| US10803795B2 (en) | 2018-09-10 | 2020-10-13 | Ordos Yuansheng Optoelectronics Co., Ltd. | Display panel and method for preparing the same, display device |
| CN109192737B (en) * | 2018-09-10 | 2021-11-30 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
| CN109712995B (en) * | 2019-01-30 | 2021-03-09 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN109712995A (en) * | 2019-01-30 | 2019-05-03 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| WO2022148260A1 (en) * | 2021-01-08 | 2022-07-14 | 华为技术有限公司 | Thin-film transistor array substrate and preparation method therefor, and display panel |
| WO2023070741A1 (en) * | 2021-10-29 | 2023-05-04 | 惠州华星光电显示有限公司 | Manufacturing method for tft substrate, and tft substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104576651A (en) | Array substrate and preparation method thereof | |
| KR102392410B1 (en) | Display device | |
| CN102812555B (en) | Semiconductor device and method for manufacturing the same | |
| US9577011B2 (en) | Complementary metal oxide semiconductor transistor and fabricating method thereof | |
| CN105552085B (en) | A kind of pixel-driving circuit and preparation method thereof | |
| US10304860B2 (en) | Array substrate and method of forming the same | |
| US9281343B2 (en) | Thin film transistor display panel and method of manufacturing the same | |
| CN103730508A (en) | Vertical thin film transistor structure of display panel and manufacturing method of vertical thin film transistor structure | |
| WO2011043300A1 (en) | Semiconductor device and method for manufacturing same | |
| CN106098699B (en) | A kind of array substrate, its production method, display panel and preparation method thereof | |
| CN103515544A (en) | Back channel etch metal-oxide thin film transistor and process | |
| CN102623451A (en) | Pixel array substrate | |
| CN104345511B (en) | Dot structure and its manufacture method, display panel | |
| CN104485333A (en) | LTPS array substrate | |
| CN107851668B (en) | Semiconductor device and method for manufacturing the same | |
| CN100470764C (en) | Two-dimensional display semiconductor structure and producing method thereof | |
| CN103745954B (en) | Display device, array substrate and manufacturing method of array substrate | |
| CN108447874B (en) | Array substrate and its manufacturing method, display panel, electronic device | |
| CN106935549B (en) | The production method and thin-film transistor array base-plate of thin-film transistor array base-plate | |
| CN104716157A (en) | Array substrate of organic light-emitting display device and manufacturing method thereof | |
| CN104733382A (en) | Preparation method for array substrate and array substrate | |
| US20180358469A1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN109698205A (en) | Active-matrix substrate and its manufacturing method | |
| CN109690661A (en) | Active-matrix substrate and the display device for having active-matrix substrate | |
| CN101295721B (en) | Image element structure and production method of display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150429 |
|
| RJ01 | Rejection of invention patent application after publication |