CN105226055B - Array substrate and production method, display panel and display device - Google Patents

Array substrate and production method, display panel and display device Download PDF

Info

Publication number
CN105226055B
CN105226055B CN201510738246.3A CN201510738246A CN105226055B CN 105226055 B CN105226055 B CN 105226055B CN 201510738246 A CN201510738246 A CN 201510738246A CN 105226055 B CN105226055 B CN 105226055B
Authority
CN
China
Prior art keywords
array substrate
metal layer
semiconductor
width
grid line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510738246.3A
Other languages
Chinese (zh)
Other versions
CN105226055A (en
Inventor
裴晓光
刘冲
肖志莲
赵海生
彭志龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510738246.3A priority Critical patent/CN105226055B/en
Publication of CN105226055A publication Critical patent/CN105226055A/en
Priority to PCT/CN2016/104067 priority patent/WO2017076260A1/en
Priority to US15/539,773 priority patent/US10134778B2/en
Application granted granted Critical
Publication of CN105226055B publication Critical patent/CN105226055B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The present invention provides a kind of array substrate and production method, display panel and display devices, belong to display technology field.Wherein, the production method of array substrate includes：Multiple the first metal layer figures that are mutually independent, including end are formed on underlay substrate, the end is located at the non-display area of the array substrate；Insulating layer is formed on the first metal layer figure；Before depositing second metal layer, semiconductor figure corresponding with the end is formed on the insulating layer.GOA unit caused by technical scheme can reduce point discharge is damaged, and improves the yields for showing product.

Description

Array substrate and production method, display panel and display device
Technical field
The present invention relates to display technology fields, particularly relate to a kind of array substrate and production method, display panel and display Device.
Background technology
To improve the antistatic effect of display product at present at module end, by GOA (raster data model electricity during product design and development Road) drive signal line in structure is changed to be made by barrier metal layer by Source and drain metal level making, and this design causes in sedimentary origin Grid line belongs to individual line before leakage metal layer, as depicted in figs. 1 and 2, is not connected between grid line 1 and GOA unit 2, such In the case of grid line 1 introduce electrostatic due to contact or other reasons after can not discharge, can be at 1 tip of grid line close to the area of GOA unit 2 Domain is discharged, and GOA unit is caused to damage, and seriously affects the yields of display product.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of array substrate and production method, display panel and display dresses It puts, GOA unit caused by can reducing point discharge is damaged, and improves the yields for showing product.
In order to solve the above technical problems, the embodiment of the present invention offer technical solution is as follows：
On the one hand, a kind of production method of array substrate is provided, including：
Multiple the first metal layer figures that are mutually independent, including end, the end position are formed on underlay substrate In the non-display area of the array substrate；
Insulating layer is formed on the first metal layer figure；
Before depositing second metal layer, semiconductor figure corresponding with the end is formed on the insulating layer.
Further, the method further includes：
Before depositing second metal layer, the underlay substrate for being formed with the semiconductor figure is heated.
Further, it is described that multiple the first metal layer figures that are mutually independent, including end are formed on underlay substrate Shape includes：
Form the first metal layer figure of the width more than the width of other parts of end.
Further, the width for forming end is more than the first metal layer figure of the width of other parts It includes：
The figure of multiple grid lines that are mutually independent, including end is formed on underlay substrate, wherein, the end Width is more than the width of the grid line other parts, and the end is used to be connected with the gate driving circuit of the array substrate.
Further, be formed with multiple thin film transistor (TFT)s on the array substrate, it is described formed on the insulating layer with The corresponding semiconductor figure in the end includes：
Be formed simultaneously on the insulating layer by a patterning processes active layer of the thin film transistor (TFT) figure and The semiconductor figure.
The embodiment of the present invention additionally provides a kind of array substrate, including：
Multiple the first metal layer figures that are mutually independent, including end on underlay substrate, the end position In the non-display area of the array substrate；
Insulating layer on the first metal layer figure；
The semiconductor figure corresponding with the end on the insulating layer, the semiconductor figure under preset temperature Capacitance is formed with the region that the end overlaps.
Further, the width of the end is more than the width of the other parts of the first metal layer figure.
Further, the first metal layer figure is the figure of grid line, wherein, the width of the end is more than the grid The width of line other parts, the end are used to be connected with the gate driving circuit of the array substrate.
Further, multiple thin film transistor (TFT)s, the semiconductor figure and the film are formed on the array substrate The figure of the active layer of transistor is to be set with layer with material.
Further, the figure of the semiconductor figure and the active layer is using non-crystalline silicon.
The embodiment of the present invention additionally provides a kind of display panel, including array substrate as described above.
The embodiment of the present invention additionally provides a kind of display device, including array substrate as described above.
The embodiment of the present invention has the advantages that：
In said program, insulating layer is formed on multiple independent the first metal layer figures, depositing second metal layer it Before, semiconductor figure corresponding with end is formed on the insulating layer, when so being preheated before depositing second metal layer, is partly led The electric conductivity of volume graphic increases, and capacitance is formed with the region that end overlaps, and the can be reduced by way of capacitance charging The voltage value of one metal layer image end stored charge so that the charge of the first metal layer figure end accumulation is difficult that tip occurs Electric discharge is reduced GOA unit caused by being discharged due to the first metal layer figure end tip and damaged, improves the non-defective unit for showing product Rate.
Description of the drawings
Fig. 1 is the schematic layout pattern of grid line in existing array substrate；
Fig. 2 is the position relationship schematic diagram between grid line and GOA unit in existing array substrate；
Fig. 3 is the schematic diagram of stored charge in grid line and GOA unit in existing array substrate；
Fig. 4 is the position relationship schematic diagram between grid line and GOA unit in the embodiment of the present invention；
Fig. 5 is the schematic layout pattern of grid line and semiconductor figure in the embodiment of the present invention.
Reference numeral
1 grid line, 2 GOA unit, 3 drive signal line 4a-si figures
6 semiconductor figure of end of 5 grid lines
Specific embodiment
To make the embodiment of the present invention technical problems to be solved, technical solution and advantage clearer, below in conjunction with Drawings and the specific embodiments are described in detail.
The embodiment of the present invention is for grid line belongs to individual line, grid line before Source and drain metal level is deposited in the prior art It is not connected between GOA unit, grid line tip is easily discharged close to the region of GOA unit, causes what GOA unit was damaged Problem provides a kind of array substrate and production method, display panel and display device, can reduce GOA caused by point discharge Unit damages, and improves the yields for showing product.
Embodiment one
A kind of production method of array substrate is present embodiments provided, including：
Multiple the first metal layer figures that are mutually independent, including end, the end position are formed on underlay substrate In the non-display area of the array substrate；
Insulating layer is formed on the first metal layer figure；
Before depositing second metal layer, semiconductor figure corresponding with the end is formed on the insulating layer.
The present embodiment forms insulating layer on multiple independent the first metal layer figures, before depositing second metal layer, Semiconductor figure corresponding with end, when so being preheated before depositing second metal layer, semiconductor are formed on the insulating layer The electric conductivity of figure increases, and capacitance is formed with the region that end overlaps, and can reduce by first by way of capacitance charging The voltage value of metal layer image end stored charge so that the charge of the first metal layer figure end accumulation is difficult that tip occurs to put Electricity is reduced GOA unit caused by being discharged due to the first metal layer figure end tip and damaged, improves the yields for showing product.
Further, the method further includes：
Before depositing second metal layer, the underlay substrate for being formed with the semiconductor figure is heated.
At normal temperatures, the electric conductivity of semiconductor figure is poor, although the region overlapped with end can also form capacitance, But the effect for carrying out capacitance charging is little.When being preheated before depositing second metal layer, the environment residing for semiconductor figure Temperature rises to 170 degrees centigrades from room temperature, and the electric conductivity of semiconductor figure increases, capacitance can be effectively performed and fill The voltage value of the first metal layer figure end stored charge is greatly reduced in electricity.
Further, it is described that multiple the first metal layer figures that are mutually independent, including end are formed on underlay substrate Shape includes：
Form the first metal layer figure of the width more than the width of other parts of end.In the present embodiment, end Width be more than the first metal layer figure other parts width, the comparison that so corresponding semiconductor figure can also be set Width, since capacitance size is directly proportional with two capacity substrate areas, can so increase the first metal layer figure end with The size of capacitance is formed between semiconductor figure, further strengthens the effect that capacitance charges.
In specific embodiment, the width for forming end is more than the first metal layer figure of the width of other parts Including：
The figure of multiple grid lines that are mutually independent, including end is formed on underlay substrate, wherein, the end Width is more than the width of the grid line other parts, and the end is used to be connected with the gate driving circuit of the array substrate. I.e. in specific embodiment, the first metal layer figure is the figure of grid line, and the width of grid line end is more than the width of grid line other parts Degree, grid line end are located at the non-display area of array substrate and for being connected with the gate driving circuit of array substrate.
So when deposition Source and drain metal level is preheated, grid line end forms electricity with the region that semiconductor figure overlaps Hold, the voltage value of grid line end stored charge can be reduced by way of capacitance charging so that the electricity of grid line end accumulation Lotus is difficult that point discharge occurs, and reduces GOA unit caused by discharging due to grid line end tip and damages, improves and show the good of product Product rate.
Further, be formed with multiple thin film transistor (TFT)s on the array substrate, it is described formed on the insulating layer with The corresponding semiconductor figure in the end includes：
Be formed simultaneously on the insulating layer by a patterning processes active layer of the thin film transistor (TFT) figure and The semiconductor figure so can form semiconductor figure on the premise of patterning processes are not increased, save patterning processes, Reduce the production cost of product.
Embodiment two
A kind of array substrate is present embodiments provided, including：
Multiple the first metal layer figures that are mutually independent, including end on underlay substrate, the end position In the non-display area of the array substrate；
Insulating layer on the first metal layer figure；
The semiconductor figure corresponding with the end on the insulating layer.
The present embodiment forms insulating layer on multiple independent the first metal layer figures, before depositing second metal layer, Semiconductor figure corresponding with end, when so being preheated before depositing second metal layer, semiconductor are formed on the insulating layer The electric conductivity of figure increases, and capacitance is formed with the region that end overlaps, and can reduce by first by way of capacitance charging The voltage value of metal layer image end stored charge so that the charge of the first metal layer figure end accumulation is difficult that tip occurs to put Electricity is reduced GOA unit caused by being discharged due to the first metal layer figure end tip and damaged, improves the yields for showing product.
Further, the width of end is more than the width of the first metal layer figure other parts, so corresponding semiconductor Figure can also be set wider, since capacitance size is directly proportional with two capacity substrate areas, can so be increased The size of capacitance is formed between the first metal layer figure end and semiconductor figure, further strengthens the effect that capacitance charges.
In specific embodiment, the first metal layer figure is the figure of grid line, wherein, the width of the end is more than institute The width of grid line other parts is stated, the end is used to be connected with the gate driving circuit of the array substrate.So depositing When Source and drain metal level is preheated, grid line end forms capacitance with the region that semiconductor figure overlaps, and can be charged by capacitance Mode reduce the voltage value of grid line end stored charge so that the charge of grid line end accumulation is difficult that point discharge occurs, It reduces GOA unit caused by discharging due to grid line end tip to damage, improves the yields for showing product.
Further, multiple thin film transistor (TFT)s, the semiconductor figure and the film are formed on the array substrate The figure of the active layer of transistor is to be set with layer with material, and the figure of such semiconductor figure and active layer can be by once Patterning processes are formed simultaneously, and so can be formed semiconductor figure on the premise of patterning processes are not increased, be saved composition work Skill reduces the production cost of product.
In specific embodiment, semiconductor figure is using a-si for the figure with active layer.
Embodiment three
The present embodiment additionally provides a kind of display panel, including above-mentioned array substrate.The display panel can be liquid crystal Display panel or OLED display panel.
Example IV
The present embodiment additionally provides a kind of display device, including above-mentioned array substrate.The knot of display device other parts Structure may be referred to the prior art, this is not described in detail herein.The display device can be：Liquid crystal panel, Electronic Paper, liquid crystal TV, liquid crystal display, Digital Frame, mobile phone, tablet computer etc. have the product or component of any display function.
Embodiment five
The array substrate of the present invention is described further below in conjunction with the accompanying drawings：
As shown in figure 3, in the manufacturing process of existing array substrate, before Source and drain metal level is deposited, array substrate it is non- Do not connected between the grid line 1 of display area and GOA unit 2, in such cases grid line 1 due to contact or other reasons introduce it is quiet Can not be discharged after electricity can generate charge accumulation.Semiconductor electric conductivity increases after being preheated before Source and drain metal level is deposited, mono- with GOA Capacitance, drive signal line 3 and a-si figures 4 are formed between the drive signal line 3 of 2 connection of member and parallel a-si figures 4 above The respectively lower substrate and upper substrate of capacitance, if what is accumulated on grid line 1 is positive charge, then according to the corresponding a- of capacity effect Si figures 4 assemble negative electrical charge, and the tip of grid line 1 and the tip of a-si figures 4 charge with opposed polarity respectively, work as charge at this time Point discharge both after accumulation to a certain extent causes ESD (Electro-static Driven Comb), i.e. GOA ESD in array substrate production process It is bad, affect the yields of array substrate.
To solve the above-mentioned problems, using semiconductor, electric conductivity increases this characteristic, such as Fig. 4 to the present embodiment at high temperature Shown in Fig. 5, in the non-display area of array substrate, semiconductor figure 6, semiconductor figure are formed on the insulating layer on grid line 1 Shape 6 is corresponding with the end 5 of grid line towards GOA unit 2, and at normal temperatures, the electric conductivity of semiconductor figure 6 is poor, although with The overlapping region in end 5 can also form capacitance, but the effect for carrying out capacitance charging is little.
When being preheated before depositing Source and drain metal level, the environment temperature residing for semiconductor figure 6 rises to 170 from room temperature Degrees centigrade, the electric conductivity of semiconductor figure 6 increase, and forming capacitance with the region that grid line end 5 overlaps can be effectively Capacitance charging is carried out, has the characteristics that voltage value is high and charge is less using electrostatic, according to voltage value=charge value/capacitance side Formula reduces voltage value, and the charge that grid line end 5 accumulates after voltage value reduces is difficult to that point discharge occurs, and reduces due to grid line GOA unit damage caused by end 5 is discharged improves the yields of array substrate.
Further, in order to strengthen the effect of capacitance charging, the width of grid line end 5 is more than the width of grid line other parts Degree, corresponding, the width of semiconductor figure 6 is also bigger, due to capacitance size be it is directly proportional with two capacity substrate areas, The size that capacitance is formed between grid line end 5 and semiconductor figure 6 can be so effectively increased.Preferably, the width of grid line end 5 Degree can be 2-10 times of the width of grid line other parts；The size of semiconductor figure 6 changes with the size of grid line end 5 and is changed Become, it is preferable that the size of semiconductor figure 6 is equal to the size of grid line end 5.
In addition, in order not to increase the number of the patterning processes of production array substrate, semiconductor figure 6 can be with array substrate The active layer of upper thin film transistor (TFT) is set with layer with material, and such semiconductor figure 6 can be with thin film transistor (TFT) on array substrate Active layer be formed simultaneously by a patterning processes, reduce the production cost of array substrate.Due to having for thin film transistor (TFT) Active layer is generally made of a-si, and therefore, semiconductor figure 6 can also be made of a-si.Certainly, if thin film transistor (TFT) Active layer is made of other materials, and correspondingly, semiconductor figure 6 is also using the same material of active layer with thin film transistor (TFT) It is made.
The present embodiment is illustrated by grid line citing of the first metal layer figure, certainly, the first metal layer figure not office It is limited to grid line, in the manufacturing process of array substrate, after the first metal layer figure is formed, before depositing second metal layer, all Semiconductor corresponding with the first metal layer figure end can be formed on insulating layer in non-display area on the first metal layer Figure, to discharge the electrostatic of the first metal layer figure end accumulation.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art For, without departing from the principles of the present invention, several improvements and modifications can also be made, these improvements and modifications It should be regarded as protection scope of the present invention.

Claims (11)

1. a kind of production method of array substrate, which is characterized in that including：
Multiple the first metal layer figures that are mutually independent, including end are formed on underlay substrate, the end is located at institute State the non-display area of array substrate；
Insulating layer is formed on the first metal layer figure；
Before depositing second metal layer, semiconductor figure corresponding with the end is formed on the insulating layer；
The method further includes：
Before depositing second metal layer, the underlay substrate for being formed with the semiconductor figure is heated.
2. the production method of array substrate according to claim 1, which is characterized in that the formation on underlay substrate is more A the first metal layer figure that is mutually independent, including end includes：
Form the first metal layer figure of the width more than the width of other parts of end.
3. the production method of array substrate according to claim 2, which is characterized in that the width for forming end is more than The first metal layer figure of the width of other parts includes：
The figure of multiple grid lines that are mutually independent, including end is formed on underlay substrate, wherein, the width of the end More than the width of the grid line other parts, the end is used to be connected with the gate driving circuit of the array substrate.
4. the production method of array substrate according to claim 2, which is characterized in that be formed on the array substrate more A thin film transistor (TFT), the formation semiconductor figure corresponding with the end on the insulating layer include：
The figure of the active layer of the thin film transistor (TFT) and described is formed simultaneously by a patterning processes on the insulating layer Semiconductor figure.
5. a kind of array substrate, which is characterized in that be made to using the production method as any one of claim 1-4 It arrives, the array substrate includes：
Multiple the first metal layer figures that are mutually independent, including end on underlay substrate, the end is located at institute State the non-display area of array substrate；
Insulating layer on the first metal layer figure；
The semiconductor figure corresponding with the end on the insulating layer.
6. array substrate according to claim 5, which is characterized in that the width of the end is more than the first metal layer The width of the other parts of figure.
7. array substrate according to claim 6, which is characterized in that the first metal layer figure is the figure of grid line, Wherein, the width of the end is more than the width of the grid line other parts, and the end is for the grid with the array substrate Pole driving circuit connection.
8. array substrate according to claim 6, which is characterized in that multiple film crystals are formed on the array substrate The figure of pipe, the semiconductor figure and the active layer of the thin film transistor (TFT) is to be set with layer with material.
9. array substrate according to claim 8, which is characterized in that the figure of the semiconductor figure and the active layer To use non-crystalline silicon.
10. a kind of display panel, which is characterized in that including the array substrate as any one of claim 5-9.
11. a kind of display device, which is characterized in that including the array substrate as any one of claim 5-9.
CN201510738246.3A 2015-11-03 2015-11-03 Array substrate and production method, display panel and display device Active CN105226055B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510738246.3A CN105226055B (en) 2015-11-03 2015-11-03 Array substrate and production method, display panel and display device
PCT/CN2016/104067 WO2017076260A1 (en) 2015-11-03 2016-10-31 Array substrate, manufacturing method therefor, display panel, and display device
US15/539,773 US10134778B2 (en) 2015-11-03 2016-10-31 Array substrate and manufacturing method thereof, display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510738246.3A CN105226055B (en) 2015-11-03 2015-11-03 Array substrate and production method, display panel and display device

Publications (2)

Publication Number Publication Date
CN105226055A CN105226055A (en) 2016-01-06
CN105226055B true CN105226055B (en) 2018-06-01

Family

ID=54994907

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510738246.3A Active CN105226055B (en) 2015-11-03 2015-11-03 Array substrate and production method, display panel and display device

Country Status (3)

Country Link
US (1) US10134778B2 (en)
CN (1) CN105226055B (en)
WO (1) WO2017076260A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105226055B (en) * 2015-11-03 2018-06-01 京东方科技集团股份有限公司 Array substrate and production method, display panel and display device
CN105572997A (en) * 2016-02-26 2016-05-11 武汉华星光电技术有限公司 Display panel and signal wires thereof
CN105572944A (en) * 2016-03-02 2016-05-11 深圳市华星光电技术有限公司 Method for regulating size of display
CN107065339A (en) * 2016-10-27 2017-08-18 厦门天马微电子有限公司 A kind of array base palte, display panel and display device
CN107367876A (en) * 2017-08-01 2017-11-21 深圳市华星光电技术有限公司 Anti-static circuit and liquid crystal display panel
CN107425144B (en) * 2017-08-21 2020-06-05 江苏集萃有机光电技术研究所有限公司 OLED evaporation source, evaporation equipment and preparation method of OLED panel pixel array

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101504500A (en) * 2008-02-04 2009-08-12 北京京东方光电科技有限公司 Image element structure of thin-film transistor LCD array substrates
CN102338959A (en) * 2011-09-20 2012-02-01 深圳市华星光电技术有限公司 Array substrate, liquid crystal display device as well as manufacturing and repairing method of array substrate
CN104576651A (en) * 2013-10-16 2015-04-29 昆山国显光电有限公司 Array substrate and preparation method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW478014B (en) 1999-08-31 2002-03-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing thereof
JP2004302466A (en) * 2003-03-29 2004-10-28 Lg Philips Lcd Co Ltd Level electrical field applicator version liquid crystal display device and its manufacturing method
KR101661305B1 (en) * 2010-08-13 2016-09-30 삼성전자 주식회사 Semiconductor memory device having capacitor and method of fabricating the same
KR101489457B1 (en) * 2012-03-30 2015-02-04 삼성전자주식회사 Semiconductor memory device
TWI505003B (en) * 2013-06-07 2015-10-21 E Ink Holdings Inc Display panel and manufacturing method thereof
CN105226055B (en) 2015-11-03 2018-06-01 京东方科技集团股份有限公司 Array substrate and production method, display panel and display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101504500A (en) * 2008-02-04 2009-08-12 北京京东方光电科技有限公司 Image element structure of thin-film transistor LCD array substrates
CN102338959A (en) * 2011-09-20 2012-02-01 深圳市华星光电技术有限公司 Array substrate, liquid crystal display device as well as manufacturing and repairing method of array substrate
CN104576651A (en) * 2013-10-16 2015-04-29 昆山国显光电有限公司 Array substrate and preparation method thereof

Also Published As

Publication number Publication date
US20170373095A1 (en) 2017-12-28
WO2017076260A1 (en) 2017-05-11
US10134778B2 (en) 2018-11-20
CN105226055A (en) 2016-01-06

Similar Documents

Publication Publication Date Title
CN105226055B (en) Array substrate and production method, display panel and display device
CN103439840B (en) A kind of manufacture method of array base palte, display device and array base palte
EP2743766A1 (en) Array substrate, its manufacturing method, and display device
CN105629612A (en) Thin film transistor array substrate and making method thereof
CN104317089A (en) Array substrate, production method thereof, display panel and display device
CN104280951A (en) Array substrate, manufacturing method thereof, and display device
CN102929060B (en) Array substrate, fabrication method of array substrate, and display device
WO2018120543A1 (en) Method for manufacturing pixel structure
WO2014166153A1 (en) Array substrate, method for manufacture thereof and display device thereof
CN102929022A (en) Liquid crystal display device and manufacture method thereof
CN102945846A (en) Array substrate, manufacturing method thereof and display device
CN102629049B (en) Electrostatic protection structure, array substrate, liquid crystal panel and display device
CN101359670B (en) Active driving TFT matrix construction and manufacturing method thereof
CN110085584A (en) ESD protection thin film transistor (TFT) and ESD protection structure
CN103926768B (en) A kind of array base palte, display floater and display device
CN104317115A (en) Pixel structure and manufacturing method thereof, array substrate, display panel and display device
CN103185997A (en) Pixel structure and thin film transistor array substrate
CN106847829A (en) A kind of preparation method of array base palte and array base palte
WO2015000226A1 (en) Esd device manufacturing method, esd device and display panel
CN103605244B (en) Dot structure
CN110061062A (en) ESD protection thin film transistor (TFT) and ESD protection structure
CN203553175U (en) Thin film transistor, array substrate and display
CN102983102B (en) Array substrate and manufacturing method thereof, as well as display device
CN105572981B (en) array substrate, display panel and liquid crystal display device
CN104701313B (en) Array base palte and preparation method, display device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant