CN104733382A - Preparation method for array substrate and array substrate - Google Patents
Preparation method for array substrate and array substrate Download PDFInfo
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- CN104733382A CN104733382A CN201310720143.5A CN201310720143A CN104733382A CN 104733382 A CN104733382 A CN 104733382A CN 201310720143 A CN201310720143 A CN 201310720143A CN 104733382 A CN104733382 A CN 104733382A
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Abstract
The invention discloses a preparation method for an array substrate and the array substrate. The preparation method comprises that the array substrate comprises a capacitor area and a thin film transistor area, after a capacitance lower pole plate is formed by the capacitor area, a third insulation layer and a fourth insulation layer are sequentially formed on the capacitance lower pole plate, wherein the capacitor area and the thin film transistor area are covered with the third insulation layer and the fourth insulation layer; the portion, corresponding to the portion above the capacitance lower pole plate, of the fourth insulation layer is removed by etching; the fourth insulation layer is used as a barrier layer for carrying out etching on the third insulation layer, and an even thin layer is formed on the portion, corresponding to the capacitance lower pole plate, of the third insulation layer by etching. Only the thin layer which is formed by etching of the third insulation layer exists between the capacitance lower pole plate and a capacitance upper pole plate of the capacitor area of the array substrate. Due to the fact that the fourth insulation layer is used as the barrier layer for carrying out etching on the third insulation layer, the technology is simplified, and an additional photolithography technology does not need to be added. The thickness of the thin layer on the third insulation layer of the capacitor area can be maximally decreased according to the requirement of the technology, the area occupation of a pixel capacitor is reduced, and the pixel aperture opening ratio is increased.
Description
Technical field
The invention belongs to organic light emitting display field, the preparation method being specifically related to a kind of array base palte and the array base palte obtained by the method.
Background technology
Organic light emitting display (OLED) is active illuminating device.Compare present main flow flat panel display Thin Film Transistor-LCD (TFT-LCD), OLED has high-contrast, wide viewing angle, low-power consumption, the advantages such as volume is thinner, being expected to the flat panel display of future generation become after LCD, is one of the maximum technology that receives publicity in current flat panel display.In order to improve display resolution and when Pixel Dimensions is reduced, the area that may be used for placing reservior capacitor in each pixel also must relatively reduce, to keep the aperture opening ratio of pixel, therefore researcher seeks all the time by the method for the area minimization needed for the reservior capacitor of array base palte in active matrix organic light-emitting diode (AMOLED) circuit.In order to increase charge storage capacity when not affecting the aperture opening ratio of pixel; Or maintain charge storage capacity when increasing the pixel aperture ratio of organic light emitting display.And electric capacity the 4th thickness of insulating layer is thicker in the array base palte of existing AMOLED pixel circuit, causes electric capacity footprint area comparatively large, reduce pixel region aperture opening ratio.In large size along with display floater, the power consumption of display unit is more and more higher, and research finds to increase the electric current that storage capacitance effectively can increase the driving stage, thus effectively reduces power consumption; In addition, storage capacitance increases and effectively reduction can also can cause the leaping voltage of the problems such as display screen flicker, gray scale entanglement.Therefore, under the condition not affecting display unit aperture opening ratio, capacitance should be improved as far as possible.In raising capacitance, main Problems existing generally all needs increase photoetching process to become thickness to reduce in medium, causes complex process like this, and add cost at present.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of brand-new array base palte preparation method, and the array base palte utilizing the method to obtain.
The preparation method of array base palte provided by the invention, comprises the steps:
This array base palte comprises capacitor area and thin film transistor region, and capacitor area forms the 3rd insulating barrier and the 4th insulating barrier of covering capacitor district and thin film transistor region successively after forming electric capacity bottom crown on electric capacity bottom crown; 4th insulating barrier is corresponded to the partial etching removing above electric capacity bottom crown; Etching using the 4th insulating barrier as barrier layer the 3rd insulating barrier, is uniform thin layer by the partial etching corresponding to electric capacity bottom crown of the 3rd insulating barrier.
The preparation method of this array base palte also comprises the steps: the flatness layer forming covering capacitor district and thin film transistor region on the 4th insulating barrier, flatness layer is corresponded to the partial etching removing above electric capacity bottom crown; The electric capacity top crown be positioned on the thin layer of the 3rd insulating barrier is formed in capacitor area.
Particularly, as optimal technical scheme, above-mentioned preparation method comprises the steps:
1) on substrate, form resilient coating and first insulating barrier of cover film transistor area and capacitor area successively;
2) on the first insulating barrier, form the source, the drain regions that are positioned at thin film transistor region, source, drain regions comprise source electrode district, channel region and drain regions;
3) on source, drain regions, form the second insulating barrier of cover film transistor area and capacitor area;
4) formation is positioned at the gate electrode of thin film transistor region and is positioned at the electric capacity bottom crown of capacitor area over the second dielectric, and gate electrode correspondence is formed at above the channel region of source, drain regions;
5) on the layer of gate electrode and electric capacity bottom crown, form the 3rd insulating barrier of corresponding cover film transistor area and capacitor area, the 3rd insulating barrier and the second insulator layer etch are gone out to manifest source, the source electrode district of drain regions and the through hole of drain regions;
6) on the 3rd insulating barrier, form source electrode and the drain electrode of thin film transistor region, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole;
7) the 4th insulating barrier of a cover film transistor area and capacitor area is formed on the source and drain electrodes, 4th insulating barrier is etched, the through hole manifesting source electrode is formed, in capacitor area by the partial etching removing corresponded to above electric capacity bottom crown of the 4th insulating barrier in thin film transistor region;
8) with the 4th insulating barrier for three insulating barrier of barrier layer to capacitor area etches, is uniform thin layer by the partial etching corresponded to above electric capacity bottom crown of the 3rd insulating barrier.
As optimal technical scheme, step 2) for form polysilicon layer on the first insulating barrier, by the removing of the polysilicon layer of capacitor area etching, the polysilicon layer of the thin film transistor region stayed is source, drain regions, and source, drain regions comprise source electrode district, channel region and drain regions; Step 4), for form a metal level over the second dielectric, after etching, forms the gate electrode of thin film transistor region and the electric capacity bottom crown of capacitor area, and gate electrode correspondence is formed at above the channel region of source, drain regions; Step 6) for form a metal level on the 3rd insulating barrier, source electrode and the drain electrode of thin film transistor region is formed after etching, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
Preferably, above-mentioned preparation method, also comprises the steps:
9) on the 4th insulating barrier, form the flatness layer of a cover film transistor area and capacitor area, flatness layer is etched, the through hole manifesting source electrode is formed, in capacitor area by the partial etching removing corresponded to above electric capacity bottom crown of flatness layer in thin film transistor region;
10) on flatness layer, form the conductive layer of cover film transistor area, it is coupled with source electrode by the through hole being formed at the 4th insulating barrier and flatness layer, forms the electric capacity top crown be positioned on the thin layer of the 3rd insulating barrier in capacitor area.
As optimal technical scheme, step 10) for form a conductive material layer on flatness layer, conductive material layer cover film transistor area and capacitor area, and conductive material layer is coupled with source electrode by the through hole being formed at the 4th insulating barrier and flatness layer, conductive material layer is etched, form the conductive layer of cover film transistor area in thin film transistor region, form the electric capacity top crown be positioned on the thin layer of interlayer insulating film in capacitor area.
The invention provides the array base palte that above-mentioned preparation method prepares, it comprises thin film transistor region and capacitor area, and capacitor area comprises:
Electric capacity bottom crown;
3rd insulating barrier, is formed on described electric capacity bottom crown, the described capacitor area of corresponding covering, and the part corresponding to described electric capacity bottom crown of described 3rd insulating barrier is etched to uniform thin layer;
4th insulating barrier, is formed on described 3rd insulating barrier, and the part of described electric capacity bottom crown of corresponding to of described 4th insulating barrier is etched removing;
Planarization layer, is formed on described 4th insulating barrier, and the part of described electric capacity bottom crown of corresponding to of described planarization layer is etched removing;
Electric capacity top crown, is formed on the thin layer of described 3rd insulating barrier.
As optimal technical scheme, above-mentioned array base palte comprises:
Described thin film transistor region comprises:
Substrate,
Resilient coating, is formed on described substrate, the described thin film transistor region of corresponding covering;
First insulating barrier, is formed on described resilient coating, the described thin film transistor region of corresponding covering;
Source, drain regions, be formed on described first insulating barrier, described source, drain regions comprise source electrode district, channel region and drain regions;
Second insulating barrier, is formed on described source, drain regions, the described thin film transistor region of corresponding covering;
Gate electrode, is formed on described second insulating barrier, above the channel region corresponding to described source, drain regions;
3rd insulating barrier, is formed on described gate electrode, the described thin film transistor region of corresponding covering;
Source electrode and drain electrode, be formed on described 3rd insulating barrier, wherein, source electrode and drain electrode are coupled with described source, drain regions respectively by the through hole being formed at described 3rd insulating barrier and described second insulating barrier, described source electrode is coupled with described source electrode district, and described drain electrode is coupled with described drain regions;
4th insulating barrier, is formed on described source electrode and drain electrode, and the described thin film transistor region of corresponding covering, is formed with through hole above described source electrode;
Planarization layer, is formed on described 4th insulating barrier, and the described thin film transistor region of corresponding covering, is formed with through hole above described source electrode;
Conductive layer, is formed on described planarization layer, and the described thin film transistor region of corresponding covering, described conductive layer is coupled with described source electrode by the through hole being formed at described 4th insulating barrier and described planarization layer.
Described capacitor area also comprises:
Substrate,
Resilient coating, is formed on described substrate, the described capacitor area of corresponding covering;
First insulating barrier, is formed on described resilient coating, the described capacitor area of corresponding covering;
Second insulating barrier, is formed on described first insulating barrier, the described capacitor area of corresponding covering;
Wherein, electric capacity bottom crown is formed on described second insulating barrier.
Preferably, the gate electrode of described electric capacity bottom crown and described thin film transistor region is etched by same conductive material layer and is formed; The conductive layer of described electric capacity top crown and described thin film transistor region is etched by same conductive material layer and is formed.
Preferably, described substrate is glass; Described resilient coating is the MULTILAYER COMPOSITE layer that silicon nitride layer or silicon nitride layer and silicon oxide layer are formed; Described first insulating barrier is silicon oxide layer; Described second insulating barrier is a kind of or its two or more MULTILAYER COMPOSITE layer be combined to form in silicon nitride layer, silicon oxide layer or alumina layer; Described 3rd insulating barrier is a kind of or its two or more MULTILAYER COMPOSITE layer be combined to form in silicon nitride layer, silicon oxide layer or alumina layer; Described 4th insulating barrier is silicon nitride layer or alumina layer; Described electric capacity bottom crown and gate electrode are metal level or non-metallic conducting material layer (metal as aluminium, molybdenum and molybdenum and tungsten alloy, non-metal kind electric conducting material is as ITO, Graphene etc.); Described conductive layer and electric capacity top crown are transparent conductive material layer.Further preferably, described transparent conductive material is indium tin oxide or Graphene.
The present invention can reach following technique effect:
1) preparation method of array base palte provided by the invention, using the 4th insulating barrier as barrier layer, the 3rd insulating barrier is etched in capacitor area, simplify technique, do not need to increase extra photoetching process, reduce cost, the 3rd thickness of insulating layer can adjust according to technological requirement.
2) the invention provides a kind of structure of array base palte of novel organic light emitting display, its technical characteristics is that the 3rd thickness of insulating layer of capacitor area at utmost can reduce according to technological requirement, improve unit-area capacitance amount, thus reduce pixel capacitance footprint area, improve pixel aperture ratio, to improve the display quality of organic light emitting display.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte of the present invention;
Fig. 2 is preparation method's schematic diagram one of array base palte of the present invention;
Fig. 3 is preparation method's schematic diagram two of array base palte of the present invention;
Fig. 4 is preparation method's schematic diagram three of array base palte of the present invention;
Fig. 5 is preparation method's schematic diagram four of array base palte of the present invention;
Fig. 6 is preparation method's schematic diagram five of array base palte of the present invention;
Fig. 7 is preparation method's schematic diagram six of array base palte of the present invention;
Fig. 8 is preparation method's schematic diagram seven of array base palte of the present invention;
Fig. 9 is preparation method's schematic diagram eight of array base palte of the present invention;
Figure 10 is preparation method's schematic diagram nine of array base palte of the present invention;
Figure 11 is preparation method's schematic diagram ten of array base palte of the present invention;
Figure 12 is preparation method's schematic diagram 11 of array base palte of the present invention;
Figure 13 is preparation method's schematic diagram 12 of array base palte of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, can better understand the present invention and can be implemented, but illustrated embodiment is not as a limitation of the invention to make those skilled in the art.
In order to simplify the array base palte preparation technology of prior art complexity, the preparation method of array base palte of the present invention, its capacitor area forms the 3rd insulating barrier and the 4th insulating barrier in covering capacitor district successively after forming electric capacity bottom crown on electric capacity bottom crown; 4th insulating barrier is corresponded to the partial etching removing above electric capacity bottom crown; Etching using the 4th insulating barrier as barrier layer the 3rd insulating barrier, is uniform thin layer by the partial etching corresponding to electric capacity bottom crown of the 3rd insulating barrier.The present invention etches the 3rd insulating barrier using the 4th insulating barrier as barrier layer in capacitor area, Simplified flowsheet, and not needing increases extra photoetching process, reduces costs.
Shown in Fig. 2-13 and Fig. 1, describe in detail the preparation method of array base palte of the present invention, it comprises the steps:
1) substrate 10 is divided into thin film transistor region A and capacitor area B, forms resilient coating 11 over the substrate 10, resilient coating 11 cover film transistor area A and capacitor area B;
2) on resilient coating 11, form the first insulating barrier 12, first insulating barrier 12 cover film transistor area A and capacitor area B;
3) on the first insulating barrier 12, polysilicon layer is formed, by the removing of the polysilicon layer of capacitor area B etching, the polysilicon layer of the thin film transistor region A stayed is source, drain regions 13, and source, drain regions 13 comprise source electrode district 131, channel region 132 and drain regions 133;
4) on source, drain regions 13, form the second insulating barrier 14, second insulating barrier 14 cover film transistor area A and capacitor area B;
5) on the second insulating barrier 14, form a metal level 15, after etching, form the gate electrode 115 of thin film transistor region A and the electric capacity bottom crown 215 of capacitor area B, gate electrode 115 correspondence is positioned at above the channel region 132 of source, drain regions 13;
6) on the layer of gate electrode 115 and electric capacity bottom crown 215, the 3rd insulating barrier 16 is formed, 3rd insulating barrier 16 corresponding cover film transistor area A and capacitor area B, by etching, the 3rd insulating barrier 16 and the second insulating barrier 14 are etched the source of manifesting, the source electrode district 131 of drain regions 13 and the through hole of drain regions 133;
7) on the 3rd insulating barrier 16, a metal level 17 is formed, source electrode 171 and the drain electrode 172 of thin film transistor region A is formed after etching, wherein source electrode 171 is coupled to the source electrode district 131 of source, drain regions 13 by through hole, and drain electrode 172 is coupled to the drain regions 133 of source, drain regions 13 by through hole;
8) in source electrode 171 and drain electrode 172, one the 4th insulating barrier 18 is formed, cover film transistor area A and capacitor area B, 4th insulating barrier 18 is etched, the through hole manifesting source electrode 171 is formed at thin film transistor region A, removed by the partial etching corresponding to electric capacity bottom crown 215 of the 4th insulating barrier 18 at capacitor area B, remainder retains;
9) being that three insulating barrier 16 of barrier layer to capacitor area B etches with the 4th insulating barrier 18, is uniform thin layer 160 by the partial etching corresponding to electric capacity bottom crown 215 of the 3rd insulating barrier 16.
10) on the 4th insulating barrier 18, a flatness layer 19 is formed, cover film transistor area A and capacitor area B, flatness layer 19 is etched, the through hole manifesting source electrode 171 is formed at thin film transistor region A, removed by the partial etching corresponding to electric capacity bottom crown 215 of flatness layer at capacitor area B, remainder retains;
11) on flatness layer 19, a conductive material layer 20 is formed, conductive material layer 20 cover film transistor area A and capacitor area B, and conductive material layer 20 is coupled with source electrode 171 by the through hole being formed at the 4th insulating barrier 18 and flatness layer 19, conductive material layer 20 is etched, form the conductive layer 120 of cover film transistor area at thin film transistor region A, form the electric capacity top crown 220 be positioned on the thin layer 160 of the 3rd insulating barrier 16 at capacitor area B.
As shown in Figure 1, the array base palte prepared by said method, being comprised: thin film transistor region A and capacitor area B,
Thin film transistor region A comprises:
Substrate 10,
Resilient coating 11, is formed on substrate 10, corresponding cover film transistor area A;
First insulating barrier 12, is formed on resilient coating 11, corresponding cover film transistor area A;
Source, drain regions 13, be formed on the first insulating barrier 11, source, drain regions are divided into source electrode district 131, channel region 132 and drain regions 133;
Second insulating barrier 14, is formed on source, drain regions 13, corresponding cover film transistor area A, and correspondence is formed with through hole above source electrode district 131 and drain regions 132;
Gate electrode 115, is formed on the second insulating barrier 14, above the channel region 132 of source, drain regions;
3rd insulating barrier 16, is formed on gate electrode 115, corresponding cover film transistor area A, and correspondence is formed with through hole above source electrode district 131 and drain regions 132;
Source electrode 171 and drain electrode 172, be formed on the 3rd insulating barrier 16, wherein, source electrode 171 and drain electrode 172 are coupled with source, drain regions 13 respectively by the through hole being formed at the 3rd insulating barrier 16 and the second insulating barrier 14, source electrode 171 is coupled with source electrode district 131, and drain electrode 172 is coupled with drain regions 133;
4th insulating barrier 18, is formed on source electrode 171 and drain electrode 172, and corresponding cover film transistor area A, is formed with through hole above source electrode 171;
Planarization layer 19, is formed on the 4th insulating barrier 18, and corresponding cover film transistor area A, is formed with through hole above source electrode 171;
Conductive layer 120, is formed on planarization layer 19, corresponding cover film transistor area A, and conductive layer 120 is coupled with source electrode 171 by the through hole being formed at the 4th insulating barrier 18 and planarization layer 19;
Capacitor area B comprises:
Substrate 10,
Resilient coating 11, is formed on substrate 10, corresponding covering capacitor district B;
First insulating barrier 12, is formed on resilient coating 11, corresponding covering capacitor district B;
Second insulating barrier 14, is formed on the first insulating barrier, corresponding covering capacitor district B;
Electric capacity bottom crown 215, is formed on the second insulating barrier 14, and the gate electrode 115 of electric capacity bottom crown 215 and thin film transistor region A is etched by same metal level 15 and formed;
3rd insulating barrier 16, is formed on electric capacity bottom crown 215, corresponding covering capacitor district B, and the part corresponding to electric capacity bottom crown 215 of the 3rd insulating barrier 16 is etched to uniform thin layer 160;
4th insulating barrier 18, is formed on the 3rd insulating barrier 16, and the part of electric capacity bottom crown 215 of corresponding to of the 4th insulating barrier 18 is etched removing;
Planarization layer 19, is formed on the 4th insulating barrier 18, and the part of electric capacity bottom crown 215 of corresponding to of planarization layer 19 is etched removing;
Electric capacity top crown 220, is formed on the thin layer 160 of the 3rd insulating barrier 16, and electric capacity top crown 220 is etched by same conductive material layer 20 with the conductive layer 120 of thin film transistor region A and formed.
In the structure of above-mentioned array base palte, substrate 10 material can be glass; Resilient coating 11 material can be silicon nitride; The material of the first insulating barrier 12 can be silica; Source, drain regions 13 are polysilicon layer; The material of the second insulating barrier 14 can be silica, silicon nitride or aluminium oxide; The material of the 3rd insulating barrier 16 can be silica; The material of the 4th insulating barrier 18 can be silicon nitride; The material of conductive material layer 20 can be transparent conductive material, as indium tin oxide or Graphene.
Be described with the numerical result of a concrete numerical value to array base palte of the present invention.3rd insulating barrier and the 4th insulating barrier are without in the array base palte etched, there are between the electric capacity top crown of capacitor area and electric capacity bottom crown two the 4th insulating barriers: the 3rd insulating barrier (silica) thickness is 0.4 μm, the thickness 275nm of the 4th insulating barrier (silicon nitride), the capacity area in 2T1C circuit is about 160 μm * 14 μm.And the present invention is after technique etching, the thin layer 160 of the 3rd insulating barrier is only had between the electric capacity top crown 220 of capacitor area B and electric capacity bottom crown 215, when THICKNESS CONTROL when 160 is 0.1 μm, unit-area capacitance quantitative change is 3 times without etching, capacity area becomes about 40 μm * 14 μm from 160 μm * 14 μm, and aperture opening ratio is increased.And because thin layer 160 thickness arbitrarily can adjust according to technological requirement, add the flexibility of technique.
The above embodiment is only that protection scope of the present invention is not limited thereto in order to absolutely prove the preferred embodiment that the present invention lifts.The equivalent alternative or conversion that those skilled in the art do on basis of the present invention, all within protection scope of the present invention.Protection scope of the present invention is as the criterion with claims.
Claims (10)
1. a preparation method for array base palte, is characterized in that, comprises the steps:
This array base palte comprises capacitor area and thin film transistor region, and capacitor area forms the 3rd insulating barrier and the 4th insulating barrier of covering capacitor district and thin film transistor region successively after forming electric capacity bottom crown on electric capacity bottom crown; 4th insulating barrier is corresponded to the partial etching removing above electric capacity bottom crown; Etching using the 4th insulating barrier as barrier layer the 3rd insulating barrier, is uniform thin layer by the partial etching corresponding to electric capacity bottom crown of the 3rd insulating barrier.
2. preparation method according to claim 1, is characterized in that, also comprises the steps: the flatness layer forming covering capacitor district and thin film transistor region on the 4th insulating barrier, flatness layer is corresponded to the partial etching removing above electric capacity bottom crown; The electric capacity top crown be positioned on the thin layer of the 3rd insulating barrier is formed in capacitor area.
3. preparation method according to claim 1, is characterized in that, comprises the steps:
1) on substrate, form resilient coating and first insulating barrier of cover film transistor area and capacitor area successively;
2) on the first insulating barrier, form the source, the drain regions that are positioned at thin film transistor region, source, drain regions comprise source electrode district, channel region and drain regions;
3) on source, drain regions, form the second insulating barrier of cover film transistor area and capacitor area;
4) formation is positioned at the gate electrode of thin film transistor region and is positioned at the electric capacity bottom crown of capacitor area over the second dielectric, and gate electrode correspondence is formed at above the channel region of source, drain regions;
5) on the layer of gate electrode and electric capacity bottom crown, form the 3rd insulating barrier of corresponding cover film transistor area and capacitor area, the 3rd insulating barrier and the second insulator layer etch are gone out to manifest source, the source electrode district of drain regions and the through hole of drain regions;
6) on the 3rd insulating barrier, form source electrode and the drain electrode of thin film transistor region, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole;
7) the 4th insulating barrier of a cover film transistor area and capacitor area is formed on the source and drain electrodes, 4th insulating barrier is etched, the through hole manifesting source electrode is formed, in capacitor area by the partial etching removing corresponded to above electric capacity bottom crown of the 4th insulating barrier in thin film transistor region;
8) with the 4th insulating barrier for three insulating barrier of barrier layer to capacitor area etches, is uniform thin layer by the partial etching corresponded to above electric capacity bottom crown of the 3rd insulating barrier.
4. preparation method according to claim 3, it is characterized in that, step 2) for form polysilicon layer on the first insulating barrier, by the removing of the polysilicon layer of capacitor area etching, the polysilicon layer of the thin film transistor region stayed is source, drain regions, and source, drain regions comprise source electrode district, channel region and drain regions; Step 4), for form a metal level over the second dielectric, after etching, forms the gate electrode of thin film transistor region and the electric capacity bottom crown of capacitor area, and gate electrode correspondence is formed at above the channel region of source, drain regions; Step 6) for form a metal level on the 3rd insulating barrier, source electrode and the drain electrode of thin film transistor region is formed after etching, wherein source electrode is coupled to the source electrode district of source, drain regions by through hole, and drain electrode is coupled to the drain regions of source, drain regions by through hole.
5. preparation method according to claim 3, is characterized in that, also comprises the steps:
9) on the 4th insulating barrier, form the flatness layer of a cover film transistor area and capacitor area, flatness layer is etched, the through hole manifesting source electrode is formed, in capacitor area by the partial etching removing corresponded to above electric capacity bottom crown of flatness layer in thin film transistor region;
10) on flatness layer, form the conductive layer of cover film transistor area, it is coupled with source electrode by the through hole being formed at the 4th insulating barrier and flatness layer, forms the electric capacity top crown be positioned on the thin layer of the 3rd insulating barrier in capacitor area.
6. preparation method according to claim 5, it is characterized in that, step 10) for form a conductive material layer on flatness layer, conductive material layer cover film transistor area and capacitor area, and conductive material layer is coupled with source electrode by the through hole being formed at the 4th insulating barrier and flatness layer, conductive material layer is etched, forms the conductive layer of cover film transistor area in thin film transistor region, form the electric capacity top crown be positioned on the thin layer of interlayer insulating film in capacitor area.
7. the array base palte for preparing of preparation method according to claim 2, it is characterized in that, described array base palte comprises thin film transistor region and capacitor area, and described capacitor area comprises:
Electric capacity bottom crown;
3rd insulating barrier, is formed on described electric capacity bottom crown, the described capacitor area of corresponding covering, and the part corresponding to described electric capacity bottom crown of described 3rd insulating barrier is etched to uniform thin layer;
4th insulating barrier, is formed on described 3rd insulating barrier, and the part of described electric capacity bottom crown of corresponding to of described 4th insulating barrier is etched removing;
Planarization layer, is formed on described 4th insulating barrier, and the part of described electric capacity bottom crown of corresponding to of described planarization layer is etched removing;
Electric capacity top crown, is formed on the thin layer of described 3rd insulating barrier.
8. array base palte according to claim 7, is characterized in that,
Described thin film transistor region comprises:
Substrate,
Resilient coating, is formed on described substrate, the described thin film transistor region of corresponding covering;
First insulating barrier, is formed on described resilient coating, the described thin film transistor region of corresponding covering;
Source, drain regions, be formed on described first insulating barrier, described source, drain regions comprise source electrode district, channel region and drain regions;
Second insulating barrier, is formed on described source, drain regions, the described thin film transistor region of corresponding covering;
Gate electrode, is formed on described second insulating barrier, above the channel region corresponding to described source, drain regions;
3rd insulating barrier, is formed on described gate electrode, the described thin film transistor region of corresponding covering;
Source electrode and drain electrode, be formed on described 3rd insulating barrier, wherein, source electrode and drain electrode are coupled with described source, drain regions respectively by the through hole being formed at described 3rd insulating barrier and described second insulating barrier, described source electrode is coupled with described source electrode district, and described drain electrode is coupled with described drain regions;
4th insulating barrier, is formed on described source electrode and drain electrode, and the described thin film transistor region of corresponding covering, is formed with through hole above described source electrode;
Planarization layer, is formed on described 4th insulating barrier, and the described thin film transistor region of corresponding covering, is formed with through hole above described source electrode;
Conductive layer, is formed on described planarization layer, the described thin film transistor region of corresponding covering, and described conductive layer is coupled with described source electrode by the through hole being formed at described 4th insulating barrier and described planarization layer;
Described capacitor area also comprises:
Substrate,
Resilient coating, is formed on described substrate, the described capacitor area of corresponding covering;
First insulating barrier, is formed on described resilient coating, the described capacitor area of corresponding covering;
Second insulating barrier, is formed on described first insulating barrier, the described capacitor area of corresponding covering;
Wherein, electric capacity bottom crown is formed on described second insulating barrier.
9. array base palte according to claim 8, is characterized in that, the gate electrode of described electric capacity bottom crown and described thin film transistor region is etched by same conductive material layer and formed; The conductive layer of described electric capacity top crown and described thin film transistor region is etched by same conductive material layer and is formed.
10. array base palte according to claim 8, is characterized in that, described substrate is glass; Described resilient coating is the MULTILAYER COMPOSITE layer that silicon nitride layer or silicon nitride layer and silicon oxide layer are formed; Described first insulating barrier is silicon oxide layer; Described second insulating barrier is a kind of or its two or more MULTILAYER COMPOSITE layer be combined to form in silicon nitride layer, silicon oxide layer or alumina layer; Described 3rd insulating barrier is a kind of or its two or more MULTILAYER COMPOSITE layer be combined to form in silicon nitride layer, silicon oxide layer or alumina layer; Described 4th insulating barrier is silicon nitride layer or alumina layer; Described electric capacity bottom crown and gate electrode are metal level or non-metallic conducting material layer; Described conductive layer and electric capacity top crown are transparent conductive material layer.
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| CN107887398A (en) * | 2017-11-14 | 2018-04-06 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display panel and display device |
| CN109449164A (en) * | 2018-10-12 | 2019-03-08 | 深圳市华星光电半导体显示技术有限公司 | A kind of TFT substrate, display panel and display device |
| CN109742053A (en) * | 2018-12-19 | 2019-05-10 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof with capacitor |
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