CN104576568A - Semiconductor packaging piece and manufacturing method thereof - Google Patents
Semiconductor packaging piece and manufacturing method thereof Download PDFInfo
- Publication number
- CN104576568A CN104576568A CN201310481588.2A CN201310481588A CN104576568A CN 104576568 A CN104576568 A CN 104576568A CN 201310481588 A CN201310481588 A CN 201310481588A CN 104576568 A CN104576568 A CN 104576568A
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- chip
- substrate
- heat
- chip module
- electrical connection
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor packaging piece and a manufacturing method thereof. The semiconductor packaging piece comprises a substrate, a chip module, chip heat conducting glue and a heat dissipation cover, wherein the chip module is arranged on the substrate and comprises an electrically connected component, and the chip module is electrically connected to the substrate through the electrically connected component; the chip heat conducting glue is formed between the chip module and the substrate and bonds the chip module and the substrate; the heat dissipation cover is arranged on the substrate and covers the chip module.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and relate to a kind of semiconductor package part and the manufacture method thereof with conductive structure especially.
Background technology
The operating frequency of semiconductor package part now has more and more high demand, produces more heat when causing semiconductor package part to work.In order to disperse heat, the upper surface of packaging body arranges fin usually.But packaging body coats chip, make between chip and fin across packaging body.Because packaging body has certain thickness usually, make the radiating efficiency of chip not good.
Summary of the invention
The invention relates to a kind of semiconductor package part and manufacture method thereof, the problem that chip cooling efficiency is not good can be improved.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, a chip module, a chip heat-conducting glue and a dissipating cover.Chip module to be located on substrate and to be comprised an electrical connection element, and chip module is electrically connected at substrate by electrical connection element.Chip heat-conducting glue to be formed between chip module and substrate and to bind chip module and substrate.Dissipating cover to be located on substrate and to be covered chip module.
According to the present invention, a kind of manufacture method of semiconductor package part is proposed.Manufacture method comprises the following steps.One chip module is provided, chip module is formed with an electrical connection element; Form a chip heat-conducting glue on a substrate; Arrange chip module on the chip heat-conducting glue of substrate, make chip module be bonding on substrate by chip heat-conducting glue, wherein chip module is electrically connected at substrate by electrical connection element; And arrange a dissipating cover and be located on substrate, dissipating cover covers chip module.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Fig. 2 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 6 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 7 A illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 7 B illustrates the vertical view of the substrate of Fig. 7 A.
Fig. 8 A to 8E illustrates the process drawing of the semiconductor package part of Fig. 1.
Fig. 9 illustrates the process drawing of the semiconductor package part of Fig. 2.
Figure 10 A to 10B illustrates the process drawing of the semiconductor package part of Fig. 3.
Figure 11 A to 11B illustrates the process drawing of the semiconductor package part of Fig. 4.
Figure 12 A to 12G illustrates the process drawing of the semiconductor package part of Fig. 5.
Figure 13 A to 13E illustrates the process drawing of the semiconductor package part of Fig. 6.
Main element symbol description:
10: the first moulds
11: base
11a: die cavity
12: moveable block
13: flexible member
14: diffusion barrier
20: the second moulds
21: coating layer
100,200,300,400,500,600,700: semiconductor package part
110,710: substrate
111: line layer
112: conductive hole
110u, 122u, 710u: upper surface
110b, 141b, 523b: lower surface
113: louvre
112: conductive pole
114: grounding parts
115: connection pad
120,520,620: chip module
121: electrical connection element
1211,1212: part
122: the first chips
123: the second chips
123a: active surface
124,481: electrical contact
125: primer
130: chip heat-conducting glue
140: dissipating cover
141: top
142: sidepiece
150: conducting resinl
160: dissipating cover heat-conducting glue
270,370: primer
480: chip
485: viscose
521: silicon substrate
521u: surface
522: chip
523: packaging body
523u: surface
523 ': package material
714: heat dissipating layer
P1, P2: spacing
Embodiment
Please refer to Fig. 1, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises substrate 110, chip module 120, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150 and dissipating cover heat-conducting glue 160.
Substrate 110 is such as the substrate of circuit board or other kind.Substrate 110 is such as single layer substrate or multilager base plate.For multilager base plate, substrate 110 comprises several sandwich circuit layer 111 and several conductive hole 112, wherein upper and lower two line layers 111 by between conductive hole 112 be electrically connected.Substrate 110 has relative upper surface 110u and lower surface 110b.
In the present embodiment, chip module 120 is after being formed in addition, then is located on the upper surface 110u of substrate 110.Chip module 120 comprises several electrical connection element 121, and chip module 120 is electrically connected at substrate 110 by electrical connection element 121.Chip module 120 more comprises the first chip 122, second chip 123, electrical contact 124 and primer 125.Second chip 123 is located on the first chip 122 towards the orientation of the first chip 122 with its active surface 123a, and is electrically connected at the first chip 122 by electrical contact 124.Electrical contact 124 is such as soldered ball or conductive pole.Primer 125 to be formed between the first chip 122 and the second chip 123 and coated electrical contact 124, to protect this little electrical contact 124.The size of the second chip 123 is less than the first chip 122, to vacate the space at the first chip 122 edge, uses and holds electrical connection element 121.In the present embodiment, the first chip 122 covers whole second chip 123 and all electrical connection element 121, and that is, the upper surface 122u toward the first chip 122 looks, and can't see the second chip 122 and all electrical connection element 121.
Chip heat-conducting glue 130 is formed between the upper surface 110u of chip module 120 and substrate 110, with by the heat conduction of chip module 120 to outside semiconductor package part 100.In one embodiment, chip heat-conducting glue 130 is such as that grease material (grease) or colloid (gel) are made, and its coefficient of heat conduction is between 0.3W/mK to 0.6W/mK.
Chip heat-conducting glue 130 binds the upper surface 110u of chip module 120 and substrate 110, with the relative position between fixed chip module 120 and substrate 110.Substrate 110 comprises at least one louvre 113, and it extends to lower surface 110b from the upper surface 110u of substrate 110, with by outside the heat conduction of chip module 120 to semiconductor package part 100.Louvre 113 directly contact chip heat-conducting glue 130 and extend to the lower surface 110b of substrate 110 as the crow flies, uses and reduces heat and pass path, improving heat radiation efficiency.In another embodiment, also can omit louvre 113.
In addition, because the thickness of chip heat-conducting glue 130 is thin, the heat of chip module 120 can be made to conduct to substrate 110 by thin chip heat-conducting glue 130.
The upper surface 110u that dissipating cover 140 is located at substrate 110 covers chip module 120.Dissipating cover 140 is conductive radiator lids, conducting resinl 150 is formed between the upper surface 110u of dissipating cover 140 and substrate 110, and be electrically connected the grounding parts 114 of substrate 110, make dissipating cover 140 by conducting resinl 150 and grounding parts 114 ground connection, and then make dissipating cover 140 become an electromagnetic interference shield layer.
Dissipating cover 140 comprises top 141 and sidepiece 142, sidepiece 142 be connected to top 141 edge and around chip module 120.Dissipating cover 140 is located on the upper surface 110u of substrate 110 with sidepiece 142.In the present embodiment, sidepiece 142 toward the direction of substrate 110 toward outer incline, so can add the area of dissipation of dissipating cover 140 from top 141, make the heat of chip module 120 by top 141 with sidepiece 142 rapidly to flowing to the external world.In the present embodiment, dissipating cover 140 is single-pieces, and its top 141 is integrally formed the structure of shaping with sidepiece 142.In another embodiment, dissipating cover 140 can be two-piece, after its top 141 is formed respectively with sidepiece 142, then is combined by welding, bonding, engaging or other suitable method.
Conducting resinl 150 binds substrate 110 and dissipating cover 140, with the relative position of fixing base 110 with dissipating cover 140.In one embodiment, conducting resinl 150 is made up of the material that thermal conductivity is good, makes the heat of chip module 120 conduct to substrate 110 by dissipating cover 140, dissipating cover heat-conducting glue 160 and conducting resinl 150, then conduct to the external world by substrate 110.In one embodiment, conducting resinl 150 can be formed by polymer, such as, be epoxy resin.
Dissipating cover heat-conducting glue 160 is formed between the top 141 of dissipating cover 140 and chip module 120, is formed at dissipating cover 140 to bind dissipating cover heat-conducting glue 160.Specifically, dissipating cover heat-conducting glue 160 binds between the lower surface 141b at the top 141 and upper surface 122u of the first chip 122, with the relative position between fixing dissipating cover heat-conducting glue 160 and the first chip 122.In addition, because the thickness of dissipating cover heat-conducting glue 160 is thin, the heat of chip module 120 can be made to conduct to the external world by thin dissipating cover heat-conducting glue 160 and dissipating cover 140.
Please refer to Fig. 2, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 200 comprises substrate 110, chip module 120, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150, dissipating cover heat-conducting glue 160 and primer 270.
Primer 270 to be formed between the first chip 122 of chip module 120 and substrate 110 and coated electrical connection element 121 and the second chip 123.In the present embodiment, primer 270 is that capillary fills glue (Capillary Underfill, CUF), and it is formed between the first chip 122 and substrate 110 by dispensing technology after chip module 120 is located at substrate 110 again.Primer 270 fills up the space between the first chip 122 and substrate 110 by capillarity, and coated and directly contact electrical connection element 121 and the second chip 123, with complete preservation electrical connection element 121 and the second chip 123.
Please refer to Fig. 3, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 300 comprises substrate 110, chip module 120, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150, dissipating cover heat-conducting glue 160 and primer 370.
Primer 370 to be formed between the first chip 122 of chip module 120 and substrate 110 and coated electrical connection element 121.In the present embodiment, primer 370 is non-conductive adhesive (non conductive paste, or non-conductive film (non conductive film NCP), NCF), it is located at before substrate 110 in chip module 120 and is just formed on substrate 110, and then makes it be coated electrical connection element 121 after flowable state by pressure sintering.In the present embodiment, primer 370 illustrates for non-conductive film, its not coated primer 130 and second chip 123.In another embodiment, primer 370 can be non-conductive adhesive, and it can be coated and directly contact primer 130 and the second chip 123.
Please refer to Fig. 4, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 400 comprises substrate 110, chip module 120, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150, dissipating cover heat-conducting glue 160, primer 270, chip 480 and viscose 485.
Before chip module 120 is not located at substrate 110, chip 480 can be located on substrate 110 in advance.Be located at after substrate 110 until chip module 120, the second chip 123 of chip module 120 is bonding on chip 480 by viscose 485.In addition, chip 480 is located on substrate 110 in orientation down with its active surface, and be electrically connected at substrate 110 by least one electrical contact 481.Electrical contact 481 is such as conductive pole or soldered ball.In another embodiment, primer 270 can replace by primer 370.
Please refer to Fig. 5, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 500 comprises substrate 110, chip module 520, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150, dissipating cover heat-conducting glue 160.
Chip module 520 comprises at least one electrical connection element 121, silicon substrate 521, chip 522 and packaging body 523.Electrical connection element 121 and chip 522 are formed on silicon substrate 521.Be positioned at the edge of silicon substrate 521 compared to chip 522, the chip 522 in the present embodiment is positioned at the zone line of silicon substrate 521, makes the structure of semiconductor package part 500 close to symmetrical, so can reduce the amount of warpage that semiconductor package part 500 produces when thermal process.
A part for packaging body 523 coating chip 522 and electrical connection element 121, and another part of electrical connection element 121 protrudes past the lower surface 523b of packaging body 523.Because electrical connection element 121 is subject to the coated of packaging body 523, the reliability of electrical connection element 121 can be promoted, avoid chip module 520 easily to destroy (as be full of cracks) being arranged in substrate 110 process.In addition, packaging body 523 is such as formed with compression forming (compression molding) technology.
Spacing (pitch) P1 of two electrical connection element 121 of chip module 520 can between 0.3 millimeter and 0.6 millimeter, or between 0.08 millimeter or 0.15 millimeter.The actual value of the spacing P1 of two electrical connection element 121 can optic placode 110 two connection pads 115 spacing P2 and determine, the value of the embodiment of the present invention not spacing P1 of two electrical connection element 121 of limited chip module 520.
Chip heat-conducting glue 130 binds lower surface 523b and the substrate 110 of the packaging body 523 of chip module 520, makes the heat of chip 522 conduct to substrate 110 by chip heat-conducting glue 130.In the present embodiment, the not direct coated electrical connection element 121 of chip heat-conducting glue 130; So in another embodiment, chip heat-conducting glue 130 can direct coated electrical connection element 121.
Please refer to Fig. 6, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 600 comprises substrate 110, chip module 620, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150, dissipating cover heat-conducting glue 160.With the semiconductor package part 500 of Fig. 5 unlike, the chip module 620 of the present embodiment omits chip 522, and the region that chip 522 is vacateed can be formed with several electrical connection element 121, with increase chip module 520 defeated/quantity of contact of coming in and going out.In the present embodiment, the heat of chip module 620 directly conducts to substrate 110 by electrical connection element 121, connection pad 115 with louvre 113.
Please refer to Fig. 7 A, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 700 comprises substrate 710, chip module 120, chip heat-conducting glue 130, dissipating cover 140, conducting resinl 150, dissipating cover heat-conducting glue 160.
In the present embodiment, substrate 710 comprises several sandwich circuit layer 111, several conductive hole 112, several louvre 113 and heat dissipating layer 714.Heat dissipating layer 714 exposes from the upper surface 710u of substrate 710 and is connected to louvre 113.Second chip 123 of chip module 120 is located on heat dissipating layer 714 by chip heat-conducting glue 130, makes the heat of chip module 120 conduct to the external world by chip heat-conducting glue 130, heat dissipating layer 714 with louvre 113.In one embodiment, heat dissipating layer 714 formed by copper, nickel or other metal.
Please refer to Fig. 7 B, it illustrates the vertical view of the substrate of Fig. 7 A.As seen from the figure, heat dissipating layer 714 is a complete heat-conducting layer (without pierced pattern) and provides a large area of dissipation, makes the heat of chip module 120 can conduct to the external world rapidly.
Please refer to Fig. 8 A to 8E, it illustrates the process drawing of the semiconductor package part 100 of Fig. 1.
As shown in Figure 8 A, provide chip module 120, wherein chip module 120 comprises several electrical connection element 121, first chip 122, second chip 123, electrical contact 124 and primer 125.Second chip 123 is located on the first chip 122 with its active surface 123a towards the orientation of the first chip 122; and be electrically connected at the first chip 122 by electrical contact 124; primer 125 to be formed between the first chip 122 and the second chip 123 and coated electrical contact 124, to protect this little electrical contact 124.In addition, the size of the second chip 123 is less than the first chip 122, to vacate the space at the first chip 122 edge, thus can hold electrical connection element 121.
As shown in Figure 8 B, can adopt is such as dispensing technology, forms chip heat-conducting glue 130 on the upper surface 110u of substrate 110.Substrate 110 comprises several sandwich circuit layer 111, several conductive pole 112 and several louvre 113.It is inner that this little line layer 111 laterally extends substrate 110, and two line layers 111 is electrically connected by conductive pole 112.Louvre 113 straightly runs through substrate 110.Chip heat-conducting glue 130 is the region of corresponding louvre 113 and is formed on the upper surface 110u of substrate 110, makes the heat conducting to chip heat-conducting glue 130 can conduct to louvre 113 by short path, then is conducted to outside substrate 110 by louvre 113.In one embodiment, can form the chip heat-conducting glue 130 (looking toward overlooking direction) of two chi structures, so this is not used to limit the embodiment of the present invention.
As shown in Figure 8 C, can adopt is such as surperficial coating technique (Surface-mount technology, SMT), after the chip module 120 of transposition Fig. 8 A, arranges chip module 120 on the upper surface 110u of substrate 110.Because chip module 120 is through transposition, chip module 120 can be made to be located on substrate 110 with the orientation of the second chip 123 towards substrate 110.Second chip 123 of chip module 120 is aimed at chip heat-conducting glue 130 and is arranged, to be bonding on substrate 110 by chip heat-conducting glue 130.In addition, electrical connection element 121 is such as tin solder, and it is in reflow process Post RDBMS.Electrical connection element 121 is contacted with substrate 110, and chip module 120 can be made to be electrically connected at substrate 110 by electrical connection element 121.
As in fig. 8d, can adopt is such as dispensing technology, and formation conducting resinl 150 is on the upper surface 110u of substrate 110 and form dissipating cover heat-conducting glue 160 on the first chip 122 of chip module 120.Conducting resinl 150 is formed on the grounding parts 114 of substrate 110, makes conducting resinl 150 by grounding parts 114 ground connection.
As illustrated in fig. 8e, can adopt is such as surperficial coating technique, dissipating cover 140 is set on substrate 110, wherein dissipating cover 140 is bonding on substrate 110 by conducting resinl 150, and be bonding on the first chip 122 of chip module 120 by dissipating cover heat-conducting glue 160, and then by thermal process Curing conductive adhesive 150 and dissipating cover heat-conducting glue 160, make dissipating cover 140 be fixed on chip module 120 and substrate 110, to form the semiconductor package part 100 shown in Fig. 1.In addition, dissipating cover 140 is by the grounding parts 114 of conducting resinl 150 and substrate 110 and ground connection.
Please refer to Fig. 9, it illustrates the process drawing of the semiconductor package part 200 of Fig. 2.Be located at after on substrate 110 at chip module 120, can adopt is such as dispensing technology, forms primer 270 coated electrical connection element 121, second chip 123 and primer 125, and by thermal process solidification primer 270.
In the present embodiment; primer 270 is that capillary fills glue; it fills up the space between the first chip 122 and substrate 110 by capillarity, and coated and directly contact electrical connection element 121 and the second chip 123, with complete preservation electrical connection element 121 and the second chip 123.
All the other manufacturing steps of the semiconductor package part 200 of Fig. 2, similar in appearance to the corresponding step of semiconductor package part 100, hold this and repeat no more.
Please refer to Figure 10 A to 10B, it illustrates the process drawing of the semiconductor package part 300 of Fig. 3.
As shown in Figure 10 A, can dispensing technology be adopted, form chip heat-conducting glue 130 on the upper surface 110u of substrate 110, to bind the chip module 120 of follow-up setting.In addition, primer 370 can be set on the upper surface 110u of substrate 110, with the electrical connection element 121 of coated follow-up formation.In the present embodiment, primer 370 is such as non-conductive film.
As shown in Figure 10 B, can adopt is such as surperficial coating technique, arranges chip module 120 on substrate 110, and wherein the second chip 123 of chip module 120 is bonding on the upper surface 110u of substrate 110 by chip heat-conducting glue 130.In the present embodiment, primer 370 (non-conductive film) is coated electrical connection element 121 by pressure sintering generation mobility.
In another embodiment, the primer 370 of Figure 10 A is non-conductive adhesive, and it is in B-stage (B-stage).The primer 370 with B-stage characteristic can be heated to soften, in a liquid also swellable, but can not dissolve completely and melting.In addition, the primer 370 of B-stage characteristic presents semisolid (as such as in jelly colloidal state) in appearance, and the stability had to a certain degree can not be stained with easily and be bonded to other objects, but not yet reaches completely crued phase (that is C stage).The primer 370 with B-stage characteristic produces mobility and coated electrical connection element 121 and the second chip 123 by pressure sintering, and its coated state is similar to the coated state of the primer 270 of Fig. 2.
All the other manufacturing steps of the semiconductor package part 300 of Fig. 3, similar in appearance to the corresponding step of semiconductor package part 100, hold this and repeat no more.
Please refer to Figure 11 A to 11B, it illustrates the process drawing of the semiconductor package part 400 of Fig. 4.
As shown in Figure 11 A, can adopt is such as surperficial coating technique, arranges chip 480 on the upper surface 110u of substrate 110, and its chips 480 is located on substrate 110 in orientation down with its active surface, and be electrically connected at substrate 110 by least one electrical contact 481.
As shown in Figure 11 A, can adopt is such as dispensing technology, forms viscose 485 on the upper surface 480u of chip 480, to bind the chip module 120 of follow-up formation.
As shown in Figure 11 B, can adopt is such as surperficial coating technique, arranges chip module 120 on substrate 110, and wherein the second chip 123 of chip module 120 is bonding on chip 480 by viscose 485.
All the other manufacturing steps of the semiconductor package part 400 of Fig. 4, similar in appearance to the corresponding step of semiconductor package part 100, hold this and repeat no more.
Please refer to Figure 12 A to 12G, it illustrates the process drawing of the semiconductor package part of Fig. 5.
As illustrated in fig. 12, provide silicon substrate 521, wherein silicon substrate 521 is formed with several electrical connection element 121.
As illustrated in fig. 12, can adopt is such as surperficial coating technique, arranges chip 522 on silicon substrate 521, its chips 522 by several electrical connection element 121 around.
As shown in Figure 12 B, can adopt is such as dispensing technology, forms package material 523 ' on the upper surface 522u of chip 522.Package material 523 ' can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-based resin), silicone (silicone-based resin) or other suitable coverings.Package material 523 ' also can comprise suitable filler, such as, be the silicon dioxide of powdery.
As indicated in fig. 12 c, the structure of Figure 12 B is set in the first mould 10.First mould 10 comprises base 11, moveable block 12, flexible member 13 and diffusion barrier 14.Moveable block 12 is connected to base 11 by flexible member 13, and by flexible member 13, moveable block 12 respect thereto 11 is movable.In addition, form die cavity 11a between base 11 and moveable block 12, the structure of Figure 12 B can be located in die cavity 11a.Diffusion barrier 14 is located on the madial wall of die cavity 11a.After the structure of Figure 12 B is located at die cavity 11a, diffusion barrier 14 is between the madial wall and silicon substrate 521 of die cavity 11a, and make in follow-up releasing process, silicon substrate 521 is easy from mould.
There is provided one second mould 20, it comprises coating layer 21, and it is in order to extrude package material 523 ' and to contact with electrical connection element 121.Coating layer 21 has compressive characteristics, and when after the first mould 10 and the second mould 20 matched moulds, a part 1211 for electrical connection element 121 can be absorbed in coating layer 21.
As indicated in fig. 12d, matched moulds first mould 10 and the second mould 20, make the second mould 20 press in package material 523 ', and heat package material 523 ' simultaneously, makes it produce mobility and coated electrical connection element 121.So far, chip module 520 is formed.A part 1211 due to electrical connection element 121 is absorbed in coating layer 21, therefore another part 1212 of the coated electrical connection element 121 of package material 523 ', make a part 1211 for electrical connection element 121 protrude past the surperficial 523u of package material 523 '.Because moveable block 12 opposite base 11 is movable, therefore the part 1211 that can control electrical connection element 121 is absorbed in the volume in coating layer 21.In addition, the thickness by designing coating layer 21 also can obtain similar effect.
In matched moulds process, coating layer 21 extrudes package material 523 ', makes it be oppressed and moves toward two effluents, and then accelerating its coated electrical connection element 121.
To be such as 175 degree of heating package material Celsius 523 ' about 30 to 60 second during matched moulds, with precuring package material 523 '.
As shown in figure 12e, the first mould 10 (Figure 12 D) and the second mould 20 (Figure 12 D) is separated, to take out chip module 520.Then, chip module 520 is put into baking box, to be such as 175 degree of continuous heating chip modules 520 Celsius about 4 hours, form packaging body 523 with complete cure package body material 523 '.
As shown in Figure 12 F, can adopt is such as dispensing technology, forms chip heat-conducting glue 130 on the upper surface 110u of substrate 110.
As shown in fig. 12g, can adopt is such as surperficial coating technique, arranges chip module 520 on substrate 110, and wherein the packaging body 523 of chip module 520 is bonding on substrate 110 by chip heat-conducting glue 130.
All the other manufacturing steps of the semiconductor package part 500 of Fig. 5, similar in appearance to the corresponding step of semiconductor package part 100, hold this and repeat no more.
Please refer to Figure 13 A to 13E, it illustrates the process drawing of the semiconductor package part 600 of Fig. 6.
As shown in FIG. 13A, provide silicon substrate 521, wherein silicon substrate 521 is formed with several electrical connection element 121, wherein electrical connection element 121 is distributed in zone line and the fringe region of a surperficial 521u of silicon substrate 521.
As shown in Figure 13 B, can adopt is such as dispensing technology, forms package material 523 ' and covers some electrical connection element 121, better but be non-exclusively cover to be positioned at the electrical connection element 121 of the zone line of surperficial 521u.Thus, after first mould 10 and the second mould 20 matched moulds of subsequent step, package material 523 ' can be moved toward two effluents.
As shown in fig. 13 c, the structure of Figure 13 B is set in the first mould 10.The structure of Figure 13 B can be located in the die cavity 11a of the first mould 10.
There is provided one second mould 20, it comprises coating layer 21, and it is in order to extrude package material 523 ' and to contact with electrical connection element 121.Coating layer 21 has compressive characteristics, and when after the first mould 10 and the second mould 20 matched moulds, a part 1211 for electrical connection element 121 can be absorbed in coating layer 21.
As illustrated in figure 13d, matched moulds first mould 10 and the second mould 20, make the second mould 20 press in package material 523 ', and heat package material 523 ' simultaneously, makes it produce mobility and move toward two effluents, and then coated electrical connection element 121.So far, chip module 520 is formed.A part 1211 due to electrical connection element 121 is absorbed in coating layer 21, therefore another part 1212 of the coated electrical connection element 121 of package material 523 ', make a part 1211 for electrical connection element 121 protrude past the surperficial 523u of package material 523 '.
As shown in figure 13e, the first mould 10 (Figure 13 D) and the second mould 20 (Figure 13 D) is separated, to take out chip module 620.Then, chip module 520 is put into baking box, to be such as 175 degree of continuous heating chip modules 520 Celsius about 4 hours, form packaging body 523 with complete cure package body material 523 '.
All the other manufacturing steps of the semiconductor package part 600 of Fig. 6, similar in appearance to the corresponding step of semiconductor package part 500, hold this and repeat no more.
In addition, the manufacturing step of the semiconductor package part 700 of Fig. 7 A, similar in appearance to the manufacturing step of semiconductor package part 100, holds this and repeats no more.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (13)
1. a semiconductor package part, is characterized in that, comprising:
One substrate;
One chip module, being located on this substrate and comprising an electrical connection element, this chip module is electrically connected at this substrate by this electrical connection element;
One chip heat-conducting glue, to be formed between this chip module and this substrate and to bind this chip module and this substrate; And
One dissipating cover, to be located on this substrate and to cover this chip module.
2. semiconductor package part as claimed in claim 1, it is characterized in that, this dissipating cover is a conductive radiator lid, and this substrate comprises a grounding parts, and this semiconductor package part more comprises:
One conducting resinl, is formed between this dissipating cover and this substrate, and this dissipating cover is electrically connected this grounding parts of this substrate by this conducting resinl.
3. semiconductor package part as claimed in claim 1, is characterized in that, this substrate has a relative upper surface and a lower surface and comprises a louvre, and this upper surface that this chip heat-conducting glue is formed at this substrate contacts this louvre.
4. semiconductor package part as claimed in claim 1, is characterized in that, more comprise:
One dissipating cover heat-conducting glue, is formed between this dissipating cover and this chip module.
5. semiconductor package part as claimed in claim 1, is characterized in that, more comprise:
One primer, to be formed between this chip module and this substrate and this electrical connection element coated.
6. semiconductor package part as claimed in claim 1, it is characterized in that, this chip module comprises:
One first chip;
One second chip, is located on this first chip, and the size of this second chip is less than this first chip;
Wherein, this electrical connection element connects this first chip and this substrate, and this second chip is located on this substrate by this chip heat-conducting glue.
7. semiconductor package part as claimed in claim 6, is characterized in that, more comprise:
One primer, this electrical connection element coated and this second chip.
8. semiconductor package part as claimed in claim 1, it is characterized in that, this chip module comprises:
One silicon substrate, this electrical connection element is formed on this silicon substrate;
One chip, is located at this silicon substrate; And
One packaging body, a part for this chip coated and this electrical connection element, another part of this electrical connection element protrudes past this packaging body.
9. a manufacture method for semiconductor package part, is characterized in that, comprising:
One chip module is provided, this chip module is formed with an electrical connection element;
Form a chip heat-conducting glue on a substrate;
Arrange this chip module on this chip heat-conducting glue of this substrate, make this chip module be bonding on this substrate by this chip heat-conducting glue, wherein this chip module is electrically connected at this substrate by this electrical connection element; And
Arranging a dissipating cover is located on this substrate, and this dissipating cover covers this chip module.
10. manufacture method as claimed in claim 9, it is characterized in that, this dissipating cover is a conductive radiator lid, and this substrate comprises a grounding parts, and this manufacture method more comprises:
Form a conducting resinl in this substrate;
In arranging in the step that this dissipating cover is located on this substrate, this dissipating cover to be bonding on this substrate by this conducting resinl and to be electrically connected this grounding parts of this substrate.
11. manufacture methods as claimed in claim 10, it is characterized in that, in this chip heat-conducting glue of formation in the step of this substrate, this substrate has a relative upper surface and a lower surface and comprises a louvre, and this upper surface that this chip heat-conducting glue is formed at this substrate contacts this louvre.
12. manufacture methods as claimed in claim 10, is characterized in that, more comprise:
Form a dissipating cover heat-conducting glue on this chip module, make in arranging in the step that this dissipating cover is located on this substrate, this dissipating cover is bonding on this chip module by this dissipating cover heat-conducting glue.
13. manufacture methods as claimed in claim 10, it is characterized in that, this chip module comprises:
One first chip;
One second chip, is located on this first chip, and the size of this second chip is less than this first chip;
In arranging in the step of this chip module on this chip heat-conducting glue of this substrate, this electrical connection element connects this first chip and this substrate, and this second chip is located on this substrate by this chip heat-conducting glue.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310481588.2A CN104576568A (en) | 2013-10-15 | 2013-10-15 | Semiconductor packaging piece and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310481588.2A CN104576568A (en) | 2013-10-15 | 2013-10-15 | Semiconductor packaging piece and manufacturing method thereof |
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| CN104576568A true CN104576568A (en) | 2015-04-29 |
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