CN104572518B - A kind of storage device - Google Patents

A kind of storage device Download PDF

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Publication number
CN104572518B
CN104572518B CN201410844479.7A CN201410844479A CN104572518B CN 104572518 B CN104572518 B CN 104572518B CN 201410844479 A CN201410844479 A CN 201410844479A CN 104572518 B CN104572518 B CN 104572518B
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ddr
pcb
controller
storage device
storage
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CN104572518A (en
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蔡远彬
欧康华
柳树要
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Huawei Technologies Co Ltd
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Hangzhou Huawei Digital Technologies Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)

Abstract

The embodiment of the invention discloses a kind of storage device, including:An at least bar printing wiring board PCB and a double data rate ddr interface, controller and storage particle are placed on every piece of PCB, the storage particle is connect with the controller, the controller is connect by DDR buses with the ddr interface, the ddr interface is placed on one of PCB, the DDR data lines in the DDR buses by the corresponding DDR data line groups of each controller into;The ddr interface is used to connect with the DDR sockets on mainboard where CPU;Wherein, the corresponding DDR data lines digit of each controller is less than the DDR data line digits that the DDR sockets provide;The controller receives the control signal that the CPU is sent, and stores particle reading and/or write-in target data from described according to the control signal.Using the embodiment of the present invention, system can be reduced from the propagation delay time of storage device read-write data.

Description

A kind of storage device
Technical field
The present invention relates to field of computer technology more particularly to a kind of storage devices.
Background technology
With the development of terminal technology, the demand that individual consumer, enterprise etc. store information increasingly increases, and calculates Storage pressure on machine, server is also increasing.It is well known that hard disk include mechanical hard disk (Hard Disk Drive, HDD) and solid state disk (Solid State Disk, SSD), wherein, solid state disk has abandoned traditional magnetic medium, using electronics Storage medium carries out data storage and reading, has many advantages, such as that read or write speed is fast, shock resistance is good, low in energy consumption, therefore, in face of increasingly The data volume of growth and storage demand, solid state disk are widely used.
Hard-disk interface is the connecting component between hard disk and host system, and effect is that data are transmitted between hard disk and host, The quality of hard-disk interface directly affects the propagation delay time that system reads data from hard disk.At present, common hard-disk interface has IDE (Integrated Drive Electronics, integrated drive electronics), SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment, a kind of connection hardware driver interface based on professional standard), SCSI (Small Computer System Interface, small computer system interface) etc., hard disk pass through interface and south Bridging connects, south bridge (Southbridge) connect with north bridge (Northbridge) (as shown in Figure 1a, Fig. 1 a be the prior art provide A kind of solid state disk and CPU relation schematic diagram), carry out data exchange, number so as to which, hard disk passes through south bridge, north bridge followed by CPU It is big according to the propagation delay time during read-write.
Invention content
The embodiment of the present invention provides a kind of storage device, when can reduce transmission of the system from storage device read-write data Prolong.
In a first aspect, the embodiment of the present invention provides a kind of storage device, including:An at least bar printing wiring board PCB and one A double data rate ddr interface is placed with controller and storage particle, the storage particle and the controller on every piece of PCB Connection, the controller are connect by DDR buses with the ddr interface, and the ddr interface is placed on one of PCB;Institute State DDR data lines in DDR buses by the corresponding DDR data line groups of each controller into;The ddr interface is used for and CPU institutes DDR sockets connection on mainboard;Wherein,
The corresponding DDR data lines digit of each controller is less than the DDR data line digits that the DDR sockets provide;It is described Controller receives the control signal that the CPU is sent, and stores particle reading and/or write-in from described according to the control signal Target data.
With reference to first aspect, in the first possible realization method of first aspect, each controller is corresponding DDR data lines digit is 8.
With reference to first aspect or the first possible realization method of first aspect, second in first aspect are possible In realization method, the storage particle includes flash chip, magnetic RAM MRAM, phase-change random access memory PRAM and resistance Any one storage medium in transition storage RRAM.
With reference to first aspect, in the third possible realization method of first aspect, if an at least bar printing line The block number of road plate PCB is n blocks, and n >=2, n are integer, and the storage device further includes n-1 block flexible boards, and adjacent two pieces of PCB lead to The flexible board is crossed to be electrically connected, wherein, the controller on two pieces of PCB is connected by the flexible board.
With reference to first aspect, in the 4th kind of possible realization method of first aspect, if an at least bar printing line The block number of road plate PCB is n blocks, and n >=2, n are integer, and the storage device further includes n-1 connector, and adjacent two pieces of PCB lead to The connector is crossed to be electrically connected, wherein, the controller on two pieces of PCB is connected by the connector.
With reference to first aspect, in the 5th kind of possible realization method of first aspect, if an at least bar printing line The block number of road plate PCB is n blocks, and n >=2, n are integer, and the storage device further includes n-1 block PCB daughter boards, adjacent two pieces of PCB It is electrically connected by the PCB daughter boards, wherein, the controller on two pieces of PCB is connected by the PCB daughter boards.
With reference to first aspect the third is to any one possible realization method in the 5th kind, the of first aspect In six kinds of possible realization methods, the storage device further includes heat sink material, and the heat sink material is arranged on adjacent two pieces Between PCB.
With reference to first aspect, the possible realization method of the first of first aspect, first aspect the third to the 5th kind In any one possible realization method, in the 7th kind of possible realization method of first aspect, the ddr interface includes DDR3 and DDR4.
The 7th kind of possible realization method with reference to first aspect, in the 8th kind of possible realization method of first aspect In, the storage device further includes shell, at least a bar printing wiring board PCB, the controller and the storage particle The enclosure is set to, the ddr interface is set in the shell.
With reference to first aspect, in the 9th kind of possible realization method of first aspect, the storage particle passes through opening Formula flash interface ONFI buses are connect with the controller.
Implement the embodiment of the present invention, storage device includes an an at least bar printing wiring board PCB and double data rate DDR Interface is placed with controller and storage particle on every piece of PCB, wherein, storage particle is connect with controller, and the controller passes through DDR buses are connect with ddr interface, and ddr interface is placed on one of PCB;DDR data lines in DDR buses are by each control The corresponding DDR data line groups of device processed into.Using the embodiment of the present invention, pass through the DDR sockets where ddr interface and CPU on mainboard Connection, so as to which storage device is carried out data transmission based on main memory access with CPU, can be reduced system and be read and write number from storage device According to propagation delay time;Meanwhile in storage device on mainboard where the corresponding DDR data lines digit of each controller is less than CPU The DDR data line digits that DDR sockets provide can realize the expandable type design of storage device, improve design storage device Flexibility.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is some embodiments of the present invention, for ability For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached Figure.
Fig. 1 a are a kind of solid state disk that the prior art provides and the relation schematic diagram of CPU;
Fig. 1 is a kind of structure diagram of storage device provided in an embodiment of the present invention;
Fig. 1 b are the relation schematic diagrams of a kind of storage device and CPU provided in an embodiment of the present invention;
Fig. 2 is a kind of another structure diagram of storage device provided in an embodiment of the present invention;
Fig. 3 is a kind of another structure diagram of storage device provided in an embodiment of the present invention;
Fig. 3 a are a kind of another structure diagrams of storage device provided in an embodiment of the present invention;
Fig. 3 b are a kind of another structure diagrams of storage device provided in an embodiment of the present invention;
Fig. 3 c are a kind of another structure diagrams of storage device provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only the part of the embodiment of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work Embodiment shall fall within the protection scope of the present invention.
Fig. 1 is referred to, Fig. 1 is a kind of structure diagram of storage device provided in an embodiment of the present invention, of the invention real It applies in example, which can include:An at least bar printing wiring board (Printed Circuit Board, PCB) 101, one A double data rate (Double Data Rate, DDR) interface 102, controller 103 and storage particle 104.
Wherein, controller and storage particle are placed on every bar printing wiring board, storage particle connect with controller, controls Device is connect by DDR buses with ddr interface, and ddr interface is placed on one of PCB;DDR data in the DDR buses Line receives the control signal that the CPU is sent by the corresponding DDR data line groups of each controller into, the controller, and according to The control signal is read from the storage particle and/or write-in target data;The ddr interface is used for and mainboard where CPU On DDR sockets connection.Thus when computer or server are when the storage device that the embodiment of the present invention is used in equipment, it can The ddr interface in the storage device directly to be connect with the DDR sockets on mainboard where CPU.Due to mainboard where CPU On DDR sockets be for connecting memory, therefore, storage device is connect by main memory access with CPU, and CPU and the storage fill It puts when carrying out data transmission, can effectively reduce system from the propagation delay time of storage device read-write data, be adapted for couple to equipment On serve as hard disk use.For convenience of understanding, refer to Fig. 1 b, Fig. 1 b be a kind of storage device provided in an embodiment of the present invention with The relation schematic diagram of CPU, it is known that, storage device provided in an embodiment of the present invention is directly connect with north bridge, therefore, storage device with Transmission path is short when CPU carries out data transmission (only passing through north bridge), can effectively reduce system from the biography of storage device read-write data Defeated time delay, what deserves to be explained is, with the development of chip technology, north bridge is regularly integrated in CPU (such as Fig. 1 a or Fig. 1 b institutes Show), so as to, system from storage device read data when real-time it is high.
In the embodiment of the present invention, the corresponding DDR data lines digit of each controller is less than the DDR that the DDR sockets provide Data line digit.For example, by taking the DDR4 on X86-based mainboard as an example, DDR4 sockets are usually 288 pins, wherein 72 are drawn Foot represents DDR data lines, and in the embodiment of the present invention, the corresponding DDR data lines of each controller are less than the DDR that DDR4 sockets provide Data line, such as the corresponding DDR data lines of each controller can be 4,8,16.What deserves to be explained is the present invention As long as the corresponding DDR data lines digit of each controller is less than DDR data line digits (such as X86 that DDR sockets provide in embodiment The data line digit of DDR4 sockets is 72), the specific embodiment of the present invention is not restricted in framework.For convenience of understanding, still By taking DDR4 sockets as an example, it is assumed that the corresponding DDR data lines digit of each controller is 8, then the storage dress based on DDR4 sockets 9 controllers can at most be included by putting, it is assumed that include 1 controller on one piece of PCB, then storage device maximum can be designed to 9 Therefore block PCB, using the embodiment of the present invention, can be extended storage device formula design, the storage for increasing storage device is held Amount.
What deserves to be explained is in the specific implementation, addressing system when reading data from hard disk and memory due to system not Equally, in the embodiment of the present invention, the DDR address wires that main memory access provides can not be used, i.e. DDR buses can only include DDR Data line and DDR control lines, wherein, the DDR control lines being connect with DDR sockets are connect with each controller.
What deserves to be explained is the embodiment of the present invention does not limit the quantity of printed wiring board, controller, storage particle System, particular number can be set according to actual demand.For example, it is assumed that the storage device of one 800G of desired design, and one The printed wiring board maximum of block suitable dimension can make 500G, then two bar printing wiring boards may be used and be designed, wherein, two Bar printing wiring board is electrically connected, the storage particle, controller on two bar printing wiring boards by ddr interface 102 with CPU transmits data;If the storage device within one 500G of desired design, using a bar printing wiring board.It is specific real In existing, it can also be multiple that the amount controller on every bar printing wiring board, which can be 1, and the embodiment of the present invention is not restricted. It for convenience of understanding, is exemplified below, it is assumed that controller possesses 8 memory channels (such as NAND channels), and each channel can at most connect 8 Storage particle, then the maximum storage granule number that controller can be supported be 64;If maximum can place in printed wiring board 128 storage particles, then can set two controllers in the printed wiring board, wherein, each controller connects 64 respectively Storage particle, and two controllers are electrically connected.In the specific implementation, quantity, the unit capacity of storage particle need basis The storage device to be designed chooses the requirements such as memory capacity, size, and the embodiment of the present invention is not intended to be limited in any this.
For convenience of description, with storage device, including being placed in a bar printing wiring board, printed wiring board, there are one controllers Scene for (as shown in Figure 1), other scenes please refer to subsequent embodiment, in Fig. 1, are placed in printed wiring board 101 Controller 103, storage particle 104 and ddr interface 102, storage particle 104 are connect respectively with controller 103, connection mode by The property or production firm for storing particle 104 determine.If for example, storage particle using Intel, Micron, SanDisk, The companies such as Sony research and develop or the NAND FLASH flash chips of production, then store particle and pass through open flash interface (Open NAND FLASH Interface, ONFI) bus connect with controller.If for another example storage particle using Samsung with Toshiba is researched and developed or the NAND FLASH flash chips of production, then stores particle and be based on Toggle DDR Mode standards and control Device connects, wherein, Toggle DDR Mode standards are originated from the completely new nand flash memory interface that Samsung and Toshiba joints are formulated Standard.In the specific implementation, the connection mode of storage particle and controller need to determine that the present invention is implemented according to the type of storage particle Example is not restricted this.
In the specific implementation, storage particle can be flash chip, such as NOR FLASH or NAND FLASH, wherein, NOR and NAND is that two kinds of main nonvolatile flash memories, NAND FLASH have the characteristics of memory capacity is big, and read-write rate is slow in the market; NOR FLASH have the characteristics of memory capacity is small, and read-write rate is fast;In general, NAND FLASH are used for as storage (Storage), NOR FLASH are used to store code (code).Therefore, actual demand can be combined and chooses flash chip, as one Kind preferred embodiment, storage particle is using NAND FLASH flash chips, so as in the printed wiring board of identical size It can be designed that have the storage device of more large storage capacity.
What deserves to be explained is storage particle can also be magnetic RAM (Magnetic Random Access Memory, MRAM), any one storage medium in phase-change random access memory PRAM and resistance-variable storing device RRAM.MRAM is one Kind non-volatile magnetic RAM, it possess Static RAM (Static Random Access Memory, SRAM high speed) reads write capability and dynamic RAM (Dynamic Random Access Memory, DRAM) High integration, and can substantially be repeatedly written infinitely.PRAM is a memory that Samsung companies release, Compared to common DRAM and flash memory, PRAM has the characteristics that high-speed low-power-consumption.RRAM is according to being applied to metal oxide (Metal Oxide the difference of the voltage on) makes the resistance of material that respective change occur between high-impedance state and low resistance state, so as to open or hinder Disconnected current flow channels, and using the memory of the various information of this property storage, it is remarkably improved durability and data transmission speed Degree.
In the storage device of description of the embodiment of the present invention, including an at least bar printing wiring board PCB and a Double Data Rate ddr interface is placed with controller and storage particle on every piece of PCB, wherein, storage particle is connect with controller, controller It is connect by DDR buses with ddr interface;Ddr interface is placed on one of PCB, and the DDR data lines in DDR buses are by every The corresponding DDR data line groups of a controller into.Using the embodiment of the present invention, pass through the DDR where ddr interface and CPU on mainboard Socket connects, so as to which storage device is carried out data transmission based on main memory access with CPU, can be reduced system and be read from storage device Write the propagation delay time of data;Meanwhile the corresponding DDR data lines digit of each controller is less than mainboard where CPU in storage device On DDR sockets provide DDR data line digits, can realize storage device expandable type design, improve design storage dress The flexibility put.
Fig. 2 is referred to, Fig. 2 is a kind of another structure diagram of storage device provided in an embodiment of the present invention, for convenience Illustrating, the embodiment of the present invention is for including placing a controller on two pieces of PCB, every piece of PCB, in embodiments of the present invention, The storage device can include:An at least bar printing wiring board (101a, 101b), a double data rate interface (102), control Device (103a, 103b) and storage particle (104a, 104b).
Wherein, controller (103a, 103b) and storage particle are placed on every bar printing wiring board (101a, 101b) (104a, 104b), storage particle is connect with controller (if storage particle 104a is connect with controller 103a, stores particle 104b It is connect with controller 103b);Ddr interface (102) is placed on one of PCB (such as 101a), and controller (103a, 103b) is logical DDR buses are crossed to connect with ddr interface (102);Controller (103a) receives the control signal that the CPU is sent, and according to described Signal is controlled to read and/or be written target data from the storage particle (104a, 104b);Ddr interface (102) is used for and CPU DDR sockets connection on the mainboard of place.Wherein, the DDR data lines in DDR buses are by the corresponding DDR data lines of each controller Composition, the corresponding DDR data lines digit of each controller are less than the DDR data line digits that the DDR sockets provide.
So as to which when computer or server are when the storage device that the embodiment of the present invention is used in equipment, this can be deposited Ddr interface in storage device is directly connect with the DDR sockets on mainboard where CPU.Due to the DDR on mainboard where CPU Socket is for connecting memory, and therefore, storage device is connect by main memory access with CPU, and CPU and the storage device are into line number According to transmission when, can effectively reduce system from storage device read-write data propagation delay time, system from storage device read data when Real-time is high.
In the embodiment of the present invention, storage device corresponds to a ddr interface, each controller by DDR buses with Ddr interface connects, since controller is arranged on PCB, in the concrete realization, if storage device includes one piece of PCB, Then the controller on the PCB is directly connect by DDR buses with ddr interface;If storage device includes two or more than two It is electrically connected between PCB, adjacent two pieces of PCB, the controller on one of PCB is directly connect by DDR buses with DDR Mouth connects, and the controller on other PCB is connect based on the Electric connection characteristic between PCB also by DDR buses with ddr interface (the DDR control lines i.e. in ddr interface are connect with each controller on PCB, wherein, DDR data lines in ddr interface by Each corresponding DDR data line groups of controller into).In the specific implementation, it is whole that storage device, which includes n bar printing wiring boards PCB, n, Number, if n >=2, adjacent two pieces of PCB are electrically connected, so that each controller on every piece of PCB passes through DDR buses It is connect with ddr interface.For convenience of understanding, spy is exemplified below, it is assumed that storage device include 2 pieces of PCB (be respectively depicted as " PCB1 " and " PCB2 "), it places on every piece of PCB there are one controller (being respectively depicted as " controller one " and " controller two "), each control The corresponding DDR data lines of device are 8 (being respectively depicted as " D1~D8 " and " D9~D16 "), and the DDR of ddr interface and DDR sockets is total DDR control lines in line are 15 (being described as " C1~C15 "), then it is found that in the DDR buses of ddr interface and DDR sockets DDR data lines are 16, including " D1~D16 ", wherein, the DDR data lines " D1~D8 " and " controller one " in ddr interface are right The DDR data line ports answered connect, DDR data lines " D9~D16 " the DDR data corresponding with " controller two " in ddr interface Line end mouth connects, and the DDR control lines " C1~C15 " in ddr interface control respectively with the DDR of " controller one " and " controller two " Line end mouth connects, i.e., " controller one " corresponding DDR buses are " D1~D8, C1~C15 ", and " controller two " corresponding DDR is total Line is " D9~D16, C1~C15 ";In the specific implementation, the DDR control lines in ddr interface can also be divided into more parts, for example, Assuming that per a corresponding 15, then the DDR controller corresponding with " controller one " of the DDR control lines " C1~C15 " in ddr interface Port connects, the DDR control lines port connection corresponding with " controller two " of the DDR control lines " C16~C30 " in ddr interface, i.e., " controller one " corresponding DDR buses be " D1~D8, C1~C15 ", " controller two " corresponding DDR buses for " D9~D16, C16~C30 ".What deserves to be explained is these are only a kind of example, equivalent or phase can be carried out in specific implementation according to actual demand Like transformation, for example, the corresponding DDR data lines of controller are 4,16 etc., the corresponding DDR control lines of controller are 20, 25 etc., specifically, the embodiment of the present invention is not restricted.It is direct addressing method generally, due to memory, based on main memory access System bus include data/address bus (Data Bus, DB), controlling bus (Control Bus, CB) and address bus Addressing system when (Address Bus, AB), the storage device in the embodiment of the present invention read data is with hard disk, CFC (Compact Flash Card, compact flash) is similar, belongs to indirect addressing mode, therefore, can also based on main memory access Memory capacity is made very big.In the specific implementation, the DDR address wires in DDR sockets can be saved, design storage device is reduced Complexity, therefore, the ddr interface of storage device can only include DDR data lines and DDR control lines, it is of course also possible to be DDR Data line, DDR control lines, DDR address wires set, specifically, the embodiment of the present invention is not restricted.
As a kind of feasible embodiment, if at least block number of a bar printing wiring board PCB is n blocks, n >=2, n For integer, the storage device further includes n-1 block flexible boards, and adjacent two pieces of PCB are electrically connected by the flexible board, Wherein, the controller on two pieces of PCB is connected by the flexible board.
For convenience of understanding, Fig. 3 is referred to, Fig. 3 is that a kind of another structure of storage device provided in an embodiment of the present invention is shown It is intended to, in Fig. 3 by taking 2 pieces of PCB (301a, 301b) as an example, which includes ddr interface (302), and controller (does not show in figure Go out) and particle (particle being reduced in figure 3, such as 304a, 304b) is stored, two pieces of PCB (301a, 301b) pass through flexible board (305) connect, ddr interface (302) for connect with the DDR sockets where CPU on mainboard, thus, except being placed with ddr interface Outside PCB, the corresponding DDR buses of each controller on other PCB can be connected to ddr interface by flexible board.As one kind Feasible embodiment, the controller on adjacent two pieces of PCB are connected by flexible board, so as to when some controller is corresponding Connection between DDR buses and ddr interface when something goes wrong, can transmit data, control by the interconnection between controller Signal etc. improves the fault-tolerant ability of storage device.It is asked in the specific implementation, may have heat dissipation in view of two pieces of adjacent PCB Topic, as a kind of feasible embodiment, storage device can also include heat sink material, and the heat sink material is arranged on adjacent Between two pieces of PCB.
As a kind of feasible embodiment, if at least block number of a bar printing wiring board PCB is n blocks, n >=2, n For integer, the storage device further includes n-1 connector, and adjacent two pieces of PCB are electrically connected by the connector, Wherein, the controller on two pieces of PCB is connected by the connector.
For convenience of understanding, Fig. 3 a are referred to, Fig. 3 a are a kind of another structures of storage device provided in an embodiment of the present invention Schematic diagram, in Fig. 3 a by taking 2 pieces of PCB (301a, 301b) as an example, which includes ddr interface (302), and controller is (in figure not Show) and particle (particle being reduced in fig. 3 a, such as 304a, 304b) is stored, two pieces of PCB (301a, 301b) pass through connector (306) connect, ddr interface (302) for connect with the DDR sockets where CPU on mainboard, thus, except being placed with ddr interface Outside PCB, the corresponding DDR buses of each controller on other PCB can be connected to ddr interface by connector.As one kind Feasible embodiment, the controller on adjacent two pieces of PCB are connected by connector, so as to when some controller is corresponding Connection between DDR buses and ddr interface when something goes wrong, can transmit data, control by the interconnection between controller Signal etc. improves the fault-tolerant ability of storage device.It is asked in the specific implementation, may have heat dissipation in view of two pieces of adjacent PCB Topic, as a kind of feasible embodiment, storage device can also include heat sink material, and the heat sink material is arranged on adjacent Between two pieces of PCB.
As a kind of feasible embodiment, if at least block number of a bar printing wiring board PCB is n blocks, n >=2, n For integer, the storage device further includes n-1 block PCB daughter boards, and adjacent two pieces of PCB are electrically connected by the PCB daughter boards It connects, wherein, the controller on two pieces of PCB is connected by the PCB daughter boards.
For convenience of understanding, Fig. 3 b are referred to, Fig. 3 b are a kind of another structures of storage device provided in an embodiment of the present invention Schematic diagram, in Fig. 3 b by taking 2 pieces of PCB (301a, 301b) as an example, which includes ddr interface (302), and controller is (in figure not Show) and particle (particle being reduced in fig. 3 a, such as 304a, 304b) is stored, two pieces of PCB (301a, 301b) pass through PCB daughter boards (307) connect, ddr interface (302) for connect with the DDR sockets where CPU on mainboard, thus, except being placed with ddr interface Outside PCB, the corresponding DDR buses of each controller on other PCB can be connected to ddr interface by PCB daughter boards.As one kind Feasible embodiment, the controller on adjacent two pieces of PCB are connected by PCB daughter boards, so as to when some controller is corresponding Connection between DDR buses and ddr interface when something goes wrong, can transmit data, control by the interconnection between controller Signal etc. improves the fault-tolerant ability of storage device.It is asked in the specific implementation, may have heat dissipation in view of two pieces of adjacent PCB Topic, as a kind of feasible embodiment, storage device can also include heat sink material, and the heat sink material is arranged on adjacent Between two pieces of PCB.
What deserves to be explained is the embodiment of the present invention is not limited printed wiring board, the quantity of controller, specific number Amount can be set according to actual demand, store the quantity of particle, unit capacity is also needed according to the storage device pair to be designed The requirements such as memory capacity, size are chosen, and the embodiment of the present invention is not restricted detail.If for example, desired design one A memory capacity be 160G storage device, may be used 4 capacity be 40G storage particle, can also use 8 capacity for Storage particle of 20G etc., however, using 4 capacity as the storage particle of 40G and using storage particle of 8 capacity for 20G The storage device designed may in size, price, performance difference, therefore, basis is needed in actual process Actual needs chooses storage particle, and the embodiment of the present invention is not intended to be limited in any this.
For convenience of understanding, it is assumed that the corresponding DDR data lines digit of each controller is 8, the DDR where CPU on mainboard Socket is DDR4, it is known that DDR4 includes 288 pins, wherein 72 pins represent DDR data/address bus, therefore, storage device is most It can be designed to greatly include 9 pieces of PCB.It can be according to the selection of dimension suitable dimension for the storage device to be designed in specific implementation PCB if can not meet the memory capacity for the storage device to be designed on one piece of PCB, then adds one piece of PCB, this two pieces PCB is electrically connected, if two pieces of PCB can not still meet the memory capacity for the storage device to be designed, continues to add PCB, until design is met.Certainly, it needs to consider various factors such as size, price, performance in specific implementation, with Desired design goes out big, at low cost, the small storage device of capacity.For convenience of understanding, storage device includes the structure of polylith PCB Can as shown in Figure 3c, Fig. 3 c are that (controller is not for another structure diagram of storage device provided in an embodiment of the present invention a kind of It is shown in figure).Two pieces of adjacent PCB are electrically connected by modes such as flexible board, connector, PCB daughter boards, are made adjacent Controller on two pieces of PCB is attached.
What deserves to be explained is in the specific implementation, ddr interface can be and matched of DDR sockets on mainboard where CPU One memory interface, at present, common memory interface have DDR3, DDR4.In the embodiment of the present invention, ddr interface include DDR3 and DDR4, it is, of course, also possible to be DDR2 or DDR1, the specific embodiment of the present invention is not restricted.
In a kind of feasible embodiment, the storage device of the embodiment of the present invention can also include shell, wherein, at least One bar printing wiring board PCB, controller and storage particle may be contained within the enclosure, if PCB is polylith, flexible board, Connector, PCB daughter boards are also disposed on enclosure, and ddr interface is set in the shell, so as to design storage device Into forms such as the hard disks or storage card that can independently use, it can directly be used when mobile hard disk, user is facilitated to carry.
In the storage device of description of the embodiment of the present invention, including an at least bar printing wiring board PCB and a Double Data Rate ddr interface is placed with controller and storage particle on every piece of PCB, wherein, storage particle is connect with controller;Ddr interface It is placed on one of PCB, the controller on the PCB is connect by DDR buses with ddr interface, the DDR numbers in DDR buses According to line by the corresponding DDR data line groups of each controller into.Using the embodiment of the present invention, pass through mainboard where ddr interface and CPU On DDR sockets connection, so as to, storage device is carried out data transmission based on main memory access with CPU, can reduce system from storage Device reads and writes the propagation delay time of data;Meanwhile the corresponding DDR data lines digit of each controller is less than CPU institutes in storage device The DDR data line digits that DDR sockets on mainboard provide can realize the expandable type design of storage device, improve design The flexibility of storage device.
In the description of this specification, reference term " one embodiment ", " example ", " is specifically shown " some embodiments " The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description Point is contained at least one embodiment of the present invention or example.In the present specification, schematic expression of the above terms are not Must must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be It is combined in an appropriate manner in any one or more embodiments or example.In addition, without conflicting with each other, this field Technical staff can carry out the feature of the different embodiments or examples described in this specification and different embodiments or examples With reference to and combination.
Those skilled in the art can be by the different embodiments described in this specification and the feature of different embodiments It is combined.The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations;Although with reference to before Each embodiment is stated the present invention is described in detail, it will be understood by those of ordinary skill in the art that:It still can be right Technical solution recorded in foregoing embodiments modifies and either which part or all technical features is equally replaced It changes;And these modifications or replacement, without departing from the principle of the present invention, still fall within the range that the present invention is covered.

Claims (10)

1. a kind of storage device, which is characterized in that including at least two bar printing wiring board PCB, further include a double data rate Ddr interface is placed with controller and storage particle on every piece of PCB, and the storage particle is connect with the controller, the control Device is connect by DDR buses with the ddr interface, and the ddr interface is placed on one of PCB;In the DDR buses DDR data lines by the corresponding DDR data line groups of each controller into;The ddr interface is used for and the DDR on mainboard where CPU Socket connects;Wherein,
Each corresponding DDR data lines digit of controller is the arbitrary position of DDR data line digits provided less than the DDR sockets Number;The controller receives the control signal that the CPU is sent, and is read according to the control signal from the storage particle And/or write-in target data.
2. storage device as described in claim 1, which is characterized in that the corresponding DDR data lines digit of each controller It is 8.
3. storage device as claimed in claim 1 or 2, which is characterized in that the storage particle include flash chip, it is magnetic with Any one storage medium in machine memory MRAM, phase-change random access memory PRAM and resistance-variable storing device RRAM.
4. storage device as described in claim 1, which is characterized in that if at least block number of two bar printing wiring board PCB For n blocks, n >=2, n are integer, and the storage device further includes n-1 block flexible boards, and adjacent two pieces of PCB pass through the flexible board It is electrically connected, wherein, the controller on two pieces of adjacent PCB is connected by the flexible board.
5. storage device as described in claim 1, which is characterized in that if at least block number of two bar printing wiring board PCB For n blocks, n >=2, n are integer, and the storage device further includes n-1 connector, and adjacent two pieces of PCB pass through the connector It is electrically connected, wherein, the controller on two pieces of adjacent PCB is connected by the connector.
6. storage device as described in claim 1, which is characterized in that if at least block number of two bar printing wiring board PCB For n blocks, n >=2, n are integer, and the storage device further includes n-1 block PCB daughter boards, and adjacent two pieces of PCB pass through PCB Plate is electrically connected, wherein, the controller on two pieces of adjacent PCB is connected by the PCB daughter boards.
7. such as claim 4-6 any one of them storage devices, which is characterized in that the storage device further includes heat dissipation material Material, the heat sink material are arranged between two pieces of adjacent PCB.
8. such as claim 1-2 or 4-6 any one of them storage device, which is characterized in that the ddr interface include DDR3 and DDR4。
9. storage device as claimed in claim 8, which is characterized in that the storage device further includes shell, and described at least two Bar printing wiring board PCB, the controller and the storage particle are set to the enclosure, and the ddr interface is set to In the shell.
10. storage device as described in claim 1, which is characterized in that the storage particle passes through open flash interface ONFI buses are connect with the controller.
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CN108986850B (en) * 2018-07-19 2020-05-19 苏州浪潮智能科技有限公司 Structure for reducing internal temperature of NVME hard disk
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211649A (en) * 2006-12-27 2008-07-02 宇瞻科技股份有限公司 Dynamic RAM module possessing solid magnetic disc
CN201514769U (en) * 2009-09-02 2010-06-23 优力勤股份有限公司 Solid-state magnetic disc memory device
CN203616758U (en) * 2013-04-02 2014-05-28 文盛业 USB (universal serial bus) storage device with multilayer structure
CN203733100U (en) * 2014-03-14 2014-07-23 山东大学 Memory system structure based on PCM (Phase Change Memory)
CN203838697U (en) * 2014-05-27 2014-09-17 浪潮电子信息产业股份有限公司 Solid-state disc device based on DDR interface

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9053066B2 (en) * 2012-03-30 2015-06-09 Sandisk Technologies Inc. NAND flash memory interface

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211649A (en) * 2006-12-27 2008-07-02 宇瞻科技股份有限公司 Dynamic RAM module possessing solid magnetic disc
CN201514769U (en) * 2009-09-02 2010-06-23 优力勤股份有限公司 Solid-state magnetic disc memory device
CN203616758U (en) * 2013-04-02 2014-05-28 文盛业 USB (universal serial bus) storage device with multilayer structure
CN203733100U (en) * 2014-03-14 2014-07-23 山东大学 Memory system structure based on PCM (Phase Change Memory)
CN203838697U (en) * 2014-05-27 2014-09-17 浪潮电子信息产业股份有限公司 Solid-state disc device based on DDR interface

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