CN103809920B - Realizing method of ultra-large capacity solid state disk - Google Patents
Realizing method of ultra-large capacity solid state disk Download PDFInfo
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- CN103809920B CN103809920B CN201410049417.7A CN201410049417A CN103809920B CN 103809920 B CN103809920 B CN 103809920B CN 201410049417 A CN201410049417 A CN 201410049417A CN 103809920 B CN103809920 B CN 103809920B
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Abstract
The invention provides a realizing method of an ultra-large capacity solid state disk. A solid state disk with the capacity of at least TB level can be realized. A storage medium which is large in single capacity and is provided with an SD/MMC interface is used on the disk; each storage channel can contain a plurality of storage media; the storage media in each storage channel share D[0 : 7]/CMD data buses of the SD/MMC interfaces; and SD/MMC interface clock signals of each storage channel are connected into the storage media through high-speed clock switch circuits, the SD/MMC interface clock signals are used as chip selection for controlling, so that the number of the storage media contained in a single storage channel of a disk controller is increased manifold, then the capacity of the disk is increased manifold, and the ultra-large capacity solid state disk is realized.
Description
Technical field
The present invention relates to field of data storage, more particularly to a kind of implementation method of vast capacity solid state hard disc.
Background technology
In the last few years, as the solid state hard disc application based on flash media is increasingly extensive, to the monomer capacity of this kind of hard disk
Bigger requirement is it is also proposed, the application of mass data storage is particularly needed in database server, redundant array of inexpensive disk etc.
Field.
Conventional solid-state hard disk realizes high-speed data read-write and capacity extension using the framework of multiple parallel memory channels,
Each memory channel selects multiple flash chips, therefore the maximum capacity of solid state hard disc to determine by the way of chip selection signal control
Monomer capacity of memory channel number, piece selected control number and flash chip due to its master controller etc..
Solid state hard disc master controller chip is limited to its framework and package pin number, the parallel memorizing passage and piece having
The quantity of selected control is limited；Traditional flash chip uses ONFI/Toggle data interface protocols in addition, there is monomer capacity
Shortcoming more than less than normal, data-interface number of pins, although as the progress of integrated circuit processing technique, monomer capacity also has and progressively increases
Big trend, such as from 4GB to 8GB or even 16GB etc., but from for Large Copacity application, the monomer capacity of flash memory is still less than normal；From
For the volume of solid state hard disc, such as 2.5 inches of solid state hard discs of standard also limit the configuration quantity of flash chip.
Therefore in terms of the design and realization of vast capacity of traditional solid state hard disc more than Large Copacity, especially TB grade,
In the presence of very big bottleneck.Therefore, for drawbacks described above present in currently available technology, it is necessary to be studied in fact, to provide one
The scheme of kind, solves defect present in prior art.
The content of the invention
In order to overcome the defect of above-mentioned prior art, the invention provides a kind of realization side of the solid state hard disc of vast capacity
Method, the method uses the storage medium of the big band SD/MMC interfaces of monomer capacity, and capacity is up to more than TB grades；It is of the invention another
Individual purpose is the memory channel capacity extension mechanism for providing a kind of solid state hard disc, and the mechanism causes that the single of hard disk controller is deposited
Many times of ground of the storage medium quantity that storage passage is accommodated increase, so that many times of ground of hard-disk capacity increase.
To solve the problems, such as prior art, the technical scheme is that：
1) the solid state hard disc external interface of vast capacity is connect using high-speed data communications such as SATA, SAS, eSATA or USB
One of degree of lip-rounding formula；
2) solid state hard disc of vast capacity is internally provided with multiple parallel memory channels；
3) each memory channel uses SD/MMC data-interfaces, configures the storage medium with SD/MMC interface protocols, deposits
Storage media can be the forms such as eMMC, iNAND, SD card or TF cards；
4) each memory channel uses capacity extension mechanism, you can the big SD/MMC interfaces of the multiple monomer capacity of configuration
Storage medium, so that many times of capacity for extending each memory channel；
5) by the capacity extension of memory channel, the solid state hard disc of vast capacity is realized.
The memory channel capacity extension mechanism of the solid state hard disc proposed according to one of goal of the invention, implementation method is:
The memory channel capacity extension mechanism of solid state hard disc mainly includes：Primary processor, DMA data passage, memory channel
Processor, SD/MMC sequential interface circuit, high-speed data on-off circuit, multiple storage mediums with SD/MMC interfaces and piece choosing
Control etc..
Primary processor described in the memory channel capacity extension mechanism, by DMA data passage by LBA data
It is respectively issued to each memory channel processor.
DMA data passage described in the memory channel capacity extension mechanism, there is provided primary processor and parallel memorizing passage
Data link.
Memory channel processor described in the memory channel capacity extension mechanism, the LBA for being responsible for being obtained turns
Change physical block address into, and be responsible for calculating the physical block address with each storage medium in assignment channel.
Memory channel processor described in the memory channel capacity extension mechanism, required reading is selected according to physical block address
The storage medium write.
Memory channel processor described in the memory channel capacity extension mechanism, is responsible for control high-speed data on-off circuit
Switching.
SD/MMC sequential interface circuits described in the memory channel capacity extension mechanism, are responsible for and each storage in passage
The data transfer in SD/MMC communications protocol modes of medium.SD/MMC sequential interface circuits in addition to clock line, other data
Line (including D [0：7] and CMD) in parallel, it is connected and shared with each storage medium in passage.
High-speed data on-off circuit described in the memory channel capacity extension mechanism, belongs to single-pole double throw or hilted broadsword is more
The on-off mode such as throw；Its common port (input) is connected to the clock cable of SD/MMC sequential interface circuits, and it throws end (output
End) clock signal input terminal of each storage medium that is then respectively coupled in passage, its control end is then connected at memory channel
Manage the control pin of device.
Multiple storage mediums with SD/MMC interfaces described in the memory channel capacity extension mechanism, can be eMMC,
The forms such as iNAND, SD card or TF cards, preferably selection is the big eMMC storage chips of monomer capacity.
The beneficial effects of the invention are as follows：
User is capable of achieving the solid state hard disc of vast capacity (more than TB grades) using the present invention.
User uses the present invention, using storage mediums such as the big eMMC of monomer capacity, can be at smaller size smaller (such as 2.5 inches)
Hard disk on, realize TB grades of vast capacity.
User can not receive the memory channel number of hard disk master controller and limiting for chip selection signal using the present invention, the capacity of hard disk
System, can many times of ground increases.
User can not change encapsulation, number of pins and the memory channel number of existing hard disk master controller chip using the present invention,
It is easy to integrated and realizes.
User while the solid state hard disc of vast capacity is realized, still keeps the property of high-speed read-write speed using the present invention
Energy
Property in specific embodiment disclosed herein can be realized by reference to the remainder of the specification and drawings
Matter and advantage further understand.
Brief description of the drawings
Fig. 1 show the theory diagram of embodiments of the invention 1；
Fig. 2 show a further detail below block diagram for memory channel (11) in embodiment 1；
Fig. 3 show the theory diagram of embodiments of the invention 2；
Fig. 4 show a further detail below for memory channel (111) in embodiment 2.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Conversely, the present invention covers any replacement done in spirit and scope of the invention being defined by the claims, repaiies
Change, equivalent method and scheme.Further, in order that the public has a better understanding to the present invention, below to of the invention thin
It is detailed to describe some specific detail sections in section description.Part without these details for a person skilled in the art
Description can also completely understand the present invention.
Fig. 1 show according to one embodiment of present invention in a solid state hard disc (10).Solid state hard disc (10) includes
One external interface (4), a primary processor (5), a high-speed serial data sequential interface and control unit (2), a DMA
Passage (3), the parallel memory channel (11-14) of N number of same architecture.
Fig. 2 is that the further detail below of said one memory channel 11 is described, including a data buffer (20), and one leads to
The processor of road 1 (21), SD/MMC sequential interface circuit (23), a high-frequency clock on-off circuit (27), on-off circuit control
The major parts such as signal (26) processed, M identical storage medium (41-43), additionally include on-off circuit control signal (26),
The shared D [0 of the clock signal clk 1 (22), storage medium of SD/MMC sequential interface circuits:7]/CMD data/address bus (25), deposit
Alone clock signal clk 1-1 (25) of storage media etc..
The working mechanism of one solid state hard disc of vast capacity (10) of embodiment is as follows：
Solid state hard disc (10) is connected by external interface (4) with external host (1)；Outside main high-speed serial data communication connects
After mouth and control unit (2) receive the serial information of external host (1), processed by signal detection and serioparallel exchange etc., then pass
Pass primary processor (5)；Primary processor (5) by required by external host (1) read-write data content (including logical blocks of data ground
The information such as location and data length), each memory channel (11-14) is averagely allocated to by DMA channel (3).
The operator scheme all same of each follow-up memory channel, by taking memory channel 1 (11) as an example, is described as follows：
The data message of DMA channel (3) passes to the processor of passage 1 (21) by data buffer (20).
The processor of passage 1 (21) is responsible for for the LBA of data being converted into physical block address, and physical block address is then
Corresponded with storage medium；The processor of passage 1 (21) can be selected to deposit accordingly according to the Data Physical block address of required read-write
Storage media (41-43)；The processor of passage 1 (21) is responsible for distributing different physics to each storage medium (41-43) in passage
Block address, is responsible for the switching of control high-frequency clock on-off circuit (27), is responsible for control SD/MMC sequential interface circuit (23).
The D [0 of SD/MMC sequential interface circuit (23):7]/CMD data/address bus (25) directly and each storage medium (41-
43) and connect and share；The clock signal clk 1 (22) of SD/MMC sequential interface circuit (23) then accesses high-frequency clock on-off circuit
(27), and after chosen and switching, then each storage medium (41-43) is connected respectively to, such as is connected to storage medium 1 (41)
Clock signal clk 1-1 (25).
Each storage medium (41-43) is set to transmission state (transfer) by the processor of passage 1 (21)：Work as receipts
During to clock signal and respective protocol order, then the storage medium can immediately enter transmission working condition, so as to keep high speed
Read or write speed；When clock signal is not received, then other total interface pins of the storage medium remain that high impedance is defeated
Enter state, and the shared D [0 of other storage mediums:7]/CMD data/address bus (25).
High-frequency clock on-off circuit (27) can throw data switch or other data more by single-pole double throw data switch, hilted broadsword
On-off circuit is constituted；Can using switch cascade by the way of etc..Preferably selection is using the data switching circuit of single-pole double throw, level
Connection is no more than two-stage.
The clock of the input (common port) connection SD/MMC sequential interface circuit (23) of high-frequency clock on-off circuit (27)
Signal CLK1 (22)；The output end (throwing end) of high-frequency clock on-off circuit (27) is then connected respectively to each storage medium (41-
43) interface clock signal.The output end switching of high-frequency clock on-off circuit (27), is controlled by on-off circuit control signal (26)
System.
When the processor of passage 1 (21) is according to physical block address, it is determined that certain storage medium of required read-write, such as store
During medium 1 (41), the processor of passage 1 (21) is control high-frequency clock on-off circuit (27), and clock signal clk 1 (22) is switched
To CLK1-1 (25) port, then, the processor of passage 1 (21) can be written and read operation to storage medium 1 (41), complete storage
The selection of medium and reading writing working flow.
One solid state hard disc of vast capacity (10) of above-described embodiment includes N number of memory channel, and each memory channel contains
There is M storage medium, then the population size of hard disk is the M x N single storage medium capacity of x.
Fig. 3 shows a kind of vast capacity solid state hard disc (100) according to another preferred embodiment, is one
Total capacity based on 128GB eMMC storage mediums is the solid state hard disc with SATA interface of 2TB.Solid state hard disc (100) is including one
Individual external SATA data-interfaces (104), 32 primary processors (105), SATA high-speed serial data sequential interface and
Control unit (102), a DMA channel (103), 8 parallel memory channels (111-118) of same architecture.
Fig. 4 is that the further detail below of mono- memory channel (111) of above-mentioned Fig. 3 is described, including a data buffer
(120), the processor of a passage 1 (121), SD/MMC sequential interface circuit (123), a high-speed data switch of 1P2T
(127), the major part such as 2 eMMC of 128GB (141-142), additionally includes on-off circuit control signal Switch_Sel
(126), the clock signal clk 1 (22) of SD/MMC sequential interface circuit, eMMC shared D [0:7]/CMD data/address bus (125),
EMMC alone clock signal clk 1-1 (25), CLK1-2 (128) etc..
One solid state hard disc of vast capacity (100) of above-described embodiment includes 8 memory channels, and each memory channel contains
There are 2 128GB eMMC, then the population size of hard disk=8x 2x 128GB=2048GB=2TB；The other solid state hard disc
(100) 16 eMMC chips are only included, can be realized in 2.5 inch hard sizes.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (6)
1. a kind of implementation method of vast capacity solid state hard disc, it is characterised in that including：
Using the storage medium of band SD/MMC interfaces；
With multiple memory channels；
Multiple storage mediums with SD/MMC interfaces are accommodated in each memory channel；
Each storage medium in same passage is selected in the switching of the clock signal that each memory channel passes through SD/MMC interfaces come piece；
Wherein, the vast capacity solid state hard disc sets external interface, high-speed serial data communication interface and control unit, main process task
Device, DMA channel and multiple parallel memory channels, each memory channel are provided with memory channel processor, SD/MMC sequential
Interface circuit and high-frequency clock on-off circuit；
It is connected with external host by external interface；High-speed serial data communication interface and control unit receive the string of external host
Primary processor is passed to after row information；Primary processor is average by DMA channel by the read-write data content required by external host
Distribute to each memory channel；
Each memory channel processor is responsible for for the LBA of data being converted into physical block address, and physical block address then and
Storage medium is corresponded；The Data Physical block address that memory channel processor is read and write according to needed for, the corresponding storage of selection is situated between
Matter, while being responsible for distributing each storage medium in passage different physical block address, controlling high-frequency clock on-off circuit
Switching and control SD/MMC sequential interface circuits；
The data/address bus of the shared SD/MMC interfaces of each storage medium in each memory channel；
The SD/MMC interface clock lines of each memory channel are connected to the public input of high-frequency clock on-off circuit, and each storage is situated between
The clock line of matter is connected respectively to the output end of high-frequency clock on-off circuit.
2. a kind of implementation method of the vast capacity solid state hard disc according to claim 1, it is characterised in that the band
The storage medium of SD/MMC interfaces is any one in eMMC storage chips, iNAND storage chips or SD/MMC storage cards.
3. the implementation method of a kind of vast capacity solid state hard disc according to claim 1, it is characterised in that described is right
External tapping can be such as one of lower interface：SATA、eSATA、USB、IDE、SCSI、SAS、PCI/PCIE.
4. the implementation method of vast capacity solid state hard disc according to claim 1, it is characterised in that at the memory channel
Reason device is responsible for the physical block address of each storage medium in assignment channel, and according to physical block address come read-write needed for selecting
Storage medium.
5. the implementation method of vast capacity solid state hard disc according to claim 1, it is characterised in that at the memory channel
The clock signal of SD/MMC sequential interface circuits is switched and is connected to required reading by reason device by controlling high-frequency clock on-off circuit
The clock cable of the storage medium write.
6. the implementation method of vast capacity solid state hard disc according to claim 1, it is characterised in that the high-frequency clock is opened
Powered-down road can be constituted more by throwing data switch single-pole double throw data switch or hilted broadsword；And can be by the way of cascade is switched.
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| CN201410049417.7A CN103809920B (en) | 2014-02-13 | 2014-02-13 | Realizing method of ultra-large capacity solid state disk |
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| CN201410049417.7A CN103809920B (en) | 2014-02-13 | 2014-02-13 | Realizing method of ultra-large capacity solid state disk |
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| CN103809920B true CN103809920B (en) | 2017-05-17 |
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| CN106326753B (en) * | 2016-08-23 | 2020-04-28 | 记忆科技(深圳)有限公司 | Encryption Hub device realized based on EMMC interface |
| CN106980474B (en) * | 2017-04-01 | 2021-11-05 | 湖南博匠信息科技有限公司 | Data recorder based on PCIE interface |
| US10866746B2 (en) | 2017-12-28 | 2020-12-15 | Silicon Motion Inc. | Memory addressing methods and associated controller, memory device and host |
| TW202314512A (en) | 2017-12-28 | 2023-04-01 | 慧榮科技股份有限公司 | Flash memory controller, sd card device, method used in flash memory controller, and host for accessing sd card device |
| CN113672536B (en) * | 2021-08-26 | 2022-06-07 | 北京微纳星空科技有限公司 | Data storage system, storage module and data storage method |
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| CN101833989A (en) * | 2010-05-27 | 2010-09-15 | 华为技术有限公司 | Multi-interface solid state disk (SSD) as well as processing method and system thereof |
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| JP4060235B2 (en) * | 2003-05-22 | 2008-03-12 | 株式会社日立製作所 | Disk array device and disk array device control method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1896968A (en) * | 2005-07-14 | 2007-01-17 | 中国科学院电子学研究所 | Method for reading and writing capacity and speed expandable high-speed data solid disk |
| CN101398745A (en) * | 2007-09-29 | 2009-04-01 | 群联电子股份有限公司 | Solid disc storage system and solid disc controller of paralleling data access architecture |
| CN101593085A (en) * | 2008-05-28 | 2009-12-02 | 付建云 | Hard disk based on a plurality of FLASH storage cards |
| CN101833989A (en) * | 2010-05-27 | 2010-09-15 | 华为技术有限公司 | Multi-interface solid state disk (SSD) as well as processing method and system thereof |
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Application publication date: 20140521 Assignee: SAGE MICROELECTRONICS CORP. Assignor: Hangzhou Electronic Science and Technology Univ Contract record no.: 2018330000073 Denomination of invention: Realizing method of ultra-large capacity solid state disk Granted publication date: 20170517 License type: Exclusive License Record date: 20180615 |
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Effective date of registration: 20200525 Address after: Room a-b102-796, 198 Qidi Road, Xiaoshan Economic and Technological Development Zone, Xiaoshan District, Hangzhou, Zhejiang Province Patentee after: SAGE MICROELECTRONICS Corp. Address before: Hangzhou City, Zhejiang province 310018 Park in Xiasha Higher Education Patentee before: HANGZHOU DIANZI University |