WO2020077518A1

WO2020077518A1 - Hybrid storage device and access method

Info

Publication number: WO2020077518A1
Application number: PCT/CN2018/110359
Authority: WO
Inventors: 肖勇军; 孔飞; 耿剑锋; 何彪; 夏邓伟; 张广宇
Original assignee: 华为技术有限公司
Priority date: 2018-10-16
Filing date: 2018-10-16
Publication date: 2020-04-23
Also published as: CN111512374B; EP3839954A4; CN111512374A; EP3839954A1; US20210232512A1

Abstract

A hybrid storage device (200) comprises: an interface (201), for electrically connecting the hybrid storage device (200) to an external device (802), and exchanging data with the external device (802); at least one storage channel (202), electrically connected to the interface (201), for exchanging the data with the interface (201); a plurality of chip select lines (203), each chip select line (203) being electrically connected to one storage channel (202) of the at least one storage channel (202), for exchanging the data with said one storage channel (202); and a plurality of storage medium particles, each storage medium particle being electrically connected to one chip select line (203), for exchanging the data with said one chip select line (203), the plurality of storage medium particles comprising a non-volatile random access memory (NVRAM), and a flash memory.

Description

Hybrid storage device and access method

Technical field

The present application relates to the field of storage technology, in particular to a hybrid storage device and access method.

Background technique

With the rapid development of the Internet, more and more data needs to be stored. The existing memory includes two types, one is random access memory (random access memory, RAM), and the other is read-only memory (read only memory, ROM). The former loses power-off data and the latter does not lose power-loss data . In the field of mobile terminals, including but not limited to mobile phones, tablets (Pad), notebooks and other electronic products, existing RAM, such as low power double data rate (low power double data rate (LPDDR) memory, third-generation low power Double data rate (low power double data rate 3, LPDDR3) memory or fourth-generation low power double data rate (low power double data rate 4, LPDDR4) memory, used for program loading, running, etc .; and ROM or NAND Flash memory (NAND flash), such as embedded multimedia controller (embedded multi-media card, eMMC) or universal flash memory (universal flash storage, UFS), used for system files, user data (such as photos, movies, applications (application, APP) etc.) storage. RAM has the characteristics of fast access speed, but the data is lost when power is lost (volatile), while ROM has the characteristics that the data is not lost (non-volatile), but the access speed is slow.

In the existing storage solution, as shown in Figure 1, a volatile controller (Volatile Controller) is integrated in the system on chip (SoC) for external connection of low power double data rate (low power double data (rate, LPDDR) memory, such as LPDDR3 memory or / LPDDR4 memory, etc., and integrated non-volatile controller (Non-Volatile Controller), used to connect external NAND flash, such as eMMC4.5 / 5.0 / 5.1 or UFS2.0 /2.1 etc. LPDDR memory has high performance, low access latency (Latency), high read and write life (Endurance), relatively small capacity, expensive unit Gbit price, and data will be lost when power is turned off. On the contrary, NAND flash has low performance, large access delay, low read and write life, relatively large capacity, cheap unit Gbit, and no data loss when power is turned off.

Existing solutions are limited by cost constraints and LPDDR memory capacity is limited. In high-memory application scenarios (such as taking photos), some processes that originally resided in LPDDR memory need to be killed, or memory compression (ZRAM) When these processes need to be called again, they need to be reloaded, or decompressed and run first, which will cause a large delay when the system calls the memory again, and the efficiency of the system is low.

Summary of the invention

The embodiments of the present application provide a hybrid storage device and an access method, which are used to improve the overall storage performance of the storage device.

A first aspect of the present application provides a hybrid storage device, including: an interface for electrically connecting the hybrid storage device to an external device and exchanging data with the external device; at least one storage channel electrically connected to the An interface for interacting with the interface for the data; a plurality of chip select lines, wherein each chip select line is electrically connected to one of the at least one memory channel for interacting with the one memory channel The data; a plurality of storage medium particles, wherein each storage medium particle is electrically connected to a chip select line for interacting with the one chip select line for the data; wherein, the plurality of storage medium particles include non-easy Volatile random access memory NVRAM and flash memory. The embodiment of the present application introduces non-volatile random access memory (NVRAM) into the storage medium particles, and utilizes the characteristics of NVRAM with high performance, high read and write life, and non-volatile to achieve double speed The expansion of synchronous dynamic random (double data, rate, DDR) memory improves the overall storage performance of hybrid storage devices, reduces system latency, and improves system efficiency.

In a possible design, in a first implementation manner of the first aspect of the embodiments of the present application, at least one storage channel includes n storage channels, where n storage channels include m first storage channels and nm Second storage channels, each first storage channel is connected to j NVRAMs by j first chip selection lines in the plurality of chip selection lines, and each second storage channel passes through the plurality of chip selection lines K second chip selection lines are respectively connected to k flash memories, wherein the n and the m are both positive integers, and the n is greater than the m, and the j and the k are positive integers. At least one storage channel is connected to NVRAM and flash memory, and the access control of NVRAM and flash memory connected to each storage channel is realized by controlling the enable of the storage channel.

In a possible design, in a second implementation manner of the first aspect of the embodiments of the present application, at least one storage channel includes n storage channels, and each storage channel is connected to k of the plurality of chip select lines Chip selection line, wherein the k chip selection lines include j first chip selection lines and kj second chip selection lines, the n, the j, and the k are all positive integers, and the k Greater than the j; each first chip select line is connected to an NVRAM, and each second chip select line is connected to a flash memory. NVRAM and NAND are connected to the chip select line connected to the same storage channel. By controlling the enable of the chip select line connected to the storage channel, the access control to the NVRAM and NAND connected to each storage channel is realized.

In a possible design, in a third implementation manner of the first aspect of the embodiments of the present application, at least one storage channel includes n storage channels, where each storage channel is connected to the j chip select lines, where n and j are positive integers; each chip select line is connected to one NVRAM, and the one NVRAM is further connected to a flash memory to connect the each chip select line and the one Flash memory. The chip select lines connected to each storage channel are connected in series with NVRAM and flash memory, and perform different operations according to the type of instruction and the address indicated by the instruction to achieve access control to the NVRAM and flash memory connected in series on each storage channel.

Optionally, the flash memory is NAND flash memory.

Optionally, the interface includes: a physical layer device for exchanging data with an external device; a controller for enabling one or more storage channels in at least one storage channel, and for enabling communication with the one or One or more chip select lines electrically connected to a plurality of storage channels, and electrically connected to one of the one or more chip select lines through the one or more memory channels and the one or more chip select lines Or multiple storage media particles interact with each other.

Optionally, each storage medium particle is a grain.

Optionally, the hybrid storage device further includes a packaging structure for packaging the at least one storage channel, a plurality of chip selection lines, and the plurality of storage medium particles. The interface is used to electrically connect the plurality of storage medium particles located inside the package to the external device for exchanging data between the plurality of storage medium particles and the external device.

A second aspect of the present application provides a hybrid storage system, including: the hybrid storage device according to any one of the foregoing first aspect to the third implementation manner of the first aspect and the external device, wherein, the The external device includes a non-volatile controller electrically connected to the hybrid storage device and used to interact with the hybrid storage device for the data. The embodiment of the present application introduces non-volatile random access memory NVRAM into the storage medium particles, and utilizes the characteristics of high performance, high read-write life and non-volatile characteristics of NVRAM to improve the overall storage performance of the hybrid storage system and improve the hybrid storage The efficiency of the system.

The third aspect of the present application provides a method for accessing a hybrid storage device, receiving an instruction sent by an external device; determining the address indicated by the instruction or the type of the instruction; enabling one or more of at least one storage channel according to the address or type Memory channels, and one or more chip select lines among the plurality of chip select lines electrically connected to the one or more memory channels, wherein the plurality of chip select lines are electrically connected to a plurality of storage medium particles, respectively, the The plurality of storage medium particles include non-volatile random access memory NVRAM and flash memory; through the one or more storage channels and the one or more chip select lines, electrically connected to the one or more chip select lines One or more storage media particles interact with data. In the embodiment of the present application, the nonvolatile random access memory NVRAM is introduced into the storage medium, and the double-rate synchronous dynamic random memory is expanded and improved by utilizing the characteristics of NVRAM with high performance, high read and write life, and non-volatility. The overall storage performance of the hybrid storage device improves the efficiency of the hybrid storage system.

In a possible design, in a first implementation manner of the third aspect of the embodiments of the present application, the at least one storage channel includes at least one first storage channel and at least one second storage channel, and the at least one first storage channel A storage channel is connected to the NVRAM through a first chip select line, the at least one second storage channel is connected to the flash memory through a second chip select line, and the at least one storage channel is enabled according to the address or the type One or more memory channels and one or more chip select lines of the plurality of chip select lines electrically connected to the one or more memory channels, including: if the address of the instruction is the address of the NVRAM , Then the at least one first storage channel and the chip select line connected to the at least one first storage channel are enabled, and through the at least one first storage channel and the at least one first storage channel The connected chip select line accesses the NVRAM; if the address of the instruction is the address of the flash memory, the at least one second storage channel is enabled and connected to the at least one second storage channel Chip select line, and the access to the flash memory the at least one channel selected from the second ray and the second memory with said at least one channel connection. By controlling the enable of the memory channel and the chip select line connected to the memory channel, the access control to the NVRAM and flash memory connected to each memory channel is realized.

In a possible design, in a second implementation manner of the third aspect of the embodiments of the present application, the at least one storage channel is connected to at least one first chip selection line and at least one second chip selection line, the At least one first chip select line is connected to the NVRAM, the at least one second chip select line is connected to the flash memory, and one or more memory channels in at least one memory channel are enabled according to the address or the type And one or more chip select lines among the plurality of chip select lines electrically connected to the one or more memory channels, including: if the address of the instruction is the address of the NVRAM, enabling the at least One storage channel and the at least one first chip select line, and access the NVRAM through the at least one storage channel and the at least one first chip select line; if the address of the instruction is the address of the flash memory, Then, the at least one storage channel and the at least one second chip select line are enabled, and the flash memory is accessed through the at least one storage channel and the at least one second chip select line. By controlling the enabling of each storage channel and the first chip selection line and the second chip selection line connected to each storage channel, access control to the NVRAM and flash memory connected to each storage channel is realized.

In a possible design, in a third implementation manner of the third aspect of the embodiment of the present application, each chip select line is connected to one NVRAM, and the one NVRAM is further connected to a flash memory. The address or the type enables one or more memory channels in at least one memory channel, and one or more chip select lines in a plurality of chip select lines electrically connected to the one or more memory channels, including: If the type of the instruction is the type of a write operation instruction, the at least one storage channel and the one or more chip select lines are enabled, the write operation instruction is used to instruct writing of target data; The one or more storage channels and the one or more chip select lines, and the one or more storage medium particles electrically connected to the one or more chip select lines to exchange data, including: if the remaining NVRAM If the space is smaller than the size of the target data, write the target data on the flash memory; if the remaining space of the NVRAM is greater than or equal to the size of the target data, determine whether the target data is a hot number ; If the target data for said thermal data, the target data is written in the NVRAM on the; if the target data is not the thermal data, the target data is written in the flash memory. The chip select line connected to each storage channel is connected in series with NVRAM and flash memory, and performs different operations according to the type of instruction to achieve access control to the NVRAM and flash memory connected in series on each storage channel.

In a possible design, in a fourth implementation manner of the third aspect of the embodiment of the present application, each chip select line is connected to one NVRAM, and the one NVRAM is further connected to a flash memory. The address or the type enables one or more memory channels in at least one memory channel, and one or more chip select lines in a plurality of chip select lines electrically connected to the one or more memory channels, including: If the type of the instruction is the type of a read operation instruction, the at least one storage channel and the one or more chip select lines are enabled, the read operation instruction is used to instruct reading of target data; The one or more storage channels and the one or more chip select lines, and the one or more storage medium particles electrically connected to the one or more chip select lines, particle interaction data, including: determining whether the NVRAM exists The target data; if the target data exists in the NVRAM, read the target data from the NVRAM; if the target data does not exist in the NVRAM, read the target from the flash memory data. The chip select line connected to each storage channel is connected in series with NVRAM and flash memory, and performs different operations according to the type of instruction to achieve access control to the NVRAM and flash memory connected in series on each storage channel.

In the embodiment of the present application, a non-volatile random access memory NVRAM is introduced into the storage medium. Taking advantage of the characteristics of high performance, high read-write life and non-volatility of NVRAM, the overall storage performance of the hybrid storage device is improved, and the hybrid The efficiency of the storage system.

BRIEF DESCRIPTION

Figure 1 is a schematic diagram of the storage structure of the existing storage scheme;

2 is a schematic structural diagram of a hybrid storage device in an embodiment of the present application;

3 is another schematic structural diagram of a hybrid storage device in an embodiment of the present application;

4 is another schematic structural diagram of a hybrid storage device in an embodiment of the present application;

5 is another schematic structural diagram of a hybrid storage device in an embodiment of the present application;

6 is a functional schematic diagram of an interface in an embodiment of this application;

7 is a schematic diagram of the interface controlling storage medium particles in the embodiment of the present application;

8 is a schematic structural diagram of a hybrid storage system in an embodiment of this application;

FIG. 9 is a schematic flowchart of an access method of a hybrid storage device in an embodiment of this application.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments.

The "first" or "second" mentioned in this application document is used to distinguish similar objects, and does not have to be used to describe a specific order or sequence. In addition, the references to "including" or "having" and any variations thereof in this application document are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units need not be limited to Those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or equipment.

This application is applied to the field of storage media, and those skilled in the art have been researching and exploring new storage media. It is expected that it will have high performance and high read and write life similar to low power double data rate (LPDDR) It also has the characteristics of high density (large capacity) and non-volatility of NAND, which combines the advantages of the two. Resistive random access memory (ReRAM), ferroelectric random access memory (ferroelectric random access memory, FRAM), magnetoresistive random access memory (magnetic random access memory (MRAM), phase change memory (phase RAM) Memory, PCM) (such as 3D Xpoint), conductive bridge random access memory (conductive-bridging random access memory, cbRAM) and other new media are collectively called non-volatile random access memory (non-volatile random access memory, NVRAM). The working principles of these different NVRAM media are different. For example, ReRAM, according to the different voltages applied to the metal oxide, makes the resistance of the material in a high resistance state and a low resistance state, thereby recording "0" and "1". Another example is MRAM, which uses different magnetoresistances caused by different magnetization directions of the free layer and the fixed layer to record "0" and "1". Another example is PCM. Taking 3D Xpoint as an example, by heating the cell, the phase (crystalline and non-crystalline) of the memory cell is changed to express "0" and "1". This application does not limit the specific type of NVRAM. It should be noted that the flash memory involved in the embodiment of the present application may be NAND flash or NOR flash. For ease of understanding, the embodiment of the present application uses NAND flash as an example for description, which is simply referred to as NAND.

This application provides a hybrid storage device. Please refer to FIG. 2. An embodiment of the hybrid storage device 200 in the embodiment of the present application includes: an interface 201 for electrically connecting the hybrid storage device to an external device and interacting with the external device Data; at least one storage channel 202, electrically connected to the interface 201 for interacting with the interface 201; a plurality of chip select lines 203, wherein each chip select line is electrically connected to one of the at least one storage channel For exchanging the data with the one storage channel; a plurality of storage medium particles 204, wherein each storage medium particle is electrically connected to a chip select line for interacting with the data with the one chip select line; wherein The plurality of storage medium particles 204 include non-volatile random access memory NVRAM and flash memory. Optionally, the hybrid storage device further includes a packaging structure (not shown in the figure) for packaging the at least one storage channel 202, a plurality of chip selection lines 203, and the plurality of storage medium particles 204. The interface 201 is used to electrically connect the plurality of storage medium particles 204 located inside the package to the external device, for exchanging data between the plurality of storage medium particles 204 and the external device. The packaging can be implemented using existing packaging technology.

It can be understood that the electrical connection may be a physical direct electrical connection, or may be implemented by a field effect crystal (field effect transistor, FET) or other components, which is not specifically limited herein.

It should be noted that the interface 201 includes a physical layer device and a controller; where the physical layer device and external devices exchange data, the controller is used to enable one or more storage channels in at least one storage channel, and is used to enable and One or more chip select lines electrically connected to the one or more memory channels, and electrically connected to the one or more chip selects through the one or more memory channels and the one or more chip select lines One or more storage media particles of the line exchange data.

In the embodiment of the present application, the nonvolatile random access memory NVRAM is introduced into the storage medium, and the double-rate synchronous dynamic random memory is expanded and improved by utilizing the characteristics of NVRAM with high performance, high read and write life, and non-volatility. The overall storage performance of the hybrid storage device improves the efficiency of the hybrid storage system.

It should be noted that the hybrid storage device provides an external interface 201, for example, a peripheral peripheral component interconnection (PCIe) interface for interfacing with a system on chip (SoC); also It may be other interfaces, such as UFS interface, universal serial bus (USB) interface, etc., which is not limited here. The access of NVRAM and NAND is completed through this interface, and the internal architecture of NVRAM and NAND has three implementation schemes, which are called: 1) channel selection scheme; 2) chip selection selection scheme; and 3) series scheme. The different schemes are introduced separately below.

In a feasible implementation, as shown in FIG. 3, when the internal architecture of NVRAM and NAND is a channel selection scheme, the flash memory may be NAND, and at least one storage channel 202 includes n storage channels (CH1 to CHn), where , The n storage channels include m first storage channels (CH1 ~ CHm) and nm second storage channels (CHm + 1 ~ CHn), each first storage channel (any one of CH1 ~ CHm) passes The j first chip selection lines (CE1 to CEj) in the multiple chip selection lines are connected to j NVRAMs respectively, and each second storage channel (any one of CHm + 1 to CHn) passes through k in the multiple chip selection lines A second chip selection line (CE1 to CEk) is connected to k NANDs respectively, wherein the n and the m are both positive integers, and the n is greater than the m, and the j and the k are positive Integer.

In this channel selection scheme, for the storage channels CH1 to CHm, the connected storage media particles are all NVRAM, and there are j chip select lines on each channel that can be enabled, that is, chip select lines CE1 to CEj, The maximum number of m × j die (Die) concurrency can be achieved. In practical applications, it is necessary to balance the performance requirements with the power consumption constraints. For the storage channels CHm + 1 ~ CHn, the connected media are all NAND, and there are k chip select lines on each channel to enable, that is, chip select lines CE1 ~ CEk, the maximum achievable (nm) × The k Dies are concurrent, and in actual applications, trade-offs need to be made based on performance requirements and power consumption constraints. For the interface 201 (for example, it can be a PCIe Controller), it can be considered that two different devices are attached, namely an NVRAM device and a NAND device. When access to the NVRAM device is required, the Enable channels CH1 to CHm are enabled. One or more channels, and close channels CHm + 1 ～ CHn. Conversely, when access to the NAND device is required, one or more channels in the CHm + 1 to CHn channels are enabled, and the CH1 to CHm channels are closed.

It should be noted that Die is the die before the IC is not packaged. It is a small piece (Die) that is cut from a silicon wafer (wafer) by laser cutting and dividing the semiconductor wafer (wafer). Each Die is an independent unpackaged chip, which can be composed of one or more circuits, but will eventually be packaged as a unit to become our common memory particles, central processing unit (CPU) and other common chip. One Die in this embodiment corresponds to one storage medium particle, that is, one Die in this embodiment of the present application may be an NVRAM device or a NAND device.

In the implementation manner of the embodiment of the present application, the chip selection line connected to the same storage channel is connected to NVRAM or NAND, and access control of the NVRAM or NAND connected to the storage channel is realized by controlling the enabling and closing of the storage channel.

In a feasible implementation manner, as shown in FIG. 4, when the internal architecture of NVRAM and NAND is a chip selection option, the flash memory may be NAND, and at least one storage channel 202 includes n storage channels (CH1 to CHn), Each storage channel is connected to k chip selection lines, where k chip selection lines include j first chip selection lines (CE1 ～ CEj) and kj second chip selection lines (CEj + 1 ～ CEk), and the n , The j and the k are positive integers, and the k is greater than the j; each first chip selection line (any one of CE1 to CEj) is connected to one NVRAM, and each second chip selection line (CEj + 1 ～ CEk) Connect one NAND.

In this chip selection option, all storage channels, namely channels CH1 to CHn, are connected to both NVRAM and NAND storage media particles. Among them, the first chip selection line (CE1 ~ CEj) corresponds to NVRAM, and the second chip selection line (CEj + 1 ~ CEk) corresponds to NAND. For NVRAM, a maximum of n × j Die concurrency can be achieved, and for NAND, a maximum of n × (k-j) concurrency can be achieved. In practical applications, there is a trade-off between performance requirements and power consumption constraints. For the interface 201, it can be considered that two different devices are attached, namely NVRAM device and NAND device. When accessing the NVRAM device is enabled, the channels CH1 to CHn are enabled, and the first chip selection line CE1 to CEj are also enabled. , And close the second chip selection line CEj + 1 ～ CEk. Conversely, when access to the NAND device is required, the channels CH1 to CHn are enabled, the second chip selection lines CEj + 1 to CEk are simultaneously enabled, and the first chip selection lines CE1 to CEj are turned off.

In the implementation of the embodiment of the present application, the first chip selection line connected to the same storage channel is connected to NVRAM, the second chip selection line is connected to NAND, and the first chip selection line and the second chip selection line connected to the storage channel are controlled by Enable the access control of NVRAM and NAND connected to the storage channel.

In a feasible implementation, as shown in FIG. 5, when the internal architecture of NVRAM and NAND is a serial scheme, at least one storage channel 202 includes n storage channels (CH1 to CHn), where each storage channel is connected j chip selection lines (CE1 to CEj), where n and j are positive integers; each chip selection line is connected to one NVRAM, and the one NVRAM is further connected to one flash memory to connect each chip selection Line and the one flash memory.

In this series connection scheme, all storage channels and all chip selections have both NVRAM and NAND. All data entering NAND needs to go through NVRAM first, as shown in Figure 5. In this solution, the interface 201 needs to implement three basic functions, including: 1. Access and management of NVRAM; 2. Realization of data interaction between NVRAM and NAND; 3. Access and management of NAND, as shown in FIG. 6 Show.

The interface 201 sends a control signal (Control Signal) to the nonvolatile random access memory NVRAM, and implements access and management to the NVRAM through the data bus. The interface 201 can also access and manage the NAND, for example, garbage collection (GC) and other operations, and the interface 201 needs to send related control commands (Control Signal) to the NAND. To realize the data interaction between NVRAM and NAND, interface 201 is also required to send a control signal (Control Signal) to NVRAM and NAND, as shown in FIG. 7.

For the write operation instruction of the mixed storage medium, it is first written into NVRAM, and then it is determined whether data needs to be written into NAND according to the conditions such as data cold and hot conditions, remaining space of NVRAM, etc. For the read operation instruction of the mixed storage medium, first read the required data in NVRAM, and if there is no data to be read in NVRAM, continue to read the required data in NAND.

It should be noted that the cold and hot data can be set according to the actual situation. For example, data that is frequently accessed in a short time is regarded as hot data, and data that is not frequently accessed is regarded as cold data. Specifically, set a number of access times for each data. When the number of data access times exceeds a preset threshold within a period of time, the data is regarded as hot data, and data other than hot data is regarded as cold data.

In the implementation of the embodiment of the present application, the chip select line connected to each storage channel is connected in series with one NVRAM and one NAND, and different operations are performed according to the type of instruction received to realize the series connection of NVRAM and NAND on the storage channel Access control.

In addition to being used on mobile terminal devices such as mobile phones, the hybrid storage device in the embodiment of the present application can also be applied to devices involving a variety of mixed media applications, including tablet computers, notebooks, and servers.

The present application provides a hybrid storage system. Please refer to FIG. 8. An embodiment of the hybrid storage system 800 in the embodiment of the present application includes: a hybrid storage device 801 and an external device 802; wherein, the external device 802 includes a non-volatile The sexual controller 8021 is electrically connected to the hybrid storage device 801 and used to exchange data with the hybrid storage device 801; the hybrid storage device 801 is the hybrid storage device described in the above embodiments and any implementation manner. Optionally, the hybrid storage system 800 may further include: a volatile control module and a volatile storage medium device; the volatile control module is connected to the volatile storage medium device.

Referring to FIG. 9, an embodiment of the present application provides a method for accessing a hybrid storage device, which is applied to the hybrid storage device involved in the foregoing embodiments and various implementations. The hybrid storage device includes at least one storage channel and multiple slices. A line selection and a plurality of storage medium particles, the at least one storage channel is connected to the chip selection line, and the chip selection line is connected to the storage medium, the method includes: 901, receiving an instruction sent by an external device; 902, determining The address or type of the instruction indicated by the instruction; 903, one or more memory channels in at least one memory channel enabled according to the address or type, and one or more chip select lines electrically connected to the one or more memory channels or A plurality of chip select lines, wherein the plurality of chip select lines are electrically connected to a plurality of storage medium particles, the plurality of storage medium particles include non-volatile random access memory NVRAM and flash memory (that is, one or more are enabled according to the address or type Storage media particles); 904, through one or more storage channels and one or more chip select lines, and one electrically connected to one or more chip select lines A plurality of data storage media particles interact (with one or more storage media particles do interaction data).

It should be noted that the internal structure of NVRAM and flash memory (NAND in the embodiment of the present application) is different, and the control method is also different. The specific process is as follows:

(1) When at least one storage channel includes at least one first storage channel and at least one second storage channel, at least one first storage channel is connected to NVRAM through a first chip select line, and at least one second storage channel is connected through a second chip select line When the flash memory is connected, that is, when the channel selection scheme is adopted:

If the address of the instruction is the address of NVRAM, at least one first storage channel and the chip select line connected to the at least one first storage channel are enabled, and through the at least one first storage channel and the at least one first The chip select line connected to the storage channel accesses the NVRAM; if the address of the instruction is the address of the flash memory, at least one second storage channel and the chip select line connected to the at least one second storage channel are enabled and pass through at least one A second storage channel and a chip select line connected to the at least one second storage channel access the flash memory.

(2) When at least one storage channel is connected with at least one first chip selection line and at least one second chip selection line, the first chip selection line is connected to NVRAM, and the second chip selection line is connected to flash memory, that is, when the chip selection selection scheme is adopted :

If the address of the instruction is the address of NVRAM, enable at least one storage channel and at least one first chip select line, and access NVRAM through at least one storage channel and at least one first chip select line; if the address of the instruction is the address of the flash memory , At least one storage channel and at least one second chip select line are enabled, and the flash memory is accessed through at least one storage channel and at least one second chip select line.

(3) When each chip select line is connected to a NVRAM, and a NVRAM is further connected to a flash memory, that is, when the series scheme is used:

If the type of the instruction is the type of the write operation instruction, at least one storage channel and one or more chip select lines are enabled. The write operation instruction is used to indicate the writing of target data; if the remaining space of NVRAM is less than the size of the target data, then Write the target data on the flash memory; if the remaining space of the NVRAM is greater than or equal to the size of the target data, determine whether the target data is hot data; if the target data is hot data, write the target data on the NVRAM; if the target data is not For hot data, the target data is written on the flash memory.

(4) When each chip select line is connected to a NVRAM, and a NVRAM is further connected to a flash memory, that is, when the series scheme is used:

If the type of the instruction is the type of the read operation instruction, at least one storage channel and one or more chip select lines are enabled. The read operation instruction is used to instruct to read the target data; determine whether the target data exists in NVRAM; if the target data exists in NVRAM , The target data is read from NVRAM; if there is no target data in NVRAM, the target data is read from flash memory.

In the embodiment of the present application, the nonvolatile random access memory NVRAM is introduced into the storage medium, and the characteristics of high performance, high read-write life and non-volatility of NVRAM are used to improve the overall storage performance of the hybrid storage device and improve the system effectiveness.

In the several embodiments provided in this application, it should be understood that the disclosed system, device (apparatus) and method may be implemented in other ways. For example, the embodiments of the hybrid storage device described above are only schematic. Another point, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling through some interfaces, devices or modules, or The communication connection may be electrical, mechanical or other forms.

The hybrid storage device involved in the embodiments of the present application may be sold or used as an independent product, and may also be used as a computer-readable storage medium. The above is only the specific implementation of this application, but the scope of protection of this application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application. It should be covered by the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A hybrid storage device, including:

An interface for electrically connecting the hybrid storage device to an external device and exchanging data with the external device;

At least one storage channel, electrically connected to the interface, for interacting with the interface to the data;

A plurality of chip selection lines, wherein each chip selection line is electrically connected to one of the at least one storage channel, and is used to interact with the one storage channel for the data;

A plurality of storage medium particles, wherein each storage medium particle is electrically connected to a chip selection line, and is used to interact with the one chip selection line for the data;

Wherein, the plurality of storage medium particles include non-volatile random access memory NVRAM and flash memory.
The hybrid storage device according to claim 1, wherein:

The at least one storage channel includes n storage channels, wherein the n storage channels include m first storage channels and nm second storage channels, and each first storage channel passes through the plurality of chip select lines The j first chip selection lines in the are respectively connected to j NVRAMs, and each second storage channel is respectively connected to k flash memories through the k second chip selection lines in the plurality of chip selection lines, wherein, the n, Both m are positive integers, and n is greater than m, and j and k are both positive integers.
The hybrid storage device according to claim 1, wherein:

The at least one storage channel includes n storage channels, and each storage channel is connected to k chip selection lines of the plurality of chip selection lines, where the k chip selection lines include j first chip selection lines and kj second chip selection lines, the n, j, and k are all positive integers, and the k is greater than the j; each first chip selection line is connected to one NVRAM, and each second chip selection line The cable is connected to a flash memory.
The hybrid storage device according to claim 1, wherein:

The at least one storage channel includes n storage channels, where each storage channel is connected to j chip selection lines of the plurality of chip selection lines, and n and j are positive integers; each chip selection line It is connected to one NVRAM, and the one NVRAM is further connected to a flash memory to connect each chip select line and the one flash memory.
A hybrid storage system, including:

The hybrid storage device and the external device according to any one of claims 1 to 4, wherein the external device includes a non-volatile controller electrically connected to the hybrid storage device and used for mixing with the hybrid storage device The storage device interacts with the data.
A method for accessing a hybrid storage device, which includes:

Receive instructions sent by external equipment;

Determine the address indicated by the instruction or the type of the instruction;

Enabling one or more memory channels in at least one memory channel and one or more chip select lines in electrical connection with the one or more memory channels according to the address or the type , Wherein the plurality of chip selection lines are electrically connected to a plurality of storage medium particles, the plurality of storage medium particles including non-volatile random access memory NVRAM and flash memory;

Through the one or more storage channels and the one or more chip select lines, data is exchanged with one or more storage medium particles electrically connected to the one or more chip select lines.
The access method of the hybrid storage device according to claim 6, wherein the at least one storage channel includes at least one first storage channel and at least one second storage channel, and the at least one first storage channel passes through the first A chip select line is connected to the NVRAM, the at least one second storage channel is connected to the flash memory through a second chip select line, and the one or more storages in the at least one storage channel are enabled according to the address or the type The channel and one or more chip select lines among the plurality of chip select lines electrically connected to the one or more storage channels include:

If the address of the instruction is the address of the NVRAM, the at least one first storage channel and the chip select line connected to the at least one first storage channel are enabled and pass through the at least one first storage channel Accessing the NVRAM with the chip select line connected to the at least one first storage channel;

If the address of the instruction is the address of the flash memory, the at least one second storage channel and the chip select line connected to the at least one second storage channel are enabled and pass through the at least one second storage channel The chip select line connected to the at least one second storage channel accesses the flash memory.
The access method of the hybrid storage device according to claim 6, wherein the at least one storage channel is connected with at least one first chip select line and at least one second chip select line, and the at least one first chip select line A line is connected to the NVRAM, and the at least one second chip select line is connected to the flash memory,

Enabling one or more memory channels in at least one memory channel and one or more chips in a plurality of chip select lines electrically connected to the one or more memory channels according to the address or the type Line selection, including:

If the address of the instruction is the address of the NVRAM, the at least one storage channel and the at least one first chip select line are enabled, and through the at least one storage channel and the at least one first chip select Line access to the NVRAM;

If the address of the instruction is the address of the flash memory, the at least one storage channel and the at least one second chip select line are enabled, and through the at least one storage channel and the at least one second chip select Line access to the flash memory.
The access method of the hybrid storage device according to claim 6, wherein each chip select line is connected to one NVRAM, and the one NVRAM is further connected to a flash memory,

Enabling one or more memory channels in at least one memory channel and one or more chips in a plurality of chip select lines electrically connected to the one or more memory channels according to the address or the type Line selection, including:

If the type of the instruction is the type of a write operation instruction, the at least one storage channel and the one or more chip select lines are enabled, and the write operation instruction is used to instruct writing of target data;

The data interaction with the one or more storage media particles electrically connected to the one or more chip select lines through the one or more storage channels and the one or more chip select lines includes:

If the remaining space of the NVRAM is smaller than the size of the target data, write the target data on the flash memory;

If the remaining space of the NVRAM is greater than or equal to the size of the target data, it is determined whether the target data is hot data;

If the target data is the hot data, write the target data on the NVRAM;

If the target data is not the hot data, write the target data on the flash memory.
The access method of the hybrid storage device according to claim 6, wherein each chip select line is connected to one NVRAM, and the one NVRAM is further connected to a flash memory,

Enabling one or more memory channels in at least one memory channel and one or more chips in a plurality of chip select lines electrically connected to the one or more memory channels according to the address or the type Line selection, including:

If the type of the instruction is the type of a read operation instruction, the at least one storage channel and the one or more chip select lines are enabled, and the read operation instruction is used to instruct reading of target data;

The data interaction with the one or more storage media particles electrically connected to the one or more chip select lines through the one or more storage channels and the one or more chip select lines includes:

Determine whether the target data exists in the NVRAM;

If the target data exists in the NVRAM, read the target data from the NVRAM;

If the target data does not exist in the NVRAM, the target data is read from the flash memory.