CN103198039A

CN103198039A - Data transmitting controller and hybrid storage device thereof

Info

Publication number: CN103198039A
Application number: CN2013101357295A
Authority: CN
Inventors: H·F·黄; 吴郎
Original assignee: WUXI YUNDONG TECHNOLOGY DEVELOPMENT Co Ltd
Current assignee: WUXI YUNDONG TECHNOLOGY DEVELOPMENT Co Ltd
Priority date: 2013-04-19
Filing date: 2013-04-19
Publication date: 2013-07-10

Abstract

The invention belongs to the technical field of computer storage, and discloses a data transmitting controller comprising a command issuing module, a first terminal, a second terminal, a pushing module, a logic controlling module and a buffering storage device. The command issuing module is connected to a main controlling line in a coupling manner and is used for receiving queue commands. The first terminal is connected to a main data line in a coupling manner. The second terminal is connected to a non-volatile storage device in a coupling manner. The pushing module is used for receiving the queue commands stored in the command issuing module and splitting the queue commands into a plurality of sub-queue commands. The logic controlling module is used for receiving the sub-queue commands sequentially, splitting the sub-queue commands into a plurality of page commands, and transmitting the page commands to the first terminal and the second terminal according to the direction of data transmission. The buffering storage device is used for storing data transmitted between the first terminal and the second terminal temporarily. By the arrangement, errors of data transmission between a volatile storage device and the non-volatile storage device are avoided effectively, and loss of important data is prevented; stability and scalability of a hybrid storage device are improved; and meanwhile, manufacturing cost of the hybrid storage device is reduced.

Description

Data transmission controller and hybrid storage device thereof

Technical Field

The present invention relates to the field of computer storage technologies, and in particular, to a data transfer controller for performing a data transfer operation between a nonvolatile memory and a volatile memory in a hybrid memory device, and a hybrid memory device thereof.

Background

NAND Flash memories based on Flash Memory (Flash Memory) technology are gradually replacing mechanical hard disks and becoming storage media for large-capacity data. It has read/write life as long as ten thousand times, and has the advantages of small size, good shock resistance, etc.

When data in a NAND flash memory is read/written, the read/write operation is generally performed in units of pages (pages). One page of data is typically 2KB or 4 KB; a Block of data (Block) typically includes 64, 128 or 256 pages of data.

The hybrid memory device configured by combining the nonvolatile memory and the volatile memory fully utilizes the advantages of high operation speed and large bandwidth of the volatile memory (DRAM), low manufacturing cost, long service life, large storage capacity and good shock resistance of the nonvolatile memory (NAND flash memory), and is becoming the leading technology in the technical field of computer storage.

However, in the process of controlling data transmission between the volatile memory and the nonvolatile memory, the data transmission controller in the hybrid storage device in the prior art cannot find data transmission errors in time, which results in loss of important data, and thus poor reliability of the hybrid storage device.

Meanwhile, the data transfer controller in the hybrid storage device in the prior art is generally provided with a CPU, and the CPU is connected to a control bus connecting the volatile memory and the nonvolatile memory to control data transfer between the volatile memory and the nonvolatile memory, so that the manufacturing cost of the data transfer controller with such a structure is increased.

Finally, in the data transfer controller of the hybrid memory device in the prior art, the data lacks autonomy during the mutual transfer between the volatile memory and the nonvolatile memory, so that it is necessary to check and correct the error of the data during the transfer by software loaded in the data transfer controller, such as ECC (error-detection correction), but this will increase the burden of the host.

In view of the above, there is a need for an improved data transmission controller and hybrid storage device thereof in the prior art to solve the above problems.

Disclosure of Invention

An object of the present invention is to overcome the deficiencies in the prior art, and to provide a data transmission controller for timely detecting and correcting transmission errors during data transmission between a volatile memory and a non-volatile memory, preventing loss of important data, and improving autonomy of data during transmission.

To achieve the above object, the present invention discloses a data transmission controller, comprising:

the command issuing module is coupled to the control bus and receives the queue command;

a first port coupled to the data bus;

a second port coupled to a non-volatile memory;

the pushing module receives the queue command stored by the command issuing module and splits the queue command into a plurality of sub-queue commands;

the logic control module receives the sub-queue commands in sequence, splits the sub-queue commands into a plurality of page commands, and respectively sends the page commands to the first port or the second port according to the data transmission direction;

a buffer memory configured to temporarily store data transmitted between the first port and the second port.

As a further improvement of the present invention, interface buses are arranged between the command issuing module and the control bus, between the first port and the data bus, and between the second port and the nonvolatile memory.

As a further development of the invention, the interface bus comprises I²C、SMBUS。

As a further development of the invention, the buffer memory comprises at least one FIFO memory.

As a further improvement of the present invention, the data transmission controller further includes a status management register, and the status management register acquires configuration information of the nonvolatile memory from the control bus and sends the configuration information to the command issuing module.

As a further improvement of the present invention, the configuration information is split into a plurality of sub-configuration information in the push module, and the sub-configuration information is bound to a plurality of sub-queue commands formed by splitting the queue commands by the push module, and is sent to the logic control module.

As a further improvement of the present invention, the logic control module splits the sub-configuration information into a plurality of pages of configuration information, and respectively sends the pages of configuration information to the first port or the second port according to the data transmission direction.

As a further improvement of the present invention, the page configuration information and the page command are bound to each other in the first port or the second port, respectively, and data access is performed to the volatile memory and the nonvolatile memory in units of pages.

Another object of the present invention is to overcome the disadvantages of the prior art and to provide a hybrid memory device with high reliability, high expandability and significantly reduced manufacturing cost.

To achieve the above object, the present invention discloses a hybrid storage device, comprising:

the data transmission controllers are respectively connected with a nonvolatile memory and are connected with a plurality of volatile memories in parallel through the data bus; wherein,

the data transmission controller includes:

a first port coupled to the data bus;

a second port coupled to a non-volatile memory;

As a further improvement of the present invention, the capacity of the nonvolatile memory is greater than or equal to the capacity of the volatile memory.

Compared with the prior art, the invention has the beneficial effects that: and splitting the queue command and the configuration information twice in the push module and the logic control module respectively, and binding the page command and the page configuration information with each other and then transmitting data to the volatile memory and the nonvolatile memory by taking a page as a unit. Through the arrangement, transmission errors in the data transmission process between the volatile memory and the nonvolatile memory can be timely found and corrected, loss of important data is prevented, and autonomy of the data in the transmission process is effectively improved; the reliability and the expansibility of the hybrid storage device are improved; while reducing the manufacturing cost of the hybrid memory device.

Drawings

Fig. 1 is a schematic structural diagram of a data transmission controller according to a first embodiment of the present invention;

FIG. 2 is a schematic structural diagram illustrating a data transfer controller transferring data from a volatile memory to a non-volatile memory according to a first embodiment;

FIG. 3 is a schematic structural diagram illustrating a data transfer controller transferring data from a non-volatile memory to a volatile memory according to a first embodiment;

FIG. 4 is a schematic diagram of a page command splitting a queue command Q into an m n matrix;

FIG. 5 is a schematic illustration of page data corresponding to the page commands of the m n matrix of FIG. 4;

FIG. 6 is a schematic diagram of the structure of the buffer memory shown in FIG. 1;

fig. 7 is a schematic structural diagram of a data transmission controller according to a second embodiment of the present invention;

fig. 8 is a schematic structural diagram of a hybrid memory device according to a third embodiment of the present invention.

Detailed Description

The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.

Example one

Please refer to fig. 1 to 6, which illustrate an embodiment of a data transmission controller according to the present invention.

Referring to fig. 1, a data transmission controller 100 is connected to a control bus 10 and a data bus 20 via an interface bus 110. The data transmission controller 100 may obtain a queue command Q through the control bus 10; and acquires data D transferred from the volatile memory 108 to the nonvolatile memory 107 or data D transferred from the nonvolatile memory 107 to the volatile memory 108 through the data bus 20.

In the present embodiment, the data transmission controller 100 includes: a command issuing module 101 coupled to the control bus 10 and receiving a queue command Q; a first port 104 coupled to the data bus 20; a second port 105 coupled to a non-volatile memory 107; the push module 102 receives the queue command Q stored in the register 101 and splits it into several sub-queue commands (Q)₁、Q₂.....Q_m) Then sent to the logic control module 103; logic control module 103, in turn, receives sub-queue commands (Q)₁、Q₂.....Q_m) And split into several page commands (Q)₁₁、Q₁₂....Q_mn) And commands (Q) pages according to the direction of data transfer₁₁、Q₁₂....Q_mn) To the first port 104 or the second port 105; a buffer memory 106 configured to temporarily store data transmitted between the first port 104 and the second port 105.

Specifically, the command issuing module 101 is composed of a plurality of command registers (not shown).

In a preferred embodiment, the nonvolatile memory 107 is a NAND flash memory; the volatile memory 108 is a Dynamic Random Access Memory (DRAM).

The nonvolatile memory 107 may be a phase change memory (FCM), a ferroelectric memory (FeRAM), a magnetic recording random access memory (MRAM), an Ovonic Unified Memory (OUM), or a resistance ram (rram).

In this embodiment, the data bus 20 may also be connected to the peripheral I/O118 through the PCI-e interface 119, so as to obtain data from the outside to be written into the NAND flash memory (the non-volatile memory 107) or from the NAND flash memory (the non-volatile memory 107) to an electronic device (not shown) having storage, communication, and data processing functions, which is connected to the peripheral I/O118, for example: an external storage device or a communication device (such as a video card, a network card, or an SSD) based on the PCI-e interface 119.

In the present embodiment, an interface bus 110 is configured between the command issuing module 101 and the control bus 10, and is used for obtaining a queue command Q from the control bus 10; the same interface buses 110 are also respectively provided between the first port 104 and the data bus 20 and between the second port 105 and the nonvolatile memory 107 for data transmission.

Specifically, the interface bus 110 includes I²C. SMBUS, and preferably SMBUS. SMBUS (System Management bus) is a two-wire serial bus. It abandons the traditional forms of the control bus and the Data bus of the central processor, so that the Data signal (Data), the clock signal (CLK) and the Address signal (Address) can be transmitted through the interface bus 110.

Referring to fig. 6, in the present embodiment, the buffer memory 106 includes at least one FIFO memory (1061, 1062.. 106k), and preferably two FIFO memories.

The FIFO memory is a First-In First-Out (First In First Out) memory. In the present embodiment, a status pin (not shown) indicating a Buffer status (Buffer Full, Buffer empty) is added to the FIFO memory. Both the first port 104 and the second port 105 in fig. 6, which are connected to the FIFO memories (1061, 1062.. 106k) through status pins, perform control of operations using the status of the FIFO memories (1061, 1062.. 106 k).

In the case of transferring data D from the volatile memory 108 to the non-volatile memory 107, if the second port 105 detects that the status of one of the FIFO memories is (Buffer Full ) through the status pin, the FIFO memory in the status of (Buffer Full ) sends a request call signal to the second port 105, and immediately calls the data in the FIFO memory through the second port 105. And vice versa when data is transferred from the non-volatile memory 107 to the volatile memory 108.

Note that data pages (pages) stored in the FIFO memories (1061, 1062.. 106k) are the basic unit of operation. Referring to fig. 4 and 5 in combination, in the process of transferring data D of a certain size from the volatile memory 108 to the non-volatile memory 107 or transferring data from the non-volatile memory 107 to the volatile memory 108, the queue command Q corresponding to the data D of a certain size may be split into m sub-queue commands (Q) in the push module 102₁、Q₂.....Q_m) And each sub-queue command (Q)₁、Q₂.....Q_m) In turn, can be split into n page commands in the logic control module 103, thereby forming page commands of an m × n matrix as shown in fig. 4.

Meanwhile, the host 50 divides the data to be transferred between the volatile memory 108 and the nonvolatile memory 107 into Page data of an m × n matrix in advance with a Page (Page) size. Specifically, the splitting of the page command depends first on the size of the data D and the physical storage characteristics of the non-volatile memory 107, such as: how many KB's per Page of data (Page) each Block of data (Block) includes how many pages (Page).

First, we will describe in detail the process of transferring data D from the volatile memory 108 to the non-volatile memory 107.

Referring to fig. 1 and fig. 2 in combination, the command issuing module 101 obtains a queue command Q corresponding to data D of a certain size from the control bus 10 through the interface bus 110, and then sends the queue command Q to the pushing module 102, and the pushing module 102 splits the queue command Q into mSub-queue command (Q)₁、Q₂.....Q_m)。

Specifically, the push module 102 first sends a first sub-queue command Q₁To the logic control module 103, and then the logic control module 103 sends the first sub-queue command Q₁Splitting into n page commands (Q)₁₁、Q₁₂......Q_1n)。

Logic control module 103 first puts the first sub-queue command Q₁Page command Q in (1)₁₁Sent to the first port 104, and the first port 104 sends the page command Q₁₁The page command Q is fetched from the volatile memory 108 via the interface bus 110₁₁Corresponding page data D₁₁And Q the page command₁₁And page data D₁₁Bound in the first port 104 and sent to the FIFO 1061 in the buffer memory 106.

As-page data D₁₁After completing the operation stored in the FIFO memory 1061, the first port 104 feeds back a transmission success signal to the logic control module 103.

Then, the FIFO 1061 sends a request call signal to the second port 105, and the second port 105 calls the page data D in the FIFO 1061₁₁。

Next, the logic control module 103 will issue a first sub-queue command Q₁Page command Q in (1)₁₂Sent to the first port 104, written into the non-volatile memory 107 through the buffer memory 106, the second port 105 and the interface bus 110, and executed in a cyclic and reciprocating manner until the first sub-queue command Q is sent₁Corresponding all page data (D)₁₁、D₁₂....D_1n) And finishing all the execution.

When the first sub-queue command Q₁After the execution is completed, the logic control module 103 feeds back a transmission success signal to the push module 102, and executes the second sub-queue command Q₂And so on until the execution of the queue command Q is completed, thereby effecting the transfer of data D from the volatile memory 108 to the non-volatile memoryA sexual memory 107.

If sub-queue command Q₁Corresponding data D of a certain page_1jWhen the page data D is not successfully stored in the buffer memory 106_1jCorresponding page command Q_1jFeeding back a transmission failure signal to the logic control module 103 through the first port 104; if sub-queue command Q₁Corresponding data D of a certain page_1jWhen the page data D is not successfully transmitted from the buffer memory 106 to the second port 105_1jCorresponding page command Q_1jA transmission failure signal is fed back to the logic control module 103 through the second port 105.

Based on the two page data D_1jIn case of transmission failure, the logic control module 103 sends the transmission failure signal to the push module 102; the page command Q with the transmission failure is sent by the push module 102_1jCorresponding sub-queue command Q₁Resends the command to the logic control module 103, and resends the sub-queue command Q₁Splitting into n page commands (Q)₁₁、Q₁₂....Q_1n) And resumes the sub-queue command Q₁N page commands (Q) in₁₁、Q₁₂....Q_1n) Corresponding page data (D)₁₁、D₁₂....D_1n) Transmit again until the queue command Q₁Corresponding page data (D)₁₁、D₁₂....D_1n) Successfully transferred from volatile memory 108 to non-volatile memory 107.

Specifically, in this embodiment, the nonvolatile memory 107 is a NAND flash memory. Page data (D)₁₁、D₁₂....D_1n) One block data D in the NAND flash memory₁. When data D is written from the DRAM (volatile memory 108) to the NAND flash memory (non-volatile memory 107), data D can be block data D for each of the data D by the data transfer controller 100_iAnd belongs to the block data D_iAll page data (D)_i1、D_i2....D_in) The transmission condition of the data transmission system is monitored in real time, thereby timely finding out errors in the data transmission process,the accidental loss of important data in the transmission process is prevented, and the reliability and the stability of data transmission between the volatile memory 108 and the nonvolatile memory 107 are improved.

Referring to fig. 4, 5 and 6, the buffer memory 106 includes a plurality of FIFO memories (1061, 1062.. 106 k). As-page data D_ijAfter storing in the FIFO memory 1061, the logic control module 103 sends the sub-queue command Q_iSecond page command Q in (1)_ij+1Sends it to the first port 104 and obtains the page command Q through the interface bus 110_ij+1Corresponding page data D_ij+1. At the same time, the first port 104 will issue a page command Q_ij+1Corresponding page data D_ij+1To FIFO memory 1062.

In this embodiment, when the page data D is completed in the FIFO memory 1061_ijIn the storing operation, the FIFO memory 1061 sends a request call signal to the second port 105, and then the second port 105 calls the page data D in the FIFO memory 1061_ijAnd sent to the non-volatile memory 107 via the interface bus 110.

When the second port 105 will transfer the page data D_ijAfter writing into the non-volatile memory 107 through the interface bus 110, the second port 105 feeds back a feedback signal of successful transmission to the logic control module 103.

If the second port 105 fails to transfer the page data D_ijUnder the condition of writing into the nonvolatile memory 107 through the interface bus 110, the second port 105 feeds back a data transmission failure signal to the logic control module 103, and the logic control module 103 sends the transmission failure signal to the push module 102; the push module 102 sends the page command Q corresponding to the page data with failed transmission_ijSub-queue command Q to which it belongs_iAll page command (Q) in_i1、Q_i2....Q_ij、Q_ij+1....Q_in) Corresponding page data (D)_i1、D_i2....D_ij、D_ij+1....D_in) Transmit again until the queue command Q_iCorresponding page data(D_i1、D_i2....D_ij、D_ij+1....D_in) Successfully from volatile memory 108 to non-volatile memory 107.

In the present embodiment, all the page data (D)_i1、D_i2....D_ij、D_ij+1....D_in) Constitute block data D_i(ii) a All block data (D)₁、D₂....D_m) Constituting data D that needs to be transferred from the volatile memory 108 to the non-volatile memory 107.

Since the buffer memory 106 includes a plurality of FIFO memories (1061, 1062.. 106k), when the FIFO memory 1061 holds the page data D, the page data D is stored_ijAnd the page data D_ijWhen not being invoked by the second port 105, the first port 104 may issue a sub-queue command Q_iPage command Q in (1)_ij+1Corresponding page data D_ij+1Bind page command Q_ij+1And then stored in the FIFO memory 1062.

Note that the page data D_ijThe speed of transfer from the first port 104 into the FIFO memory 1061 is greater than the page data D_ijSpeed of transfer from the FIFO memory 1061 to the second port 105. Therefore, several FIFO memories (1061, 1062.. 106k) are provided in the buffer memory 106 to improve the transmission efficiency of data.

Next, we will explain in detail the process of transferring the data D from the nonvolatile memory 107 to the volatile memory 108.

Referring to fig. 1 and fig. 3 in combination, the command issuing module 101 obtains a queue command Q corresponding to data D of a certain size from the control bus 10 through the interface bus 110, and then sends the queue command Q to the pushing module 102, and the pushing module 102 splits the queue command Q into m sub-queue commands (Q)₁、Q₂.....Q_m)。

Specifically, the push module 102 first sends a first sub-queue command Q₁To the logic control module 103, and then the logic control module 103 willFirst sub-queue command Q₁Splitting into n page commands (Q)₁₁、Q₁₂......Q_1n)。

Logic control module 103 first puts the first sub-queue command Q₁Page command Q in (1)₁₁Sent to the second port 105, and the second port 105 sends the page command Q₁₁The page command Q is retrieved from the non-volatile memory 107 via the interface bus 110₁₁Corresponding page data D₁₁(ii) a And Q the page command₁₁And page data D₁₁Bound in the second port 105 and sent to the FIFO 1061 in the buffer memory 106.

As-page data D₁₁After completing the operation stored in the FIFO memory 1061, the second port 105 feeds back a transmission success signal to the logic control module 103.

Next, the logic control module 103 will issue a first sub-queue command Q₁Page command Q in (1)₁₂Sent to the second port 105, written into the volatile memory 108 through the buffer memory 106 and the first port 104, and executed in a cyclic and reciprocating manner until the first sub-queue command Q is transmitted₁Corresponding all page data (D)₁₁、D₁₂....D_1n) And finishing all the execution.

When the first sub-queue command Q₁After the execution is completed, the logic control module 103 feeds back a successful sending signal to the push module 102, and executes the second sub-queue command Q₂And so on until the execution of the queue command Q is completed, thereby effecting the transfer of data D from the non-volatile memory 107 to the volatile memory 108.

If sub-queue command Q₁Corresponding data D of a certain page_1jWhen the page data D is not successfully stored in the buffer memory 106_1jCorresponding page command Q_1jFeeding back a transmission failure signal to the logic control module 103 through the second port 105; if sub-queue command Q₁Corresponding data D of a certain page_1jWhen it is not successfully sent from the buffer memory 106 to the first port 104, it is sentPage data D_1jCorresponding page command Q_1jA transmission failure signal is fed back to the logic control module 103 through the first port 104.

Based on the two page data transmission failures, the logic control module 103 sends the sending failure signal to the pushing module 102; the page command Q with the transmission failure is sent by the push module 102_1jCorresponding sub-queue command Q₁Resends the command to the logic control module 103, and resends the sub-queue command Q₁Splitting into n page commands (Q)₁₁、Q₁₂....Q_1n) And resumes the sub-queue command Q₁Page data (D) corresponding to all page commands in the page₁₁、D₁₂....D_1n) Transmit again until the queue command Q₁Corresponding page data (D)₁₁、D₁₂....D_1n) Successfully from non-volatile memory 107 to volatile memory 108.

Specifically, in this embodiment, the nonvolatile memory 107 is a NAND flash memory. Page data (D)₁₁、D₁₂....D_1n) One block data D in the NAND flash memory₁All block data (D)₁、D₂....D_m) Constituting data D that needs to be transferred from the non-volatile memory 107 to the volatile memory 108.

When a certain large data D is transferred from the nonvolatile memory 107 to the volatile memory 108, the data D can be each block data D by the data transfer controller 100_iAnd belongs to the block data D_iAll page data (D)_i1、D_i2....D_in) The transmission condition of the data transmission system is monitored in real time, so that errors in the data transmission process can be found in time, accidental loss of the data in the transmission process can be prevented, and the reliability and stability of data transmission between the volatile memory 108 and the nonvolatile memory 107 can be improved.

Referring to fig. 4, 5 and 6, the buffer memory 106 includes a plurality of FIFO memories (1061, 1062.. 106 k). As-page dataD_ijAfter storing in the FIFO memory 1061, the logic control module 103 sends the sub-queue command Q_iSecond page command Q in (1)_ij+1Sent to the second port 105 and gets the page command Q through the interface bus 110_ij+1Corresponding page data D_ij+1. At the same time, the first port 104 will issue a page command Q_ij+1Corresponding page data D_ij+1To FIFO memory 1062.

In this embodiment, when the page data D is completed in the FIFO memory 1061_ijIn the storing operation, the FIFO memory 1061 sends a request call signal to the first port 104, and then the first port 104 calls the page data D in the FIFO memory 1061_ijAnd sent to the volatile memory 108 via the interface bus 110.

When the first port 104 will page data D_ijAfter writing to the volatile memory 108, the first port 104 feeds back a transmission success signal to the logic control module 103.

If the first port 104 fails to transfer the page data D_ijUnder the condition of writing into the volatile memory 108, the first port 104 feeds back a data transmission failure signal to the logic control module 103, and the logic control module 103 sends the transmission failure signal to the push module 102; the push module 102 sends the page command Q corresponding to the page data with failed transmission_ijSub-queue command Q to which it belongs_iAll page command (Q) in_i1、Q_i2....Q_ij、Q_ij+1....Q_in) Corresponding page data (D)_i1、D_i2....D_ij、D_ij+1....D_in) Transmit again until the queue command Q_iCorresponding page data (D)_i1、D_i2....D_ij、D_ij+1....D_in) Successfully from non-volatile memory 107 to volatile memory 108.

Since the buffer memory 106 includes a plurality of FIFO memories (1061, 1062.. 106k), when the FIFO memory 1061 holds the page data D, the page data D is stored_ijAnd the page data D_ijIs not covered by the first endWhen port 104 is invoked, the second port 105 may issue a sub-queue command Q_iPage command Q in (1)_ij+1Corresponding page data D_ij+1Bind page command Q_ij+1And then stored in the FIFO memory 1062.

Note that the page data D_ijThe speed of transfer from the FIFO memory 1061 into the first port 104 is greater than the page data D_ijThe speed of transfer from the second port 105 to the FIFO memory 1061. Therefore, several FIFO memories (1061, 1062.. 106k) are provided in the buffer memory 106 to improve the transmission efficiency of data.

Example two

Please refer to fig. 7, which shows a second embodiment of a data transmission controller 100 according to the present invention.

Referring to fig. 1, the main difference between the present embodiment and the first embodiment is that the data transmission controller 100 further includes a status management register 109, the status management register 109 is connected to the control bus 10 through an interface bus 110, and the control bus 10 is connected to the host 50 through the interface bus 110, and is configured to obtain configuration information in the nonvolatile memory 107 through the control bus 10 and send the configuration information to the command issuing module 101. The status management Register 109 is composed of a plurality of registers (registers).

Specifically, the configuration information includes: data sequence number, data error correction code, data source tracing information, data destination information, block data size and page data size.

When the NAND flash memory (the non-volatile memory 107) is electrically connected to the data transfer controller 100 and the system is powered on, the host 50 automatically obtains how many blocks (blocks) and how many pages (pages) each Block (Block) includes in the NAND flash memory (the non-volatile memory 107) through the control bus 10, thereby obtaining the Block data size and the Page data size.

The configuration information is split into several sub-configuration information in the pushing module 102, and the sub-configuration information is compared with the pushed moduleMultiple sub-queue commands (Q) formed by splitting queue command Q at block 102₁、Q₂....Q_m) Bound with each other and sent to the logic control module 103. The logic control module 103 splits the sub-configuration information into a plurality of pages of configuration information, and sends the pages of configuration information to the first port 104 or the second port 105 according to the data D transmission direction.

Referring to fig. 4 and 5, the page configuration information is further associated with page commands (Q) one by one, respectively₁₁、Q₁₂....Q_mn) The first port 104 or the second port 105 are bound to each other, and data access is performed to the volatile memory 108 and the volatile memory 107 in page units.

When page data (D) is fetched from the volatile memory 108 through the first port 104₁₁、D₁₂....D_mn) And then sent to the buffer memory 106. Similarly, when page data (D) is fetched from the nonvolatile memory 107 through the second port 105₁₁、D₁₂....D_mn) And then sent to the buffer memory 106. The physical memory characteristics of the NAND flash memory (the nonvolatile memory 107) can be accurately acquired by the state management register 109, and the page data (D) is guided by the page configuration information₁₁、D₁₂....D_mn) Writing into or reading page data (D) from the NAND flash memory (non-volatile memory 107)₁₁、D₁₂....D_mn) And transferred to the volatile memory 108.

Therefore, after the push module 102 and the logic control module 103 split the queue command Q twice, all the page commands (Q) are sent to the logic control module 103₁₁、Q₁₂......Q_mn) And the page configuration information is bound, so that the addressing and guiding functions can be provided for the data transferred from the volatile memory 108 to the NAND flash memory (the non-volatile memory 107) or the data transferred from the NAND flash memory (the non-volatile memory 107) to the volatile memory 108 through the page configuration information, thereby effectively improving the autonomy of the data in the transfer process of the non-volatile memory 107 and the volatile memory 108.

In this embodiment, the volatile memory 108 is a Dynamic Random Access Memory (DRAM).

EXAMPLE III

Please refer to fig. 8, which illustrates an embodiment of a hybrid memory device 200 according to the present invention.

In the present embodiment, a hybrid storage device 200 includes:

a plurality of data transfer controllers 100 are provided in parallel with the control bus 10 and the data bus 20, respectively, and the data transfer controllers 100 are connected to one nonvolatile memory 107a, 107b, respectively, and are connected to two volatile memories 108a, 108b in parallel via the data bus 20.

As shown in fig. 1, 4 and 5, in the present embodiment, the data transmission controller 100 includes:

a command issuing module 101 coupled to the control bus 10 and receiving a queue command Q; a first port 104 coupled to the data bus 20; a second port 105 coupled to a non-volatile memory 108a, 108 b; the pushing module 102 receives the queue command Q stored in the command issuing module 101 and splits the queue command Q into several sub-queue commands (Q)₁、Q₂....Q_m) (ii) a Logic control module 103, in turn, receives sub-queue commands (Q)₁、Q₂....Q_m) And split into several page commands (Q)₁₁、Q₁₂....Q_mn) And respectively transmits page commands (Q) according to the direction of data D transmission₁₁、Q₁₂....Q_mn) To the first port 104 or the second port 105; a buffer memory 106 configured to temporarily store data transmitted between the first port 104 and the second port 105.

In the present embodiment, the data transfer controller 100 is connected to the control bus 10 and the data bus 20 via the interface bus 110; the data transfer controller 100 is connected to the non-volatile memories 108a, 108b via an interface bus 110, respectively.

The interface bus 110 includes I²C. SMBUS, and preferably SMBUS. SMBUS (System management bus) is a two-wire serial bus. It abandons the traditional forms of the control bus and the Data bus of the central processor, so that the Data signal (Data), the clock signal (CLK) and the Address signal (Address) can be transmitted through the interface bus 110.

Specifically, the nonvolatile memories 107a and 107b are NAND flash memories; the volatile memory 108a, 108b is preferably a Dynamic Random Access Memory (DRAM).

The nonvolatile memories 107a and 107b may be a phase change memory (FCM), a ferroelectric memory (FeRAM), a Magnetic Random Access Memory (MRAM), an Ovonic Unified Memory (OUM), or a resistance ram (rram).

In this embodiment, the data bus 20 may also be connected to the peripheral I/O118 through the PCI-e interface 119, and is used to obtain data from the external to be written into the NAND flash memory or from the NAND flash memory to an external electronic device (not shown) having storage, communication, and data processing functions connected to the peripheral I/O118, for example: an external storage device (such as a video card, a network card, an SSD) based on the PCI-e interface 119.

In this embodiment, the advantages of fast operation speed and large bandwidth of a Dynamic Random Access Memory (DRAM), low manufacturing cost of a NAND flash memory, long service life, large storage capacity, and good shock resistance can be fully exerted. Therefore, the hybrid memory device 200 forms a plurality of parallel data transmission channels in the process of transmitting data from the volatile memories 108a and 108b to the nonvolatile memories 107a and 107b or transmitting data from the nonvolatile memories 107a and 107b to the volatile memories 108a and 108b, thereby improving the data transmission efficiency of the hybrid memory device 200.

In the present embodiment, the data transfer controller 100 is coupled to one of the nonvolatile memories 107a and 107b through a second port 105 (shown in fig. 1) provided therein. Of course, the second port 105 may also be coupled to a plurality of non-volatile memories 107.

In a preferred embodiment, the capacity of the nonvolatile memory 107 is greater than or equal to the capacity of the volatile memory 108; more preferably, the capacity of the nonvolatile memory 107 is equal to that of the volatile memory 108.

In the present embodiment, the control bus 10 of the hybrid storage device 200 does not need to be connected to a CPU (not shown); therefore, the manufacturing cost of the hybrid memory device 200 can be significantly reduced.

The command issuing module 101 in the data transmission controller 100 is coupled to the control bus 10 and receives the queue command Q, and then splits the queue command Q into block data (D) in data D in the push module 102₁、D₂....D_m) Corresponding sub-queue commands (Q)₁、Q₂....Q_m) And sends each sub-queue command (Q) in the logic control module 103₁、Q₂....Q_m) Split into blocks of data (D)₁、D₂....D_m) Page data (D) in (1)₁₁、D₁₂....D_mn) Corresponding several page commands (Q)₁₁、Q₁₂....Q_mn) And respectively transmits page commands (Q) according to the data transmission direction₁₁、Q₁₂....Q_mn) To the first port 104 or the second port 105, and performs data access to the volatile memory 108 or the nonvolatile memory 107 in units of pages.

Then, the page command (Q)₁₁、Q₁₂....Q_mn) And page data (D)₁₁、D₁₂....D_mn) After the first port 104 or the second port 105 are bound to each other, data transmission is performed between the volatile memory 108 and the nonvolatile memory 107 through the buffer memory 106.

Obviously, a greater number of data transmission controllers 100 and nonvolatile memories 107 can be connected in parallel between the control bus 10 and the data bus 20, so as to expand the hybrid storage apparatus 200 to some extent according to actual use requirements, thereby effectively improving the expandability of the hybrid storage apparatus 200.

The embodiments described above are merely exemplary in nature and are intended to be used in many general purpose or special purpose computing system environments or configurations, or communication system environments or devices. For example: personal computers, server computers, hand-held or portable devices, tablet-type devices, multi-processing systems, microprocessor-based systems, programmable consumer electronics, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, switches, routers, and the like.

The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A data transmission controller, comprising:

a first port coupled to the data bus;

a second port coupled to a non-volatile memory;

2. The data transmission controller according to claim 1, wherein interface buses are configured between the command issuing module and a control bus, between the first port and a data bus, and between the second port and the nonvolatile memory.

3. The data transfer controller of claim 2, wherein the interface bus comprises I²C、SM[BUS。

4. The data transfer controller of claim 1, wherein the buffer memory comprises at least one FIFO memory.

5. The data transfer controller of claim 1, further comprising a status management register, wherein the status management register obtains configuration information of the non-volatile memory from the control bus and sends the configuration information to the command issuing module.

6. The data transmission controller according to claim 1 or 5, wherein the configuration information is split into several sub-configuration information in a push module, and the sub-configuration information is bound to a plurality of sub-queue commands formed by splitting the queue commands by the push module and sent to the logic control module.

7. The data transmission controller according to claim 1 or 6, wherein the logic control module splits the sub-configuration information into a plurality of pages of configuration information, and sends the pages of configuration information to the first port or the second port according to the data transmission direction.

8. The data transfer controller according to claim 1 or 7, wherein the page configuration information and the page command are bound to each other in the first port or the second port, respectively, and perform data access to the volatile memory and the nonvolatile memory in units of pages.

9. A hybrid storage device, comprising:

the data transmission controller includes:

a first port coupled to the data bus;

a second port coupled to a non-volatile memory;

10. The hybrid storage device of claim 9, wherein the capacity of the non-volatile memory is greater than or equal to the capacity of the volatile memory.