CN107039059A - Memory package, includes its memory module and memory package operating method - Google Patents

Memory package, includes its memory module and memory package operating method Download PDF

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Publication number
CN107039059A
CN107039059A CN201710061219.6A CN201710061219A CN107039059A CN 107039059 A CN107039059 A CN 107039059A CN 201710061219 A CN201710061219 A CN 201710061219A CN 107039059 A CN107039059 A CN 107039059A
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China
Prior art keywords
memory
chip
data
memory chip
package
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Granted
Application number
CN201710061219.6A
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Chinese (zh)
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CN107039059B (en
Inventor
金灿景
姜郁成
金南升
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from US15/012,845 external-priority patent/US9847105B2/en
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Publication of CN107039059A publication Critical patent/CN107039059A/en
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Publication of CN107039059B publication Critical patent/CN107039059B/en
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

Disclose memory package.The memory package includes nonvolatile memory chip, its access speed volatile memory chip faster than the access speed of nonvolatile memory chip and logic chip, and the logic chip is used to perform on the refresh operation of volatile memory chip in response to the refresh command from external device (ED) and moves to volatile memory chip when performing refresh operations by least a portion of the data stored in nonvolatile memory chip.

Description

Memory package, includes its memory module and memory package operating method
Technical field
This disclosure relates to semiconductor memory, and more specifically to memory package, with the memory package Memory module and its operating method.
Background technology
Semiconductor memory can use such as silicon (Si), germanium (Ge), GaAs (GaAs), indium phosphide (InP) etc. The storage arrangement that semiconductor is realized.Semiconductor memory system is typically divided into volatile memory devices and non-volatile Property storage arrangement.
Volatile memory devices refer to the storage arrangement of the loss of data wherein stored when electrical power is off.Separately On the one hand, non-volatile memory device refers to keeping the storage arrangement of stored data when electrical power is off.Because There is high access speed as a kind of dynamic random access memory of volatile memory devices (DRAM), so DRAM is extensive Ground is used as working storage, buffer memory, main storage of computing system etc..With the development of computing technique, DRAM conducts Increase the need for the working storage of computing system.Because DRAM memory cell generally includes capacitor and transistor, It is difficult to cell size decreasing below constant level.Accordingly, it is difficult to realize the Large Copacity DRAM in finite region.
To solve the problem, the non-volatile dual-in-line based on nonvolatile memory and DRAM operations has been developed Formula memory module (NVDIMM).NVDIMM can provide high power capacity by combining high power capacity nonvolatile memory and DRAM Working storage.But, because the operating characteristic of nonvolatile memory, operating method etc. are different from those of DRAM, Various methods may be needed to be used to control and manage them.
The content of the invention
The embodiment of concept of the present invention provides memory package, the memory module with memory package and its operation Method, it performs Data Migration and with increased memory capacity without performance reduction during refresh operation.
According to the one side of concept of the present invention, memory package can include nonvolatile memory chip, access speed The degree volatile memory chip faster than the access speed of nonvolatile memory chip and logic chip, the logic chip are used for The refresh operation on volatile memory chip is performed in response to the refresh command from external device (ED), and refreshes behaviour when performing At least a portion of the data stored in nonvolatile memory chip is moved into volatile memory chip when making.
Nonvolatile memory chip and volatile memory chip can be stacked on the direction perpendicular to logic chip, And nonvolatile memory chip, volatile memory chip and logic chip can be by being connected to each other through silicon hole.
According to the another aspect of concept of the present invention, memory module can include including volatile memory chip and Fei Yi The memory package of the property lost memory chip, and for the control memory encapsulation under the control of external device (ED) and periodically Ground sends refresh command to random access memory (RAM) control device of memory package.Memory package can be in response to Refresh command performs refresh operation for volatile memory chip, it is possible to by nonvolatile memory during refresh operation At least a portion of the data stored in chip moves to volatile memory chip.
Memory package can include multiple data signal lines.Memory package can be by the part of data signal line Exchange data with external device (ED), and will can be stored by the remainder of data signal line in nonvolatile memory chip At least a portion of data moves to volatile memory chip.
According to the another aspect of concept of the present invention, memory package includes volatile memory chip and non-volatile memories Device chip.The operating method of memory package includes：Refresh command is received from external device (ED)；With in response to refresh command for Volatile memory devices move at least a portion of the data stored in nonvolatile memory chip when performing refresh operation Move on to volatile memory chip.
Brief description of the drawings
Above and other objects and features will become obvious from following explanation with reference to the following drawings, in the accompanying drawings, unless Otherwise indicated, identical reference refers to identical part throughout each figure, and wherein：
Fig. 1 is block diagram of the diagram according to the custom system of some embodiments of concept of the present invention；
Fig. 2 is block diagram of the diagram according to the example memory module such as shown in Figure 1 of some embodiments；
Fig. 3 is the figure that diagram is encapsulated according to the example memory such as shown in Figure 2 of some embodiments；
Fig. 4 is the perspective view that diagram is encapsulated according to the example memory such as shown in Figure 3 of some embodiments；
Fig. 5 is that diagram is encapsulated according to the example memory such as shown in Figure 2 of some embodiments of concept of the present invention Block diagram；
Fig. 6 is the perspective view that diagram is encapsulated according to the example memory such as shown in Figure 5 of some embodiments；
Fig. 7 is flow chart of the diagram according to the exemplary operation of the memory package as shown in Figure 2 of some embodiments；
Fig. 8 is the block diagram for describing the exemplary operation as shown in Figure 7 according to some embodiments；
Fig. 9 is that diagram is encapsulated according to the example memory such as shown in Figure 2 of some embodiments of concept of the present invention Block diagram；
Figure 10 is the block diagram that diagram is encapsulated according to the example memory of some embodiments of concept of the present invention；
Figure 11 is the exemplary operation for describing the memory package according to the ratios of some embodiments as shown in fig. 10 Block diagram；
Figure 12 is the block diagram that diagram is encapsulated according to the example memory of some embodiments of concept of the present invention；
Figure 13 is the exemplary operation for describing the Data Management Unit DMU as shown in figure 12 according to some embodiments Flow chart；
Figure 14 is block diagram of the diagram according to the exemplary user system of some embodiments of concept of the present invention；
Figure 15 is block diagram of the diagram according to the exemplary user system of some embodiments of concept of the present invention；
Figure 16 is exemplarily to illustrate the exemplary volatile memory core such as shown in Figure 3 according to some embodiments The block diagram of piece；
Figure 17 is the example for exemplarily illustrating the nonvolatile memory chip as shown in Figure 3 according to some embodiments The block diagram of the first nonvolatile memory chip of property；
Figure 18 is block diagram of the diagram according to the example memory module of some embodiments of concept of the present invention；
Figure 19 is block diagram of the diagram according to the example memory module of some embodiments of concept of the present invention；
Figure 20 is the server of exemplarily memory module of the diagram including some embodiments according to concept of the present invention The figure of system；With
Figure 21 is that diagram includes the memory module or memory package of some embodiments according to concept of the present invention The block diagram of electronic system.
Embodiment
In detailed description below, some examples of the present invention have shown and described simply by the mode of explanation Property embodiment.
As used herein, semiconductor device for example also refers to such as semiconductor chip (for example, being formed on nude film Memory chip and/or logic chip), the stacking of semiconductor chip including stack on the package substrate it is one or more The semiconductor packages of semiconductor chip or the device for encapsulating stacked laminator including multiple encapsulation.Encapsulation, which can refer to, to be had The single package substrate of the one or more chips stacked thereon, or the envelope with multiple single packages stacked on each other Fill stacked laminator.These devices can use baii grid array, wire bonding, Through-substrate through hole or other electrical connection elements Part is formed, and can form the storage arrangement of such as volatibility or Nonvolatile memory devices.
In addition, as used herein, term " storage arrangement " refers generally to the heap of memory chip or memory chip It is folded, and/or memory package.Memory package refers to including the semiconductor packages of memory chip.For example, memory package (this chip can also be referred to as at least one semiconductor chip that can be including package substrate and including memory cell array Memory chip).In addition to the logic chip of such as Memory Controller, memory package can also include memory chip. One or more chips that memory package will typically comprise the sealer protection circuit of package substrate and be stacked thereon. Under certain situation, memory package can have at least two chips being flatly separated from each other for sharing identical sealer.
As used herein, memory module includes multiple memory packages, memory chip, or divides each other horizontally The stacking for the memory chip opened and formed on the substrate of such as printed circuit board (PCB) etc.In the specified level of memory module The stacking of each memory package of position, memory chip or memory chip typically comprises the sealer of its own.
As used herein, electronic installation can generally refer to semiconductor device, storage arrangement or memory module, and The product comprising these devices, such as the hard disk drive of storage card including add-on assemble, or mobile electricity can be comprised additionally in Words, laptop computer, tablet personal computer, desktop computer, camera or other consumer electronics devices, etc..
Chip refers to the semiconductor devices formed by the chip of the integrated circuit such as formed on nude film.As made herein , chip is not including package substrate or PCB.
First memory encapsulation can be included according to the memory module of some embodiments of concept of the present invention.First storage Device encapsulation can include volatile memory chip and nonvolatile memory chip.To keep the volatibility in memory package The data of memory chip, memory package can periodically carry out refresh operation.Here, memory package can perform from Data Migration of the nonvolatile memory chip to volatile memory chip.Therefore, the embodiment of concept of the present invention can be carried For having improved properties memory package and memory module with increased capacity.
The disclosure will be described more fully hereinafter with reference to the accompanying drawings now, various embodiments are shown in the drawings.But Be, the present invention can specific manifestation and should not be viewed as limited to is proposed herein in many different forms example implement Example.These example embodiments are only " examples ", and do not require that many realizations and modification of the details provided herein are possible. It should be again emphasized that the disclosure provides the details of alternative exemplary, but listing for this replacement is not limit.In addition, various examples Between any uniformity of details be not construed as requiring this details --- for each characteristic series described here It is unpractiaca to go out each possible modification.The language of claim should be referred to determine the requirement of the present invention.
In figure, the size and relative size in layer and region can be exaggerated in order to clear.Identical numeral is referred to Identical element in full text.Although different figures shows the modification of exemplary embodiment, these figures are unnecessarily intended to Repel each other.But, as will be seen from context described further below, when generally consider accompanying drawing and they say The some features for showing and describing when bright, in different figures can be combined to generate various implementations with other features from other figures Example.
The term being used herein is only used for describing the purpose of specific embodiment and being not intended to the limitation present invention.As herein Use, singulative " one ", " one " and "the" are intended to also include plural form, make an exception unless the context clearly dictates. As used herein, the project listed of term "and/or" including one or more associations any and all combination and can be with It is abbreviated as "/".
It will be understood that, although term first, second, third, etc. can be used to describe various elements, component, area herein Domain, layer and/or part, but these elements, component, region, layer and/or part should not be limited by these terms.Unless on Exception is indicated below, these terms, for example as naming rule, are only used for distinguishing an element, component, region, layer or portion Divide and another element, component, region, layer or part.Therefore, first yuan discussed below in a part of specification Part, component, region, layer or part can specification another part or be referred to as in the claims the second element, Component, region, layer or part, without departing from the teachings of the present invention.In addition, in some cases, even if not having in the description Have the Terminologies such as use " first ", " second ", its still can be referred to as in the claims " first " or " second " with The element for the different claims that are distinguished from each other.
It will further be understood that term " comprising " and/or "comprising" or " containing " and/or " having " when making in this specification Used time specifies the presence of described feature, region, integer, step, operation, element or its component, and is not excluded for one or more Further feature, region, integer, step, operation, element, component and/or its presence organized or additional.
It will be understood that when element is referred to as " connecting " or during " coupled " to another element or " on another element ", it can To be directly connected to either be coupled to another element or on another element or there may be intervenient element. On the contrary, when element is referred to as " being directly connected to " or " direct-coupling " to another element, in the absence of intervenient element. Should be explained in a similar manner for describing other words of the relation between element (for example, " ... between " relative to " directly ... between ", " adjacent " is relative to " direct neighbor ", etc.).But, term " contact " as used herein refers to directly Contact (that is, is touched), unless context indicates exception.
By by way of idealized schematic diagram reference planes figure, perspective view and/or cross-sectional view describe described here Embodiment.It therefore, it can depend on the figure of manufacturing technology and/or tolerance modified example.Therefore, the disclosed embodiments are not limited Those shown in figure, but include the modification of the configuration based on manufacture handling process formation.Therefore, illustrating Region can have schematic nature, and the shape in the region shown in figure can be with the specific shape in the region of example elements Shape, aspect not limited to this of the invention.
Spatially relative term, such as " under ", " following ", " bottom ", " on ", " top " etc. can use herein In being easy to description to describe an element or feature as shown in figure and other one or more elements or feature Relation.It will be understood that spatially relative term is intended to include the dress in use or operation in addition to orientation shown in the figure The different azimuth put.If for example, the device upset in figure, be described as other elements or feature " under " or The element of " following " will be orientated in other elements or feature " on ".Therefore, term " under " can include above and below Two orientation.Device can otherwise be oriented and (is rotated by 90 ° or in other orientation), and the space being used herein The relative descriptor in ground is correspondingly explained.
The term of as used herein such as " identical ", " being equal to ", " plane " or " coplanar " when be related to orientation, Layout, position, shape, size, amount or other when measuring, it is not necessary to refer to accurately identical orientation, layout, position, shape, big Small, amount or other measure, and be intended to and be included in the acceptable change being for example likely to occur due to manufacturing process Almost identical orientation, layout, position, shape, size, amount other are measured.Term " substantially " can be used for herein Reflect the implication.
As used herein, configuration is described as the item " electrically connected " so that electric signal can be delivered to other from an item .Therefore, passive electrical insulation assembly is physically connected to (for example, prepreg (prepreg) layer of printed circuit board (PCB), connection The adhesive of the electric insulation of two devices, underfill (underfill) or moulding layer of electric insulation etc.) passive conductive group Part (for example, electric wire, pad, internal wire etc.) is not electrically connected to the component.In addition, the item of " directly electrical connection " passes through each other One or more passive element electrical connections, for example, cable, pad, internal wire, through hole etc..Thus, the component directly electrically connected Do not include by active component, such as transistor or the component of diode electrical connection.The item of electrical connection can be described as directly Connect and physically connect to indicate that they are physically adjacent directly with one another.
Although the language of such as " one embodiment " or " some embodiments " can be used to refer to figure described here, But these figures and their corresponding explanation be not intended to other figures or illustrate it is mutually exclusive, unless context so refers to Show.Therefore, some aspects from some figures may be identical with some of other figures feature, and/or some figures can be special The different of fixed exemplary embodiment represent or different piece.
Unless defined otherwise, all terms (including technology and scientific terminology) being used herein have and this public affairs Open the identical implication that the those skilled in the art in the field belonged to are generally understood that.It will further be understood that such as in usually used word The term limited in allusion quotation should be construed to consistent with their implications in the context of prior art and/or the application Implication, and by meaning interpretation not to idealize or excessively formalize, unless clearly so limited herein.
Fig. 1 is block diagram of the diagram according to the custom system of the embodiment of concept of the present invention.With reference to Fig. 1, custom system 10 can With including processor 101, memory module 100, chipset 102, graphics processing unit (GPU) 103, input/output device 104 With storage device 105.In the exemplary embodiment, custom system 10 can be electronic installation and can include computer, portable Computer, super mobile personal computer (UMPC), work station, server computer, net book, personal digital assistant (PDA), net Network flat board, radio telephone, mobile phone, smart phone, digital camera, digital audio recorder, digital audio-frequency player, numeral Scanner-recorder, digital image player, digital video recorder, video frequency player, it can send in the wireless context Or receive information device or constitute one of various electronic installations of home network.
Processor 101 can control the overall operation of custom system 10.Processor 101 can be performed in custom system 10 The various operations performed.
Memory module 100 may be used as buffer storage, main storage, working storage of custom system 10 etc..Deposit Memory modules 100 can be directly connected to processor 101.For example, memory module 100 can have dual-in-line memories The form of module (DIMM), and memory module 100 may be mounted in DIMM sockets, the DIMM sockets are directly connected to processing Device 101 with processor 101 so as to communicate.In the sense that, memory module 100 may be electrically connected to processor 101 and not have There is any other IC apparatus, such as other chips, encapsulation or module therebetween.
Chipset 102 may be electrically connected to processor 101 and can control custom system under the control of processor 101 10 hardware.For example, chipset 102 can be connected to GPU 103, input/output device 104 and storage device by main bus 105, and the bridge operation on main bus can be performed.
GPU 103 can perform a series of arithmetical operations of the view data for exporting custom system 10.It is real in example Apply in example, GPU 103 can be installed in the processor 101 in the form of on-chip system (SoC).
Input/output device 104 can include arriving custom system 10 or output data for input data or instruction To the various devices of external device (ED).For example, input/output device 104 can include user input apparatus, such as keyboard, small key Disk, button, touch pad, touch-screen, touch pads, touch ball, camera, microphone, gyro sensor, vibrating sensor, piezoelectricity Element, temperature sensor, biometric sensor etc., and input/output device 104 can include user's output device, such as Liquid crystal display (LCD), Organic Light Emitting Diode (OLED) display device, Activematric OLED (AMOLED) display device, hair Optical diode (LED), loudspeaker, motor etc..
Storage device 105 may be used as the large-capacity storage media of custom system 10.Storage device 105 can be included such as The large-capacity storage media of hard disk drive (HDD), solid-state drive (SSD), storage card, memory stick etc..
In the exemplary embodiment, memory module 100 can write or export number under the control of processor 101 According to.In the exemplary embodiment, memory module 100 can include various types of memories.For example, memory module 100 can To be mixing memory and can be realized based on various storage arrangements：Volatile memory devices, such as DRAM, static random Access memory (SRAM), synchronous dram (SDRAM), or non-volatile memory device, such as read-only storage (ROM), Programming ROM (PROM), electrically programmable ROM (EPROM), electric erazable programmable ROM (EEPROM), flash memory devices, phase Become RAM (PRAM), magnetic RAM (MRAM), resistance RAM (RRAM), ferroelectric RAM (FRAM) etc..
Fig. 2 is the block diagram for illustrating example memory module such as shown in Figure 1.With reference to Fig. 1 and Fig. 2, memory mould Block 100 can include RAM control devices (RCD) 110, memory package 120 and serially there is detection chip (SPD) 130.
RCD 110 can the control memory encapsulation 120 under the control of processor 101.For example, RCD 110 can be from Processor 101 receives address AD DR, order CMD and clock CK.In response to received signal, RCD 110 can control storage Device encapsulation 120, to cause the data by data-signal DQ and data strobe signal DQS receptions to be written into memory package 120, Or to encapsulate the data stored in 120 by data-signal DQ and data strobe signal DQS output storages.It is real in example Apply in example, address AD DR, order CMD and clock CK from processor 101 can be sent to memory package 120 by RCD 110. RCD 110 for example can be a part for the chip of such as logic chip.RCD 110 can be referred to as RAM control electricity herein Road, or more generally control circuit.
Memory package 120 can write under RCD 110 control passes through data-signal DQ and data strobe signal The data that DQS is received.Alternatively, memory package 120 can pass through data-signal DQ and data under RCD 110 control The data of gating signal DQS output write-ins.In the exemplary embodiment, memory package 120 can include various types of storages Device device (for example, memory chip).For example, memory package 120 can include the non-volatile memories based on nand flash memory Device device and the volatile memory devices based on DRAM.In the exemplary embodiment, memory package 120 can include volatibility Storage arrangement, such as DRAM, SRAM, SDRAM, or non-volatile memory device, such as ROM, PROM, EPROM, EEPROM, flash memory devices, PRAM, MRAM, RRAM or FRAM.
In the exemplary embodiment, memory module 100 can include multiple memory packages.It is each in memory package It is individual to be operated under RCD 110 control.In the exemplary embodiment, each in memory package can be based on double Data rate (DDR) interface communicates with RCD 110.
In certain embodiments, SPD 130 can be programmable read only memory (for example, EEPROM).SPD 130 can be with Initial information or device information DI including memory module 100.In the exemplary embodiment, SPD 130 can include memory The initial information or accumulator system information MSI of module 100, such as the configuration of modular form, module, memory capacity, module class Type, performing environment etc..When the custom system 10 including memory module 100 starts, processor 101 can be read from SPD 130 Access to memory system information MSI, and accumulator system information MSI recognition memories module 100 can be based on.Processor 101 can With based on the accumulator system information MSI control memories module 100 from SPD 130.For example, processor 101 can be based on Accumulator system information MSI from SPD, identification is included in the type of the memory package 120 in memory module 100.Cause This, some of some accumulator system information MSI can be module information, or more specifically, some accumulator systems are believed It can be device information to cease some of MSI.
In the exemplary embodiment, SPD 130 can be communicated by universal serial bus with processor 101.Processor 101 can lead to Cross universal serial bus and exchange signal with SPD 130.SPD 130 can be communicated by universal serial bus with RCD 110.Universal serial bus can be with Including at least one in 2 wire serial bus, such as mutual integrated circuit (I2C) bus, System Management Bus (SMBus), power Manage bus (PMBus), IPMI (IPMI) bus, management assembly transport protocol (MCTP) bus etc..
In the exemplary embodiment, memory package 120 can include non-volatile memory device and volatile storage The mixing memory encapsulation of device device (for example, nonvolatile memory chip and volatile memory chip).Deposited including mixing The memory module 100 of reservoir encapsulation can be non-volatile DIMM (NVDIMM).The operation speed of non-volatile memory device Degree can be slower than the service speed of volatile memory devices.Therefore, memory package 120 can fill nonvolatile memory The Data Migration of middle storage is put to volatile memory devices.In the exemplary embodiment, memory package 120 can be in response to brush Newer command performs refresh operation and migration operation together.
According to some embodiments of concept of the present invention, in memory module 100, including non-volatile memory device and The memory package 120 of volatile memory devices can perform migration during refresh operation, thus increase memory span Without losing performance.As a result, the memory module of cost and improved performance with reduction can be provided.
Fig. 3 is the figure for illustrating example memory encapsulation such as shown in Figure 2.Fig. 4 is diagram storage as shown in Figure 3 The perspective view of device encapsulation.With reference to Fig. 3 and Fig. 4, memory package 120 can include logic chip 121, volatile memory chip 122 and the first to the 3rd nonvolatile memory chip 123a to 123c.In the exemplary embodiment, memory package 120 can be with Including additional volatile memory chip or nonvolatile memory chip.Memory package 120 can be mixing storage Device is encapsulated.
Under RCD 110 control, logic chip 121 can be in volatile memory chip 122 or first to The number that write-in is received by data-signal DQ and data strobe signal DQS in three nonvolatile memory chip 123a to 123c According to.Under RCD 110 control, logic chip 121 can be by data-signal DQ and data strobe signal DQS outputs easy The data write in the property lost memory chip the 122 or first to the 3rd nonvolatile memory chip 123a to 123c.
Logic chip 121 can include migration management unit MMU.Migration management unit MMU can be by first to the 3rd The data write in nonvolatile memory chip 123a to 123c move, replicate or move to volatile memory chip 122.Logic chip 121 can include the logic circuit for being used to perform this task.
In the exemplary embodiment, logic chip 121 may further include for buffering the letter received from external device (ED) Number (for example, order CMD, address AD DR, data-signal DQ or data strobe signal DQS) buffer circuits, for controlling First to the 3rd nonvolatile memory chip 123a to 123c non-volatile memory control circuitry, or for managing easily The address administration electricity of the property lost memory chip the 122 and first to the 3rd nonvolatile memory chip 123a to 123c address Road.
Under the control of logic chip 121, volatile memory chip 122 can write data or can export and write The data entered.In the exemplary embodiment, volatile memory chip 122 can be SRAM or DRAM.In order to simple, it is assumed that easily The property lost memory chip 122 is DRAM.
It is every in the first to the 3rd nonvolatile memory chip 123a to 123c under the control of logic chip 121 One can write data or can export the data of write-in.In the exemplary embodiment, the first to the 3rd non-volatile memories In device chip 123a to 123c each can include ROM, PROM, EPROM, EEPROM, flash memory devices, PRAM, At least one in MRAM, RRAM or FRAM.In order to simple, it is assumed that the first to the 3rd nonvolatile memory chip 123a is arrived Each in 123c includes flash memory devices.
In some example embodiments, the memory capacity of volatile memory chip 122 can be non-less than first to the 3rd Volatile memory chip 123a to 123c memory capacity.The access speed of volatile memory chip 122 can be than first To the 3rd nonvolatile memory chip 123a to 123c access speed faster.
It is included in logic chip 121 in memory package 120, volatile memory chip 122 and first to the 3rd non- Each in volatile memory chip 123a to 123c can be single semiconductor chip or single nude film.Including Logic chip 121, the nonvolatile memory of volatile memory chip the 122 and first to the 3rd in memory package 120 Chip 123a to 123c can be stacked on the third direction perpendicular to the plane defined along a first direction with second direction.By This, as shown in figure 4, logic chip 121 can be placed in the plane defined along the first and second directions, and volatibility is deposited Nonvolatile memory chip 123a to the 123c of memory chip the 122 and first to the 3rd can be perpendicular to logic chip 121 Stacked on third direction.The logic chip 121 of stacking, the non-volatile memories of volatile memory chip the 122 and first to the 3rd Device chip 123a to 123c can be connected to each other by multiple through substrate through vias TSV (for example, through silicon hole).It is real in example Apply in example, logic chip 121 through substrate through vias TSV can control volatile memory chip 122 and first to the by this Each in three nonvolatile memory chip 123a to 123c.
In the exemplary embodiment, migration management unit MMU can perform migration operation by migrating channels MC.The migration is led to Road MC can be independently of data-signal DQ and data strobe signal DQS passage.For example, migration management unit MMU can pass through Migration operation is performed through substrate through vias TSV.It is, may be used as migrating channels MC through substrate through vias TSV.Migration management Unit MMU can be by performing transmission and reception on the data to be migrated through substrate through vias TSV.In example embodiment In, migrating channels MC can be realized with serial link.
As described above, because the first to the 3rd nonvolatile memory chip 123a to 123c memory capacity is more than volatile The memory capacity of property memory chip 122, the total memory capacity of memory package 120 can be by non-volatile first to the 3rd Data storage in property memory chip 123a to 123c and increase.But, because the first to the 3rd nonvolatile memory chip The access speed of each in 123a to 123c is slower than the access speed of volatile memory chip 122, so overall performance can Can reduction.Therefore, can under given conditions will be non-volatile first to the 3rd according to the memory package 120 of example embodiment A part for the data stored in property memory chip 123a to 123c moves to volatile memory chip 122.It is real in example Apply in example, specified conditions can include following：There are the data to be migrated, perform the situation, etc. of refresh operation.Will The data accessed by RCD 110 or processor 101 can be stored in volatile memory chip 122 by migration operation. Therefore, RCD 110 or processor 101 can access volatile memory chip 122, thereby making it possible to improving performance and increasing Plus memory span.
Fig. 5 is block diagram of the diagram according to the memory package such as shown in Figure 2 of another embodiment of concept of the present invention. Fig. 6 is the perspective view of diagram memory package as shown in Figure 5.With reference to Fig. 5 and Fig. 6, memory package 120 ' can include patrolling Collect chip 121 ', volatile memory chip 122 ' and the first to the 3rd nonvolatile memory chip 123a ' and arrive 123c '.Ginseng Examine Fig. 3 and Fig. 4 and describe logic chip, volatile memory chip and the first to the 3rd nonvolatile memory chip, and because This, which can omit memory package 120 ', can include logic chip 121 ', volatile memory chip 122 ' and first to the 3rd Nonvolatile memory chip 123a ' arrives 123c ' detailed description.
Logic chip 121 ' and volatile memory chip 122 ' can be perpendicular to along a first direction and second direction (referring to Fig. 6) is stacked on the third direction of the plane of definition, and can be connected to each other by first group through substrate through vias TSV1. In certain embodiments, first direction and second direction can be the directions for the memory cell for arranging memory chip.First Can be perpendicular to the plane defined along line direction and column direction to the 3rd nonvolatile memory chip 123a ' to 123c ' Direction on stack, and can be connected to each other by second group through substrate through vias.
Thus, logic chip 121 ', volatile memory chip 122 ' and first to the 3rd nonvolatile memory chip 123a ' to 123c ' can be stacked on region different from each other, to cause them to be flatly separated from each other.But, they can be with It is a part for same encapsulation, because they share package substrates and can covered by same insulated enclosure thing.Logic chip 121 ' and the first to the 3rd nonvolatile memory chip 123a ' to 123c ' can each other be connected by single migrating channels MC ' Connect.In the exemplary embodiment, migrating channels MC ' can be single signal wire (wire e.g., including in package substrate).
Embodiment with reference to Fig. 3-Fig. 6 descriptions on the structure of memory package, but the scope and essence of concept of the present invention Refreshing not limited to this.Logic chip, volatile memory chip and the nonvolatile memory chip that memory package includes can To be stacked or arranged by other method (for example, stacking, table top (mesa) structure etc. in a zigzag).
Fig. 7 is the flow chart for the exemplary operation for illustrating memory package such as shown in Figure 2.With reference to figs. 2 and 7, In step S110, memory package 120 can receive refresh command REF from RCD 110.For example, RCD 110 can be based on predetermined The communication protocol control memory encapsulation 120 of justice.In the exemplary embodiment, predefined communication protocol can be based on DRAM Communication protocol.In the exemplary embodiment, DRAM can periodically carry out refresh operation to maintain stored data.RCD 110 can periodically send refresh command REF to memory package 120, to cause memory package 120 is performed to refresh behaviour Make.
In step S120, when the refresh command REF in response to being received performs refreshing behaviour in volatile memory chip When making, memory package 120 can also perform migration operation.For example, as described above, memory package 120 can include it is volatile Property memory chip the 122 and first to the 3rd nonvolatile memory chip 123a to 123c.Memory package 120 can be responded Refresh operation is performed in the refresh command REF received.Refresh operation can represent to be used to read in volatile memory chip The data that the data and rewriting stored in 122 are read, to refresh depositing in the volatile memory chip 122 of data storage The operation of storage unit.
When performing refresh operations, memory package 120 can also perform the first to the 3rd nonvolatile memory chip The transition process of the data to be migrated in the data stored in 123a to 123c.In the exemplary embodiment, the data to be migrated Can be among the data stored in the first to the 3rd nonvolatile memory chip 123a to 123c, with will be by processor The data of the high likelihood of 101 accesses, the data of the frequency of access with more than or equal to constant level are used as the number of dsc data According to, or with certain types of data.In the exemplary embodiment, the data to be migrated can by logic chip 121 migration Administrative unit MMU is determined.
Fig. 8 is the block diagram for describing operation as shown in Figure 7.In order to simple, it is convenient to omit description behaviour as shown in Figure 7 The unnecessary component made.Furthermore, it is assumed that the first page data PD1 is the data to be migrated determined by migration management unit MMU.
With reference to Fig. 2, Fig. 7 and Fig. 8, memory package 120 can include logic chip 121, volatile memory chip 122 With nonvolatile memory chip 123a.Logic chip 121 can be from external device (ED) (for example, via memory module 100 RCD 110) receive refresh command REF (1.).In response to the refresh command REF received, logic chip 121 can control volatile Property memory chip 122, with cause volatile memory chip 122 perform refresh operation.Volatile memory chip 122 can be with Refresh operation is performed under the control of logic chip 121.
When performing refresh operations, logic chip 121 can also read first page from nonvolatile memory chip 123a Data PD1 (2.).In the exemplary embodiment, the first page data PD1 can be the migration management unit MMU by logic chip 121 The data for the data for selecting to be migrated.For example, migration management unit MMU can include on nonvolatile memory chip 123a which data are for example, because they are the data continually accessed, be determined in advance as volatile storage to be moved to The information of device chip 122.
When performing refresh operations, in addition to the refreshing of existing data in control volatile memory chip 122, logic Chip 121 can also control volatile memory chip 122 to cause read from nonvolatile memory chip 123a first Page data PD1 (for example, the data continually accessed) is written into volatile memory chip 122 (3.).For example, volatile storage Device chip 122 can perform refresh operation under the control of logic chip 121.Refresh operation can include reading particular row Data and by the rewriting data of reading to same particular row.While rewriting is performed, logic chip 121 can be controlled easily in addition The property lost memory chip 122 is to cause first page data PD1 to be written into volatile memory chip 122.
In the exemplary embodiment, particular row can represent row corresponding with refresh address.In addition, volatile memory chip 122 migration address can be selected by logic chip 121 or volatile memory chip 122.In order in volatile memory The first page data PD1 is write in chip 122, logic chip 121 can for example elect migration address as volatile memory chip The wherein not address of the row of data storage in the 122 multiple trades included.
As described above, memory package 120 can be performed during on the refresh operation of volatile memory chip 122 Migration operation.As a result, because reducing due to expense caused by migration operation, it is possible to provide depositing with increased capacity Memory modules 100 are without reducing performance.It is, therefore, possible to provide the memory module of cost and improved performance with reduction and Memory package.
Fig. 9 is block diagram of the diagram according to the memory package as shown in Figure 2 of another embodiment of concept of the present invention.With reference to Fig. 2 and Fig. 9, memory package 120 " can include logic chip 121 ", volatile memory chip 122 " and first to the 3rd Nonvolatile memory chip 123a " arrives 123c ".Logic chip, volatile memory chip and first are described with reference to Fig. 3 to arrive 3rd nonvolatile memory chip, and therefore can omit logic chip 121 ", volatile memory chip 122 " and first 123c " detailed description is arrived to the 3rd nonvolatile memory chip 123a ".
Compared with the memory package 120 and 120 ' illustrated in Fig. 3 to Fig. 6, memory package 120 " as shown in Figure 9 can To use data signal line as migrating channels.For example, logic chip 121 " can include the first data signal line DQL1 and the Two data signal line DQL2.In the exemplary embodiment, each in the first and second data signal line DQL1 and DQL2 can be with Including multiple signal wires (for example, multiple wires).
Logic chip 121 " can be used to be not used in and outside dress among the first and second data signal line DQL1 and DQL2 Put (for example, processor 101) and exchange the signal wire of data as migrating channels.For example, logic chip 121 " can pass through first Data signal line DQL1 receives data-signal DQ and data strobe signal DQS from processor 101.Logic chip 121 " can pass through Second data signal line DQL2 exchanges the data that 123c " is arrived from the first to the 3rd nonvolatile memory chip 123a ".Cause This, logic chip 121 " can use the second data signal line DQL2 as migrating channels.
Figure 10 is block diagram of the diagram according to the memory package of another embodiment of concept of the present invention., can be with order to simple Omit the explanation overlapping with said modules.With reference to Figure 10, memory package 220 can include logic chip 221, volatile storage Nonvolatile memory chip 223a to the 223c of device chip the 222 and first to the 3rd.As described above, the group of memory package 220 Part can in the direction perpendicular to the planes stack and can be by being connected to each other through silicon hole TSV.In the exemplary embodiment, Migrating channels MC should be may be used as through silicon hole TSV.Logic chip, volatile memory chip are described with reference to figs. 2 to Fig. 9 With the first to the 3rd nonvolatile memory chip, and logic chip 221, volatile memory chip 222 therefore can be omitted With the first to the 3rd nonvolatile memory chip 223a to 223c detailed description.
Logic chip 221 can include migration management unit MMU, nonvolatile memory administrative unit NMU and address is managed Manage unit AMU.Migration management unit MMU is as described above, and therefore can be so that description is omitted.
Nonvolatile memory administrative unit NMU is configurable to control the first to the 3rd nonvolatile memory chip 223a to 223c.For example, nonvolatile memory administrative unit NMU can be generated for controlling first to the 3rd non-volatile to deposit Memory chip 223a to 223c order, address, control signal etc..Nonvolatile memory administrative unit NMU can be for It is flat that one to the 3rd nonvolatile memory chip 223a to 223c performs operand address translation, garbage collection operations and loss Weighing apparatus (wear leveling) operation.In the exemplary embodiment, nonvolatile memory administrative unit NMU can be by as moving Mobile Communication road MC's runs through silicon hole TSV to control the first to the 3rd nonvolatile memory chip 223a to 223c.Alternatively, it is non- Volatile memory administrative unit NMU can pass through single signal line traffic control first to the 3rd nonvolatile memory chip 223a to 223c.
Address administration unit AMU can manage the nonvolatile memory of volatile memory chip the 222 and first to the 3rd Chip 223a to 223c address.For example, external device (ED) (for example, processor 101 as shown in Figure 1) can be by memory package Nonvolatile memory chip 223a to the 223c of volatile memory chip the 222 and first to the 3rd in 220 is identified as one Storage region.It is, memory package 220 can be identified as a working storage by external device (ED).Here, external device (ED) CMD and address AD DR can will be ordered to provide the data for reading and being write in memory package 220 to RCD 210.Memory is sealed Data corresponding with address AD DR can be exported under RCD 210 control by filling 220.
In the exemplary embodiment, external device (ED) can with the migration operation of nonrecognition memory package 220 but can will easily The property lost memory chip the 222 and first to the 3rd nonvolatile memory chip 223a to 223c is identified as an address area. Therefore, when corresponding nonvolatile memory chip 223a to the 223c of data from first to the 3rd of address AD DR with being received is moved When moving on to volatile memory chip 222, it is not possible to perform normal operating, or operating characteristics may be reduced.
In the exemplary embodiment, address AD DR corresponding with the data migrated is received, address administration unit AMU can be managed Access address is wanted to volatile memory chip 222.Therefore, when the data of access migration, data can be deposited from volatibility Memory chip 222 is exported, and therefore can improve operating characteristics.
In the exemplary embodiment, although not shown in Figure 10, but volatile memory chip 222 can be from RCD 210 Receive order CMD, address AD DR and clock CK and can be operated in response to received signal.
Figure 11 is the block diagram for describing the operation of memory package as shown in Figure 10.In the exemplary embodiment, it will join Examine the operation that Figure 11 intensively describes address administration unit AMU.In order to simple, it is convenient to omit description address administration unit AMU's The unnecessary component of operation.Furthermore, it is possible to omit on the explanation with said modules identical component.
With reference to Figure 10 and Figure 11, memory package 220 can include logic chip 221, the and of volatile memory chip 222 First nonvolatile memory chip 223a.
Memory package 220 can receive the first address AD DR1 and can access DR1 pairs of the first address AD with being received The data answered.For example, data corresponding with the first address AD DR1 can be the first page data PD1.First page data PD1 can be with It is stored in the first nonvolatile memory chip 223a.Here, address administration unit AMU can carry the first address AD DR1 The first nonvolatile memory chip 223a is supplied to, to read the first number of pages from the first nonvolatile memory chip 223a According to PD1.
Hereafter, the first page data PD1 stored in the first nonvolatile memory chip 223a can move to volatibility Memory chip 222.For example, as described above, memory package 220 can be selected in the first nonvolatile memory chip 223a First page data PD1 of middle storage is used as the data to be migrated.Memory package 220 can be non-by first during refresh operation The the first page data PD1 stored in volatile memory chip 223a moves to volatile memory chip 222.
Here, the address administration unit AMU of memory package 220 can manage PD1 pairs of the first page data with being migrated The address answered.For example, migrate the first page data PD1 after, when receive with migration the first page data PD1 corresponding first During address AD DR1, the first address AD DR1 can be provided and be arrived volatile memory chip 222 by address administration unit AMU, so that The the first page data PD1 stored in volatile memory chip 222 must be exported.
As described above, when migrating the data of specific page, address administration unit AMU can manage or change what is received Address, to export certain number of pages evidence from volatile memory chip 222.
Figure 12 is block diagram of the diagram according to the memory package of the another embodiment of concept of the present invention.With reference to Figure 12, storage Device encapsulation 320 can include logic chip 321, the nonvolatile memory core of volatile memory chip the 322 and first to the 3rd Piece 323a to 323c.Logic chip 321 can include migration management unit MMU and Data Management Unit DMU.It described above is and patrol Chip 321, nonvolatile memory chip 323a to the 323c of volatile memory chip the 322 and first to the 3rd are collected, and therefore Can be so that description is omitted.
Data Management Unit DMU can manage the data received from external device (ED) (for example, processor).For example, data Administrative unit DMU can determine the attribute of received data.Data Management Unit DMU can be based on identified attribute easy Number is optionally write in the property lost memory chip the 322 or first to the 3rd nonvolatile memory chip 323a to 323c According to.
For example, when received data is dsc data, Data Management Unit DMU can set address and be received so as to obtain Data be written into volatile memory chip 322.Alternatively, when received data is cold data, data management list First DMU can set address and be arrived so as to obtain received data and be written in the first to the 3rd nonvolatile memory chip 323a In 323c.In the exemplary embodiment, the header letter that Data Management Unit DMU can be based on size of data, the type of data, data Breath etc. determines that received data is dsc data or cold data.
Figure 13 is the flow chart for describing Data Management Unit DMU as shown in figure 12 operation.With reference to Figure 12 and figure 13, data can be received from external device (ED) (for example, processor) in step S210, Data Management Unit DMU.For example, as above institute State, Data Management Unit DMU can by data-signal DQ and data strobe signal DQS from external device (ED) receive data.
The attribute of received data can be determined in step S220, Data Management Unit DMU.For example, data management list First DMU can based on size of data, the type of data, header information of data etc. determine received data be dsc data or Cold data.
In step S230, Data Management Unit DMU can based on determined by result in volatile memory chip or Received data is stored in nonvolatile memory chip.For example, when received data is dsc data, data management list First DMU can change address corresponding with received data, to cause received data to be written into volatile memory core In piece 322.When received data is cold data, Data Management Unit DMU can change corresponding with received data Address, to cause received data to be written into the first to the 3rd nonvolatile memory chip 323a to 323c.In example In embodiment, although not shown in fig. 13, but the address changed can be by the address administration unit with reference to Figure 10 descriptions AMU is managed.
In the exemplary embodiment, the data that Data Management Unit DMU can be to store in managing non-volatile memory chip Dsc data.For example, the data stored in nonvolatile memory chip can be cold data.But, based on being sealed to memory It is dsc data that its type change is there may be among the frequency of access of dress, the data stored in nonvolatile memory chip Data.Here, Data Management Unit DMU can manage the access to nonvolatile memory chip and can be deposited from non-volatile The data that its type change is dsc data are determined among the data stored in memory chip.In the exemplary embodiment, it is non-volatile Its type change can be moved to volatile for the data of dsc data by migration operation among the data stored in memory chip Property memory chip.
As described above, memory package can the attribute based on received data and in volatile memory chip or Received data is stored in nonvolatile memory chip.It is, the high dsc data of its frequency of access can be stored in tool In the volatile memory chip for having fast service speed, and the low cold data of its frequency of access can be stored in relatively slow In the nonvolatile memory chip of service speed, thus maintain access speed and increase available memory capacity.
Figure 14 is block diagram of the diagram according to the custom system of the another embodiment of concept of the present invention.With reference to Figure 14, user system System 40 can include processor 401 and memory module 400.Processor 401 can include Memory Controller 401a.Memory Controller 401a is configurable to control memory module 400.For example, Memory Controller 401a can will be used for control storage Address AD DR, the order CMD and clock CK of device module 400 are sent to memory module 400.Memory Controller 401a can lead to Cross data-signal DQ and data strobe signal DQS exchanges data with memory module 400.
Memory module 400 can include RCD 410 and memory package 420.It described above is RCD410 and memory Encapsulation 420, and therefore can be so that description is omitted.In the exemplary embodiment, RCD 410 as shown in figure 14 can include upper Migration management unit MMU, address administration unit AMU, Data Management Unit DMU or the nonvolatile memory management of face description Unit NMU.
For example, can be including migration management unit MMU, address administration referring to figs. 1 to Figure 13 memory packages described Operated under the control of unit AMU, Data Management Unit DMU or nonvolatile memory administrative unit NMU logic chip.
But, RCD 410 as shown in figure 14 can include migration management unit MMU, address administration unit AMU, data Administrative unit DMU or nonvolatile memory administrative unit NMU, can control the migration of memory package described above to grasp Work, address translation operation and data management operations, and all kinds for controlling nonvolatile memory chip can be generated Control signal.It is, memory package 420 can include volatile memory chip and nonvolatile memory chip, And can be operated under RCD 410 control.
In the exemplary embodiment, Memory Controller 401a can include translation look-aside buffer TLB.Translation look-aside is buffered Device TLB can include the address information or index information of the data on being stored in memory module 400.For example, processor Whether 401 can scan translation look-aside buffer TLB to determine the data to be accessed in memory module 400.When accessing Data not in memory module 400 when, processor 401 can from other storage mediums read the data to be accessed.When will When the data of access are in memory module 400, Memory Controller 401a can be provided corresponding address AD DR to storage Device module 400.Memory module 400 can export data corresponding with the address AD DR received.
In the exemplary embodiment, can be with when performing migration operation in the memory package 420 in memory module 400 Translation look-aside buffer TLB is updated based on Data Migration result.For example, working as the first page data from non-volatile memory device When moving to volatile memory devices, memory module 400 can update translation look-aside buffer TLB to cause first page number According to corresponding to volatile memory devices.
In the exemplary embodiment, by one of one or more of the translation look-aside buffer TLB address AD DR selected Divide volatile memory chip and Fei Yi that (for example, highest significant position (MSB)) can be indicated in memory package 420 The information of at least one in the property lost memory chip.Here, RCD 410 can control storage based on address AD DR MSB Device encapsulates at least one in volatile memory chip and nonvolatile memory chip in 420.
In the exemplary embodiment, in fig. 14, RCD 410 can include migration management unit MMU, address administration unit AMU, Data Management Unit DMU or nonvolatile memory administrative unit NMU.For example, migration management unit MMU, address pipe Reason unit AMU, Data Management Unit DMU and nonvolatile memory administrative unit NMU can be respectively included in processor 401, In Memory Controller 401a, RCD 410 and memory package 420, or can be individually to control circuit realiration.
Figure 15 is the block diagram for the custom system for exemplarily illustrating the another embodiment according to concept of the present invention.With reference to figure 15, custom system 50 can include processor 501 and memory module 500.Processor 501 can include Memory Controller 501a.Memory module 500 can include RCD 510 and memory package 520.It described above is processor 501, memory control Device 501a processed, memory module 500, RCD 510 and memory package 520, and therefore can be so that description is omitted.
Waiting signal WS can be output to RCD 510 by memory package 520.Waiting signal WS can be indicated for depositing Reservoir encapsulation 520 gets out the signal of access.For example, as described above, memory package 520 can include volatile memory core Piece and nonvolatile memory chip.The access speed or service speed of nonvolatile memory chip can be deposited than volatibility Memory chip it is slow.RCD 510 can be based on predefined communication protocol control memory encapsulation 520.In the exemplary embodiment, Predefined communication protocol can be the communication protocol based on volatile memory chip.It is, when access has slow operation During the nonvolatile memory chip of speed, memory module can not be operated normally.
When performing to the access of nonvolatile memory chip, memory package 520 can will be non-as being used to indicating The waiting signal WS that volatile memory chip gets out the signal of access is sent to RCD 510.RCD 510 can in response to etc. Treat the nonvolatile memory chip that signal WS accesses memory package 520 includes.In the exemplary embodiment, RCD 510 can Memory Controller 501a is arrived so that waiting signal WS to be provided.Memory Controller 501a can be accessed in response to waiting signal WS Memory module 500.
In the exemplary embodiment, memory module 500 can be identified as one by the Memory Controller 501a of processor 501 Individual address area.For example, the Memory Controller 501a of processor 501 can include volatile memory chip and non-volatile Memory chip.Memory Controller 501a can manage volatile memory chip and non-volatile as an address area Memory chip, without being distinguished between volatile memory chip and nonvolatile memory chip.Here, processor 501 It cannot recognize the data storage to be accessed in volatile memory devices or non-volatile memory device.It is, Processor 501 cannot normally control memory module 500.
, can be by waiting signal WS according to the memory module 500 of embodiment when accessing nonvolatile memory chip Processor 501 is provided and can notify to notify the access to nonvolatile memory chip to be ready to processor 501.Processing Device 501 can normally access the data stored in nonvolatile memory chip in response to waiting signal WS.
As described above, can be in refresh operation according to the memory package of the memory module of the embodiment of concept of the present invention Data are moved to volatile memory chip by period from nonvolatile memory chip.In addition, memory package can include The volatile memory chip and nonvolatile memory chip of stacking, and can perform by the migration through silicon hole TSV Operation.Memory package can manage the address of migration.Memory package can manage received data.As described above, root According to the embodiment of concept of the present invention, the memory module with increased memory capacity and improved performance can be provided.
In the exemplary embodiment, migration management unit MMU, address administration unit AMU, Data Management Unit DMU or non- Each in volatile memory administrative unit NMU can be realized with hardware or software.
Figure 16 is the block diagram for exemplarily illustrating volatile memory chip as shown in Figure 3.In the exemplary embodiment, it is false Determining volatile memory chip 122 is, but is not limited to DRAM.
With reference to Figure 16, volatile memory chip 122 can include memory cell array 122_1, address buffer 122_2, X- decoder 122_3, Y- decoder 122_4 and sensing amplifier and write driver block 122_5.
Memory cell array 122_1 can include multiple memory cells.Memory cell can be arranged in many Individual wordline WL and multiple bit line BL intersection.Memory cell may be coupled to wordline WL and bit line BL.In memory cell Each can include capacitor and transistor.
Address buffer 122_2 can receive address AD DR from external device (ED) (for example, logic chip or RCD), and can To buffer received address AD DR.The address AD DR received can be provided and be arrived X- decoders by address buffer 122_2 122_3 or Y- decoders 122_4.
X- decoders 122_3 can receive row control command RAS from external device (ED) (for example, logic chip or RCD), and At least one wordline can be activated in response to received signal.In the exemplary embodiment, X- decoders 122_3 can be from address Buffer 122_2 receives row address (ADDR_row), and the wordline of activation can be wordline corresponding with the row address received.
Y- decoders 122_4 can receive row control command RAS from external device (ED) (for example, logic chip or RCD), and At least one bit line can be activated in response to received signal.In the exemplary embodiment, Y- decoders 122_4 can be from address Buffer 122_2 receives column address (ADDR_col), and the bit line of activation can be bit line corresponding with the column address received.
Sensing amplifier and write driver block 122_5 can be connected to Y- decoders 122_4 by multiple data wire DL.Sense Amplifier and write driver block 122_5 can sense the fluctuation of (or detection) data wire DL voltage, to amplify and export The fluctuation of voltage, or can be based on the data by data-signal DQ and data strobe signal DQS receptions come control data line DL voltage.
Figure 17 is the first nonvolatile memory core for exemplarily illustrating nonvolatile memory chip as shown in Figure 3 The block diagram of piece.With reference to Figure 17, the first nonvolatile memory chip 123a can include memory cell array 123a_1, address Decoder 123a_2, control circuit 123a_3, page buffer 123a_4 and input/output circuitry 123a_5.
Memory cell array 123a_1 can include multiple memory blocks.Each in memory block can include many Individual unit string, and each unit string can include multiple memory cells.Memory cell may be coupled to multiple wordline WL. Memory cell can be made up of along line direction and column direction arrangement and every page memory cell.
Address decoder 123a_2 can be by going here and there selection line SSL, wordline WL and ground selection line GSL is connected to memory list Element array 123a_1.Address decoder 123a_2 can receive address from external device (ED) (for example, logic chip or RCD) ADDR_n, and received address AD DR_n can be decoded.Address decoder 123a_2 can be based on the address choice decoded At least one wordline WL and selected wordline can be controlled.In the exemplary embodiment, address AD DR_n can be with right and wrong volatibility The corresponding addresses of memory chip 123a.Address AD DR_n can be the address changed by address administration unit AMU (with reference to figure 10)。
Control circuit 123a_3 order CMD_n and control can be received from external device (ED) (for example, logic chip or RCD) Signal CTRL, and address decoder 123a_2, page buffer 123a_4 and input/defeated can be controlled in response to received signal Go out circuit 123a_5.In the exemplary embodiment, logic chip 121 can be in response to the order CMD_n from processor 101, will Order CMD_n and control signal CTRL corresponding with order, which are provided, arrives non-volatile memory device NVM.
Page buffer 123a_4 can be connected to memory cell array 123a_1 by multiple bit line BL, and can pass through Multiple data wire DL are connected to input/output circuitry 123a_5.Page buffer 123a_4 can control circuit 123a_3 control Control bit line BL under system, depositing from the input/output circuitry 123a_5 data storages received by data wire DL In memory cell array 123a_1.Page buffer 123a_4 can read under control circuit 123a_3 control and be stored in Data in memory cell array 123a_1.
Input/output circuitry 123a_5 can exchange data with external device (ED) (for example, logic chip or processor).
There is provided three-dimensional (3D) memory array in the example embodiment of concept of the present invention.3D memory arrays are monolithically Formed in one or more physical levels of the array of memory cell, the array of the memory cell have silicon substrate it The active region of upper setting and the circuit associated with the operation of those memory cells, no matter this associated circuit is at this Kind of substrate or within.Term " monolithic " refers to that every grade of layer of array is deposited directly to the layer of each subordinate of array On.
In the example embodiment of concept of the present invention, 3D memory arrays include vertically oriented to cause at least one to deposit Storage unit is located at the vertical nand string above another memory cell.At least one memory cell can include charge trap Layer.Each vertical nand string can include being located at least one selection transistor above memory cell, at least one choosing Selecting transistor has and memory cell identical structure and is monolithically formed together with memory cell.
The following patent document that this is incorporated herein by reference describes the appropriate configuration of 3 D memory array, wherein three-dimensional Memory array configuration is multiple levels, shared word line and/or bit line between at different levels：United States Patent (USP) No.7,679,133；No.8, 553,466；No.8,654,587；No.8,559,235 and U.S. Patent Publication No.2011/0233648.
Figure 18 is block diagram of the diagram according to the memory module of the embodiment of concept of the present invention.In the exemplary embodiment, such as Memory module 1000 shown in Figure 18 can have the structure of load reduction dual inline memory modules (LRDIMM).Such as Memory module 1000 shown in Figure 18 may be mounted on DIMM sockets and can be with processor communication.
With reference to Figure 18, memory module 1000 can include RCD 1100, SPD 1200, multiple memory packages 1310 and arrive 1380 and multiple data buffers 1410 to 1480.In the exemplary embodiment, RCD, SPD and storage are described referring to figs. 1 to Figure 16 Device is encapsulated, and therefore can omit RCD 1100, SPD 1200 and memory package 1310 to 1380 detailed description.
Each in data buffer 1410 to 1480 is configurable to exchange number with external device (ED) (for example, processor) It is believed that number DQ and data strobe signal DQS.In addition, data buffer 1410 to 1480 be configurable to respectively with memory package 1310 to 1380 exchange data signals DQ and data strobe signal DQS.
In the exemplary embodiment, each in memory package 1310 to 1380 as described above can be mixing storage Device is encapsulated.In addition, each in memory package 1310 to 1380 can be according to the operating method described referring to figs. 1 to Figure 18 To operate.
Figure 19 is block diagram of the diagram according to the memory module of another embodiment of concept of the present invention.In example embodiment In, memory module 2000 as shown in figure 19 can have the structure of register dual inline memory modules (RDIMM). Memory module 2000 as shown in figure 19 may be mounted on DIMM sockets and can be with processor communication.
With reference to Figure 19, memory module 2000 can include RCD 2100, SPD 2200 and multiple memory packages 2310 To 2380.Compared with memory module 1000 as shown in figure 18, memory module 2000 as shown in figure 19 can not include Data buffer.Each in memory package 2310 to 2380 can pass through data-signal DQ and data strobe signal DQS With external device (ED) (for example, processor) direct communication.
In the exemplary embodiment, each in memory package 2310 to 2380 as described above can be mixing storage Device is encapsulated, and can be operated according to the operating method described referring to figs. 1 to Figure 16.
Figure 20 is the server system of exemplarily memory module of the diagram including the embodiment according to concept of the present invention Figure.With reference to Figure 20, server system 3000 can include multiple server racks 3100.It is each in server rack 3100 It is individual to include multiple memory modules 3200.Memory module 3200, which can be directly connected to, is respectively included in server rack Processor in 3100.For example, memory module 3200 can have the form of dual inline memory modules, it can install In the DIMM sockets of processor are electrically connected to, and can be with processor communication.In the exemplary embodiment, memory module 3200 It may be used as the storage device or operation memory of server system 3000.In the exemplary embodiment, memory module 3200 It can be operated according to the method described referring to figs. 1 to Figure 19.
Figure 21 is memory module or the electronics of memory package of the diagram including the embodiment according to concept of the present invention The block diagram of system.Electronic system 4000 can be can use or support to be carried by mobile industrial processor interface (MIPI) alliance The data processing equipment of the interface of confession is realized.For example, electronic system 4000 can be with mobile terminals, personal digital assistant (PDA), portable media player (PMP), smart phone or wearable device are realized.
Electronic system 4000 can include application processor 4100, display 4220 and imaging sensor 4230.Using place DigRF main equipments 4110, display serial line interface (DSI) main frame 4120, camera serial line interface (CSI) master can be included by managing device 4100 Machine 4130 and physical layer (PHY) 4140.
DSI main frames 4120 can be communicated by DSI with the DSI devices 4225 of display 4220.For example, optical serial device SER can be realized in DSI main frames 4120, and optics deserializer DES can be realized in DSI devices 4225.
CSI main frames 4130 can be communicated by CSI with the CSI devices 4235 of imaging sensor 4230.For example, optics unstrings Row device can be realized in CSI main frames 4130, and optical serial device can be realized in CSI devices 4235.
DSI and CSI can use physical layer and link layer.DSI and CSI can apply to the embodiment of concept of the present invention. The selectivity for example, DSI main frames 4120 and DSI devices 4225 can be communicated by the equity (P2P) between physical layer and link layer Extract error log in ground.Alternatively, CSI devices 4235 and CSI main frames 4130 can pass through the P2P between physical layer and link layer Error log is optionally extracted in communication.
Electronic system 4000 may further include radio frequency (RF) chip 4240 for being communicated with application processor 4100. RF chips 4240 can include physical layer (PHY) 4242, DigRF slave units 4244 and antenna 4246.For example, RF chips 4240 Physical layer 4242 and the physical layer of application processor 4,100 4140 can each other be handed over by the DigRF interfaces provided by MIPI alliances Change data.
Electronic system 4000 may further include working storage 4250 and embedded/card memory appts 4255.Work Memory 4250 and embedded/card memory appts 4255 can store the data received from application processor 4100.In addition, work Making memory 4250 and embedded/card memory appts 4255 can provide the data stored wherein and arrive application processor 4100.In the exemplary embodiment, working storage 4250 can be the memory module described referring to figs. 1 to Figure 20.In example In embodiment, working storage 4250 can include multiple memory packages, and each memory package can include it is volatile Property memory chip and nonvolatile memory chip.Each memory package can perform migration behaviour during refresh operation Make.
Working storage 4250 can provisionally store via or the data that will be handled by application processor 4100. Working storage 4250 can include volatile memory chip, such as SRAM, DRAM, SDRAM etc., and nonvolatile memory Chip, such as flash memories, PRAM, MRAM, ReRAM, FRAM etc..
Embedded/card memory appts 4255 can with data storage regardless of whether power supply how.In the exemplary embodiment, it is embedded Formula/card memory appts 4255 can store (UFS) interface protocol according to Common Flash Memory and operate, but not limited to this.Embedded/card Storage device 4255 can include the non-volatile memory device described referring to figs. 1 to Figure 20.In embedded/card memory appts 4255 non-volatile memory devices included can based on the program success described referring to figs. 1 to Figure 20/unsuccessfully determination side Method performs programming operation.
Electronic system 4000 can pass through worldwide interoperability (WiMAX) 4260, the wireless local for microwave access Net (WLAN) 4262 and the grade of ultrabroad band (UWB) 4264 and External system communication.
Electronic system 4000 may further include the loudspeaker 4270 and microphone 4275 for handling voice messaging.Electricity Subsystem 4000 may further include global positioning system (GPS) device 4280 for processing position information.Electronic system 4000 may further include the bridging chip 4290 for managing the connection between peripheral unit.
It is apparent to those skilled in the art although describing concept of the present invention by reference to exemplary embodiment, do not carrying on the back Various changes and modifications can be made in the case of spirit and scope from the present invention.It is therefore understood that implementing above Example is not restricted, but illustrative.
The embodiment of concept of the present invention can provide memory package, the memory module with the memory package and its Operating method, they have increased memory capacity and improved performance.

Claims (20)

1. a kind of memory package, including：
Nonvolatile memory chip；
Volatile memory chip, its access speed is faster than the access speed of the nonvolatile memory chip；With
Logic chip, is configured to perform on the volatile memory chip in response to the refresh command from external device (ED) Refresh operation, and when performing refresh operations move at least a portion of the data stored in the nonvolatile memory chip Move on to the volatile memory chip.
2. memory package as claimed in claim 1, wherein, the logic chip is performed by individually migrating designated lane Migration operation.
3. memory package as claimed in claim 1, wherein, the nonvolatile memory chip and the volatile storage Device chip is stacked on the direction perpendicular to logic chip, and
Wherein, the nonvolatile memory chip, the volatile memory chip and the logic chip pass through through-silicon Through hole is connected to each other.
4. memory package as claimed in claim 3, wherein, the logic chip through silicon hole by performing migration behaviour Make.
5. memory package as claimed in claim 1, wherein, the logic chip determines the nonvolatile memory chip The data to be migrated among the data of middle storage.
6. memory package as claimed in claim 5, wherein, the data to be migrated are that its frequency of access is higher than specific level Other data.
7. memory package as claimed in claim 1, wherein, the logic chip includes：
Nonvolatile memory administrative unit, is configured to perform the garbage collection on the nonvolatile memory chip Operation and loss balancing operation.
8. memory package as claimed in claim 1, wherein, the logic chip includes：
Address administration unit, is configured to manage the ground of the nonvolatile memory chip and the volatile memory chip Location, to cause output data corresponding with the address received from the external device (ED).
9. memory package as claimed in claim 8, wherein, when the corresponding data storage in address with being received it is described easily Lose property memory chip in when, the address that the address administration cell translation is received with cause output in the volatile storage The data stored in device device.
10. memory package as claimed in claim 1, wherein, it is described to patrol when accessing the nonvolatile memory chip Collect chip and the waiting signal as the signal accessed for indicating the nonvolatile memory chip to be ready to is sent to institute State external device (ED).
11. memory package as claimed in claim 1, wherein, the memory package is connect based on Double Data Rate (DDR) Mouth and the communication with external apparatus.
12. a kind of memory module, including：
Memory package, including volatile memory chip and nonvolatile memory chip；With
Random access memory (RAM) control device, is configured to the control memory under the control of external device (ED) and encapsulates, and week Refresh command is sent to phase property to the memory package,
Wherein, refresh operation of the memory package in response to refresh command execution on the volatile memory chip, And during refresh operation by least a portion of the data stored in the nonvolatile memory chip move to it is described easily The property lost memory chip.
13. memory module as claimed in claim 12, wherein, the memory package includes multiple data signal lines, and
Wherein, the memory package exchanges data with external device (ED) by a part for data signal line, and is believed by data The remainder of number line moves at least a portion of the data stored in the nonvolatile memory chip described volatile Property memory chip.
14. memory module as claimed in claim 12, wherein, the memory package further comprises：
Logic chip, is configured to control the volatile memory chip under the control of RAM control devices and described non-easy The property lost memory chip.
15. memory module as claimed in claim 14, wherein, the volatile memory chip and described non-volatile deposit Memory chip is stacked on the direction perpendicular to the logic chip, and the nonvolatile memory chip, the volatibility Memory chip and the logic chip through silicon hole by being connected to each other.
16. memory module as claimed in claim 15, wherein, the memory package is by will be described non-through silicon hole At least a portion of the data stored in volatile memory chip moves to the volatile memory chip.
17. memory module as claimed in claim 12, wherein, the volatile memory chip is that dynamic randon access is deposited Reservoir (DRAM), and the nonvolatile memory chip is NAND-flash memory.
18. memory module as claimed in claim 17, wherein, the nonvolatile memory chip includes three-dimensional (3D) and deposited Memory array.
19. memory module as claimed in claim 12, further comprises serially there is detection chip, described serial in the presence of inspection Surveying chip includes the device information on memory module.
20. a kind of operating method of memory package,
Wherein, the memory package includes volatile memory chip and nonvolatile memory chip,
The operating method includes：
Refresh command is received from external device (ED)；With
In the refresh operation performed in response to refresh command for volatile memory chip, by the nonvolatile memory At least a portion of the data stored in chip moves to the volatile memory chip.
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108665936A (en) * 2018-07-11 2018-10-16 睿力集成电路有限公司 Systematization encapsulation aggregate
CN108962301A (en) * 2018-05-24 2018-12-07 济南德欧雅安全技术有限公司 A kind of storage device
CN109656748A (en) * 2018-12-10 2019-04-19 华中科技大学 A method of the MLC nand flash memory bit error rate is reduced by data pattern remapping
CN109753237A (en) * 2017-11-01 2019-05-14 三星电子株式会社 Calculate equipment and non-volatile dual inline memory modules
CN110096366A (en) * 2019-05-10 2019-08-06 苏州浪潮智能科技有限公司 A kind of configuration method, device and the server of isomery memory system
CN110728998A (en) * 2018-07-17 2020-01-24 爱思开海力士有限公司 Memory device and memory system having the same
WO2020041442A1 (en) * 2018-08-23 2020-02-27 Micron Technology, Inc. Disturb management based on write times
WO2020077518A1 (en) * 2018-10-16 2020-04-23 华为技术有限公司 Hybrid storage device and access method
CN111625392A (en) * 2019-02-27 2020-09-04 西部数据技术公司 Memory die layout for failure protection in an SSD
US20220148653A1 (en) * 2020-11-12 2022-05-12 Commissariat à I'Energie Atomique et aux Energies Alternatives Hybrid resistive memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070136523A1 (en) * 2005-12-08 2007-06-14 Bonella Randy M Advanced dynamic disk memory module special operations
CN101281494A (en) * 2002-09-11 2008-10-08 株式会社日立制作所 System and method for using dynamic random access memory and flash memory
US20090193186A1 (en) * 2008-01-25 2009-07-30 Barth Jr John E Embedded dram having multi-use refresh cycles
US20100202237A1 (en) * 2009-02-11 2010-08-12 Stec, Inc. Flash backed dram module with a selectable number of flash chips
CN101960430A (en) * 2007-07-25 2011-01-26 技佳科技有限公司 Hybrid nonvolatile memory
US20130077382A1 (en) * 2011-09-26 2013-03-28 Samsung Electronics Co., Ltd. Hybrid memory device, system including the same, and method of reading and writing data in the hybrid memory device
US20150199126A1 (en) * 2014-01-10 2015-07-16 Advanced Micro Devices, Inc. Page migration in a 3d stacked hybrid memory

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281494A (en) * 2002-09-11 2008-10-08 株式会社日立制作所 System and method for using dynamic random access memory and flash memory
US20070136523A1 (en) * 2005-12-08 2007-06-14 Bonella Randy M Advanced dynamic disk memory module special operations
CN101960430A (en) * 2007-07-25 2011-01-26 技佳科技有限公司 Hybrid nonvolatile memory
US20090193186A1 (en) * 2008-01-25 2009-07-30 Barth Jr John E Embedded dram having multi-use refresh cycles
US20100202237A1 (en) * 2009-02-11 2010-08-12 Stec, Inc. Flash backed dram module with a selectable number of flash chips
US20130077382A1 (en) * 2011-09-26 2013-03-28 Samsung Electronics Co., Ltd. Hybrid memory device, system including the same, and method of reading and writing data in the hybrid memory device
US20150199126A1 (en) * 2014-01-10 2015-07-16 Advanced Micro Devices, Inc. Page migration in a 3d stacked hybrid memory

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109753237B (en) * 2017-11-01 2024-04-05 三星电子株式会社 Computing device and non-volatile dual in-line memory module
CN109753237A (en) * 2017-11-01 2019-05-14 三星电子株式会社 Calculate equipment and non-volatile dual inline memory modules
CN108962301A (en) * 2018-05-24 2018-12-07 济南德欧雅安全技术有限公司 A kind of storage device
CN108665936A (en) * 2018-07-11 2018-10-16 睿力集成电路有限公司 Systematization encapsulation aggregate
CN108665936B (en) * 2018-07-11 2024-03-26 长鑫存储技术有限公司 Systematic packaging aggregate
CN110728998A (en) * 2018-07-17 2020-01-24 爱思开海力士有限公司 Memory device and memory system having the same
CN110728998B (en) * 2018-07-17 2023-04-28 爱思开海力士有限公司 Memory device and memory system having the same
WO2020041442A1 (en) * 2018-08-23 2020-02-27 Micron Technology, Inc. Disturb management based on write times
US10586592B1 (en) 2018-08-23 2020-03-10 Micron Technology, Inc. Disturb management based on write times
CN111512374B (en) * 2018-10-16 2022-11-11 华为技术有限公司 Hybrid storage device and access method
CN111512374A (en) * 2018-10-16 2020-08-07 华为技术有限公司 Hybrid storage device and access method
WO2020077518A1 (en) * 2018-10-16 2020-04-23 华为技术有限公司 Hybrid storage device and access method
CN109656748A (en) * 2018-12-10 2019-04-19 华中科技大学 A method of the MLC nand flash memory bit error rate is reduced by data pattern remapping
CN111625392A (en) * 2019-02-27 2020-09-04 西部数据技术公司 Memory die layout for failure protection in an SSD
CN111625392B (en) * 2019-02-27 2023-03-31 西部数据技术公司 Memory die layout for failure protection in an SSD
CN110096366A (en) * 2019-05-10 2019-08-06 苏州浪潮智能科技有限公司 A kind of configuration method, device and the server of isomery memory system
US20220148653A1 (en) * 2020-11-12 2022-05-12 Commissariat à I'Energie Atomique et aux Energies Alternatives Hybrid resistive memory

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