CN107039059B - Memory package, memory module including the same, and memory package operation method - Google Patents

Memory package, memory module including the same, and memory package operation method Download PDF

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Publication number
CN107039059B
CN107039059B CN201710061219.6A CN201710061219A CN107039059B CN 107039059 B CN107039059 B CN 107039059B CN 201710061219 A CN201710061219 A CN 201710061219A CN 107039059 B CN107039059 B CN 107039059B
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volatile memory
chip
memory
memory chip
data
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CN107039059A (en
Inventor
金灿景
姜郁成
金南升
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

A memory package is disclosed. The memory package includes a nonvolatile memory chip, a volatile memory chip having an access speed faster than that of the nonvolatile memory chip, and a logic chip for performing a refresh operation with respect to the volatile memory chip in response to a refresh command from an external device and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

Description

Memory package, memory module including the same, and memory package operation method
Technical Field
The present disclosure relates to a semiconductor memory, and more particularly, to a memory package, a memory module having the same, and an operating method thereof.
Background
The semiconductor memory may be a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like. Semiconductor memory devices are typically divided into volatile memory devices and non-volatile memory devices.
Volatile memory devices refer to memory devices in which stored data is lost when power is turned off. On the other hand, a nonvolatile memory device refers to a memory device that retains stored data when power is turned off. Since a Dynamic Random Access Memory (DRAM), which is one of volatile memory devices, has a high access speed, the DRAM is widely used as a working memory, a cache memory, a main memory, and the like of a computing system. With the development of computing technology, the demand of DRAMs as working memories of computing systems has increased. Because DRAM memory cells typically include capacitors and transistors, it is difficult to reduce the cell size to less than a constant level. Therefore, it is difficult to realize a large capacity DRAM in a limited area.
To address this problem, non-volatile dual in-line memory modules (NVDIMMs) based on non-volatile memory and DRAM operations have been developed. NVDIMMs can provide high capacity working memory by combining high capacity nonvolatile memory and DRAM. However, since the operating characteristics, operating methods, and the like of the nonvolatile memory are different from those of the DRAM, various methods may be required for controlling and managing them.
Disclosure of Invention
Embodiments of the inventive concept provide a memory package, a memory module having the same, and an operating method thereof, which perform data migration during a refresh operation and have an increased storage capacity without performance degradation.
According to an aspect of the inventive concept, a memory package may include a nonvolatile memory chip, a volatile memory chip having an access speed faster than that of the nonvolatile memory chip, and a logic chip for performing a refresh operation with respect to the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.
The nonvolatile memory chip and the volatile memory chip may be stacked in a direction perpendicular to the logic chip, and the nonvolatile memory chip, the volatile memory chip, and the logic chip may be connected to each other by through-silicon vias.
According to another aspect of the inventive concept, a memory module may include a memory package including a volatile memory chip and a non-volatile memory chip, and a Random Access Memory (RAM) control device for controlling the memory package under control of an external device and periodically transmitting a refresh command to the memory package. The memory package may perform a refresh operation with respect to the volatile memory chip in response to the refresh command, and may migrate at least a portion of data stored in the non-volatile memory chip to the volatile memory chip during the refresh operation.
The memory package may include a plurality of data signal lines. The memory package may exchange data with an external device through a portion of the data signal line, and may migrate at least a portion of the data stored in the nonvolatile memory chip to the volatile memory chip through a remaining portion of the data signal line.
According to another aspect of the inventive concept, a memory package includes a volatile memory chip and a non-volatile memory chip. The operation method of the memory package comprises the following steps: receiving a refresh command from an external device; and migrating at least a portion of the data stored in the non-volatile memory chip to the volatile memory chip when a refresh operation is performed for the volatile memory device in response to the refresh command.
Drawings
The above and other objects and features will become apparent from the following description with reference to the accompanying drawings in which like reference numerals refer to like parts throughout the various figures unless otherwise specified, and in which:
FIG. 1 is a block diagram illustrating a user system according to some embodiments of the present inventive concept;
FIG. 2 is a block diagram illustrating an exemplary memory module, such as shown in FIG. 1, in accordance with certain embodiments;
FIG. 3 is a diagram illustrating an exemplary memory package such as that shown in FIG. 2, in accordance with certain embodiments;
FIG. 4 is a perspective view illustrating an exemplary memory package such as that shown in FIG. 3, in accordance with certain embodiments;
FIG. 5 is a block diagram illustrating an exemplary memory package such as that shown in FIG. 2 in accordance with certain embodiments of the present inventive concept;
FIG. 6 is a perspective view illustrating an exemplary memory package such as shown in FIG. 5, in accordance with certain embodiments;
FIG. 7 is a flowchart illustrating exemplary operations of the memory package shown in FIG. 2, in accordance with certain embodiments;
FIG. 8 is a block diagram depicting exemplary operations, as shown in FIG. 7, in accordance with certain embodiments;
FIG. 9 is a block diagram illustrating an exemplary memory package, such as shown in FIG. 2, in accordance with certain embodiments of the present inventive concept;
FIG. 10 is a block diagram illustrating an exemplary memory package according to some embodiments of the present inventive concept;
FIG. 11 is a block diagram depicting exemplary operations of a memory package such as that shown in FIG. 10, according to some embodiments;
FIG. 12 is a block diagram illustrating an exemplary memory package according to some embodiments of the present inventive concept;
FIG. 13 is a flowchart describing exemplary operation of the data management unit DMU shown in FIG. 12 according to some embodiments;
FIG. 14 is a block diagram illustrating an exemplary user system in accordance with certain embodiments of the present inventive concept;
FIG. 15 is a block diagram illustrating an exemplary user system in accordance with certain embodiments of the present inventive concept;
FIG. 16 is a block diagram exemplarily illustrating an exemplary volatile memory chip such as that shown in FIG. 3 in accordance with certain embodiments;
FIG. 17 is a block diagram exemplarily illustrating an exemplary first non-volatile memory chip, such as the non-volatile memory chip illustrated in FIG. 3, in accordance with certain embodiments;
FIG. 18 is a block diagram illustrating an exemplary memory module according to some embodiments of the present inventive concept;
FIG. 19 is a block diagram illustrating an exemplary memory module according to some embodiments of the present inventive concept;
FIG. 20 is a diagram exemplarily illustrating a server system including a memory module according to some embodiments of the inventive concept; and
FIG. 21 is a block diagram illustrating an electronic system including a memory module or memory package according to some embodiments of the present inventive concept.
Detailed Description
In the following detailed description, certain exemplary embodiments of the present invention are shown and described, simply by way of illustration.
As used herein, a semiconductor device may refer to, for example, a device such as a semiconductor chip (e.g., a memory chip and/or a logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a package-on-package device including a plurality of packages. A package may refer to a single package substrate having one or more chips stacked thereon, or a package-on-package device having a plurality of single packages stacked on each other. These devices may be formed using ball grid arrays, wire bonds, through substrate vias, or other electrical connection elements, and may form memory devices such as volatile or non-volatile memory devices.
Additionally, as used herein, the term "memory device" generally refers to a memory chip or stack of memory chips, and/or a memory package. The memory package refers to a semiconductor package including a memory chip. For example, a memory package may include a package substrate and at least one semiconductor chip including an array of memory cells (such a chip may also be referred to as a memory chip). The memory package may include a memory chip in addition to a logic chip such as a memory controller. A memory package will typically include an encapsulant protection circuit of a package substrate and one or more chips stacked thereon. In some cases, a memory package may have at least two chips horizontally separated from each other that share the same encapsulant.
As used herein, a memory module includes a plurality of memory packages, memory chips, or stacks of memory chips that are horizontally separated from each other and formed on a substrate such as a printed circuit board. Each memory package, memory chip, or stack of memory chips at a particular horizontal location of the memory module typically includes its own encapsulant.
As used herein, an electronic device may generally refer to a semiconductor device, a memory device, or a memory module, and may additionally include products that include such devices, such as memory cards, hard drives that include additional components, or mobile phones, laptops, tablets, desktops, cameras, or other consumer electronic devices, and so forth.
A chip refers to a semiconductor device formed from a wafer, such as an integrated circuit formed on a die. As used herein, a chip does not include a package substrate or PCB.
A memory module according to some embodiments of the inventive concept may include a first memory package. The first memory package may include a volatile memory chip and a non-volatile memory chip. To maintain data of the volatile memory chips in the memory package, the memory package may periodically perform refresh operations. Here, the memory package may perform data migration from the nonvolatile memory chip to the volatile memory chip. Accordingly, embodiments of the inventive concept may provide memory packages and memory modules with improved performance and increased capacity.
The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. These example embodiments are merely "examples," and many implementations and variations are possible that do not require the details provided herein. It should also be emphasized that this disclosure provides details of alternative examples, but this list of alternatives is not exhaustive. Moreover, any consistency in details between various examples should not be construed as requiring such details-it is not practical to list every possible variation for every feature described herein. Reference should be made to the claim language for determining the requirements of the present invention.
In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. While the various figures illustrate variations of the exemplary embodiments, the figures are not necessarily intended to be mutually exclusive. Rather, as the figures and their descriptions are generally considered in the context of the following detailed description, some features shown and described in different figures may be combined with other features from other figures to produce various embodiments.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as "/".
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, such terms are used merely to distinguish one element, component, region, layer or section from another element, component, region, layer or section, e.g., as a naming convention. Thus, a first element, component, region, layer or section discussed below in one section of the specification could be termed a second element, component, region, layer or section in another section of the specification or in the claims without departing from the teachings of the present invention. In addition, even if the terms "first", "second", and the like are not used in the specification to describe terms, they may be referred to in the claims as "first" or "second" to distinguish elements of different claims from each other.
It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "having," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, or components thereof, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between," "adjacent" with respect to "directly adjacent," etc.). However, the term "contact" as used herein refers to direct contact (i.e., touch), unless the context indicates otherwise.
Embodiments described herein will be described with reference to plan, perspective, and/or cross-sectional views by way of idealized schematic diagrams. Accordingly, the exemplary diagrams may be modified depending on manufacturing techniques and/or tolerances. Accordingly, the disclosed embodiments are not limited to those shown in the figures, but include modifications of configurations formed based on manufacturing processes. Accordingly, regions illustrated in the drawings may have schematic characteristics, and shapes of the regions illustrated in the drawings may exemplify specific shapes of regions of elements, to which aspects of the present invention are not limited.
Spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature or elements as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" may include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, terms such as "same," "equal," "planar," or "coplanar," when referring to an orientation, layout, location, shape, size, quantity, or other measure, do not necessarily refer to exactly the same orientation, layout, location, shape, size, quantity, or other measure, but are intended to encompass nearly the same orientation, layout, location, shape, size, quantity, or other measure within acceptable variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to reflect this meaning.
As used herein, a configuration describes items as being "electrically connected," such that an electrical signal can pass from one item to another. Thus, passive conductive components (e.g., wires, pads, internal wires, etc.) that are physically connected to a passive electrically insulating component (e.g., a prepreg (preprg) layer of a printed circuit board, an electrically insulating adhesive that connects two devices, an electrically insulating underfill (underfill) or mold layer, etc.) are not electrically connected to the component. Further, items that are "directly electrically connected" to each other are electrically connected through one or more passive elements, such as cables, pads, internal wires, vias, and the like. Thus, components that are directly electrically connected do not include components that are electrically connected through active elements, such as transistors or diodes. Items that are electrically connected may be described as being directly physically connected to indicate that they are directly physically adjacent to each other.
Although language such as "one embodiment" or "some embodiments" may be used to refer to the figures described herein, these figures and their corresponding description are not intended to be mutually exclusive from other figures or descriptions unless the context so indicates. Thus, certain aspects from certain figures may be the same as certain features in other figures, and/or certain figures may be different representations or different parts of a particular example embodiment.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and/or the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a block diagram illustrating a user system according to an embodiment of the inventive concept. Referring to fig. 1, a user system 10 may include a processor 101, a memory module 100, a chipset 102, a Graphics Processing Unit (GPU)103, an input/output device 104, and a storage device 105. In an example embodiment, the user system 10 may be an electronic device and may include a computer, a portable computer, an Ultra Mobile Personal Computer (UMPC), a workstation, a server computer, a netbook, a Personal Digital Assistant (PDA), a web tablet, a wireless telephone, a mobile telephone, a smartphone, a digital camera, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device capable of sending or receiving information in a wireless environment, or one of various electronic devices constituting a home network.
The processor 101 may control the overall operation of the user system 10. The processor 101 may perform various operations performed in the user system 10.
The memory module 100 may be used as a buffer memory, a main memory, a work memory, etc. of the user system 10. The memory module 100 may be directly connected to the processor 101. For example, the memory module 100 may be in the form of a dual in-line memory module (DIMM), and the memory module 100 may be mounted in a DIMM socket that is directly connected to the processor 101 to communicate with the processor 101. In this sense, memory module 100 may be electrically connected to processor 101 without any other integrated circuit devices, such as other chips, packages, or modules therebetween.
The chipset 102 may be electrically connected to the processor 101 and may control the hardware of the user system 10 under the control of the processor 101. For example, chipset 102 may be connected to GPU 103, input/output device 104, and storage device 105 through a host bus, and may perform bridging operations with respect to the host bus.
GPU 103 may perform a series of arithmetic operations for outputting image data of user system 10. In an example embodiment, the GPU 103 may be installed in the processor 101 in the form of a system on a chip (SoC).
The input/output devices 104 may include various devices for inputting data or instructions to the user system 10 or outputting data to external devices. For example, the input/output devices 104 may include user input devices such as a keyboard, keypad, button, touchpad, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, temperature sensor, biometric sensor, etc., and the input/output devices 104 may include user output devices such as a Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display device, active matrix OLED (amoled) display device, Light Emitting Diode (LED), speaker, motor, etc.
The storage device 105 may serve as a mass storage medium for the user system 10. The storage 105 may include a mass storage medium such as a Hard Disk Drive (HDD), a Solid State Drive (SSD), a memory card, a memory stick, and the like.
In an example embodiment, the memory module 100 may write or output data under the control of the processor 101. In example embodiments, the memory module 100 may include various types of memory. For example, the memory module 100 may be a hybrid memory and may be implemented based on various memory devices: volatile memory devices such as DRAM, Static Random Access Memory (SRAM), synchronous DRAM (sdram), or non-volatile memory devices such as Read Only Memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory devices, phase change ram (pram), magnetic ram (mram), resistive ram (rram), ferroelectric ram (fram), and the like.
FIG. 2 is a block diagram illustrating an exemplary memory module such as that shown in FIG. 1. Referring to fig. 1 and 2, a memory module 100 may include a RAM Control Device (RCD)110, a memory package 120, and a serial presence detect chip (SPD) 130.
The RCD 110 may control the memory package 120 under the control of the processor 101. For example, RCD 110 may receive address ADDR, command CMD, and clock CK from processor 101. In response to the received signals, the RCD 110 may control the memory package 120 such that data received through the data signal DQ and the data strobe signal DQs is written to the memory package 120 or such that data stored in the memory package 120 is output through the data signal DQ and the data strobe signal DQs. In an example embodiment, the RCD 110 may send the address ADDR, the command CMD, and the clock CK from the processor 101 to the memory package 120. The RCD 110 may be, for example, part of a chip such as a logic chip. The RCD 110 may be referred to herein as a RAM control circuit, or more generally a control circuit.
The memory package 120 may write data received through the data signal DQ and the data strobe signal DQs under the control of the RCD 110. Alternatively, the memory package 120 may output the written data through the data signal DQ and the data strobe signal DQs under the control of the RCD 110. In example embodiments, the memory package 120 may include various types of memory devices (e.g., memory chips). For example, the memory package 120 may include a NAND flash based non-volatile memory device and a DRAM based volatile memory device. In example embodiments, the memory package 120 may include a volatile memory device, such as DRAM, SRAM, SDRAM, or a non-volatile memory device, such as ROM, PROM, EPROM, EEPROM, flash memory device, PRAM, MRAM, RRAM, or FRAM.
In an example embodiment, the memory module 100 may include a plurality of memory packages. Each of the memory packages may operate under the control of the RCD 110. In an example embodiment, each of the memory packages may communicate with the RCD 110 based on a Double Data Rate (DDR) interface.
In some embodiments, SPD 130 may be a programmable read-only memory (e.g., EEPROM). The SPD 130 may include initial information or device information DI of the memory module 100. In an example embodiment, the SPD 130 may include initial information of the memory module 100 or memory system information MSI, such as module form, module configuration, memory capacity, module type, execution environment, and the like. When a user system 10 including the memory module 100 is booted up, the processor 101 may read the memory system information MSI from the SPD 130, and may identify the memory module 100 based on the memory system information MSI. The processor 101 may control the memory module 100 based on the memory system information MSI from the SPD 130. For example, the processor 101 may identify the type of memory enclosure 120 included in the memory module 100 based on the memory system information MSI from the SPD. Accordingly, some of the certain memory system information MSI may be module information, or more specifically, some of the certain memory system information MSI may be device information.
In an example embodiment, the SPD 130 may communicate with the processor 101 via a serial bus. The processor 101 may exchange signals with the SPD 130 via a serial bus. The SPD 130 may communicate with the RCD 110 via a serial bus. The serial bus may comprise at least one of a 2-wire serial bus, such as an inter-integrated circuit (I2C) bus, a system management bus (SMBus), a power management bus (PMBus), an Intelligent Platform Management Interface (IPMI) bus, a Management Component Transfer Protocol (MCTP) bus, and the like.
In an example embodiment, the memory package 120 may be a hybrid memory package including a non-volatile memory device and a volatile memory device (e.g., a non-volatile memory chip and a volatile memory chip). The memory module 100 including the hybrid memory package may be a non-volatile dimm (nvdimm). The operating speed of the non-volatile memory device may be slower than the operating speed of the volatile memory device. Thus, the memory package 120 may migrate data stored in the non-volatile memory device to the volatile memory device. In an example embodiment, the memory package 120 may perform a refresh operation and a migration operation together in response to a refresh command.
In accordance with certain embodiments of the inventive concept, in a memory module 100, a memory package 120 including a non-volatile memory device and a volatile memory device may perform migration during a refresh operation, thereby increasing memory capacity without losing performance. As a result, a memory module with reduced cost and improved performance may be provided.
Fig. 3 is a diagram illustrating an exemplary memory package such as that shown in fig. 2. Fig. 4 is a perspective view illustrating the memory package shown in fig. 3. Referring to fig. 3 and 4, the memory package 120 may include a logic chip 121, a volatile memory chip 122, and first to third nonvolatile memory chips 123a to 123 c. In example embodiments, the memory package 120 may include additional volatile or non-volatile memory chips. The memory package 120 may be a hybrid memory package.
Under the control of the RCD 110, the logic chip 121 may write data received through the data signal DQ and the data strobe signal DQs in the volatile memory chip 122 or the first to third nonvolatile memory chips 123a to 123 c. Under the control of the RCD 110, the logic chip 121 may output data written in the volatile memory chip 122 or the first to third nonvolatile memory chips 123a to 123c through the data signal DQ and the data strobe signal DQs.
The logic chip 121 may include a migration management unit MMU. The migration management unit MMU may move, copy, or migrate the data written in the first to third nonvolatile memory chips 123a to 123c to the volatile memory chip 122. Logic chip 121 may include logic circuitry for performing such tasks.
In example embodiments, the logic chip 121 may further include a buffer circuit for buffering a signal (e.g., a command CMD, an address ADDR, a data signal DQ, or a data strobe signal DQs) received from an external device, a nonvolatile memory control circuit for controlling the first to third nonvolatile memory chips 123a to 123c, or an address management circuit for managing addresses of the volatile memory chip 122 and the first to third nonvolatile memory chips 123a to 123 c.
The volatile memory chip 122 may write data or may output the written data under the control of the logic chip 121. In example embodiments, the volatile memory chips 122 may be SRAM or DRAM. For simplicity, it is assumed that the volatile memory chips 122 are DRAMs.
Under the control of the logic chip 121, each of the first to third nonvolatile memory chips 123a to 123c may write data or may output the written data. In example embodiments, each of the first to third nonvolatile memory chips 123a to 123c may include at least one of a ROM, a PROM, an EPROM, an EEPROM, a flash memory device, a PRAM, an MRAM, an RRAM, or an FRAM. For simplicity, it is assumed that each of the first to third nonvolatile memory chips 123a to 123c includes a flash memory device.
In some example embodiments, the storage capacity of the volatile memory chip 122 may be smaller than that of the first to third nonvolatile memory chips 123a to 123 c. The access speed of the volatile memory chip 122 may be faster than that of the first to third nonvolatile memory chips 123a to 123 c.
Each of the logic chip 121, the volatile memory chip 122, and the first to third nonvolatile memory chips 123a to 123c included in the memory package 120 may be a separate semiconductor chip or a separate die. The logic chip 121, the volatile memory chip 122, and the first to third nonvolatile memory chips 123a to 123c included in the memory package 120 may be stacked in a third direction perpendicular to a plane defined along the first and second directions. Thus, as shown in fig. 4, the logic chip 121 may be placed on a plane defined along the first and second directions, and the volatile memory chip 122 and the first to third nonvolatile memory chips 123a to 123c may be stacked in a third direction perpendicular to the logic chip 121. The stacked logic chip 121, volatile memory chip 122, and first to third nonvolatile memory chips 123a to 123c may be connected to each other through a plurality of through-substrate vias TSV (e.g., through-silicon vias). In example embodiments, the logic chip 121 may control each of the volatile memory chip 122 and the first to third nonvolatile memory chips 123a to 123c through the through-substrate via TSV.
In an example embodiment, the migration management unit MMU may perform the migration operation through the migration channel MC. The migration channel MC may be independent of the channels of the data signal DQ and the data strobe signal DQs. For example, the migration management unit MMU may perform the migration operation through the through-substrate via TSV. That is, the through-substrate via TSV may be used as the migration channel MC. The migration management unit MMU may perform transmission and reception with respect to data to be migrated through the through-substrate vias TSV. In an example embodiment, the migration channel MC may be implemented as a serial link.
As described above, since the storage capacity of the first to third nonvolatile memory chips 123a to 123c is larger than that of the volatile memory chip 122, the total storage capacity of the memory package 120 can be increased by storing data in the first to third nonvolatile memory chips 123a to 123 c. However, since the access speed of each of the first to third nonvolatile memory chips 123a to 123c is slower than that of the volatile memory chip 122, the overall performance may be degraded. Accordingly, the memory package 120 according to example embodiments may migrate a portion of data stored in the first to third nonvolatile memory chips 123a to 123c to the volatile memory chip 122 under certain conditions. In an example embodiment, the specific conditions may include the following: there are cases where data is to be migrated, where a refresh operation is performed, and so on. Data to be accessed by the RCD 110 or processor 101 may be stored in the volatile memory chip 122 by a migration operation. Thus, the RCD 110 or the processor 101 can access the volatile memory chip 122, thereby making it possible to improve performance and increase memory capacity.
Fig. 5 is a block diagram illustrating a memory package such as that shown in fig. 2 according to another embodiment of the inventive concept. Fig. 6 is a perspective view illustrating the memory package shown in fig. 5. Referring to fig. 5 and 6, the memory package 120 ' may include a logic chip 121 ', a volatile memory chip 122 ', and first to third nonvolatile memory chips 123a ' to 123c '. The logic chip, the volatile memory chip, and the first to third nonvolatile memory chips are described with reference to fig. 3 and 4, and thus detailed descriptions that the memory package 120 ' may include the logic chip 121 ', the volatile memory chip 122 ', and the first to third nonvolatile memory chips 123a ' to 123c ' may be omitted.
The logic chip 121 'and the volatile memory chip 122' may be stacked in a third direction perpendicular to a plane defined along the first and second directions (refer to fig. 6), and may be connected to each other through the first set of through-substrate vias TSV 1. In some embodiments, the first direction and the second direction may be directions in which memory cells of the memory chip are arranged. The first to third nonvolatile memory chips 123a 'to 123 c' may be stacked in a direction perpendicular to a plane defined along the row and column directions and may be connected to each other through the second group of through substrate vias.
Thus, the logic chip 121 ', the volatile memory chip 122', and the first to third nonvolatile memory chips 123a 'to 123 c' may be stacked on different regions from each other such that they are horizontally separated from each other. However, they may be part of the same package, as they share the package substrate and may be covered by the same insulating encapsulant. The logic chip 121 'and the first to third nonvolatile memory chips 123 a' to 123c 'may be connected to each other through a separate migration channel MC'. In an example embodiment, the migration channel MC' may be a separate signal line (e.g., a wire included in the package substrate).
Embodiments regarding the structure of a memory package are described with reference to fig. 3-6, although the scope and spirit of the present inventive concept is not limited thereto. The logic chips, volatile memory chips, and non-volatile memory chips included in the memory package may be stacked or arranged by other methods (e.g., zigzag stacking, mesa (mesa) structure, etc.).
FIG. 7 is a flow chart illustrating exemplary operation of a memory package such as that shown in FIG. 2. Referring to fig. 2 and 7, the memory package 120 may receive a refresh command REF from the RCD 110 at step S110. For example, the RCD 110 may control the memory package 120 based on a predefined communication protocol. In an example embodiment, the predefined communication protocol may be a DRAM-based communication protocol. In example embodiments, the DRAM may periodically perform refresh operations to maintain stored data. The RCD 110 may periodically send a refresh command REF to the memory package 120 to cause the memory package 120 to perform a refresh operation.
In step S120, when a refresh operation is performed in the volatile memory chip in response to the received refresh command REF, the memory package 120 may also perform a migration operation. For example, as described above, the memory package 120 may include the volatile memory chip 122 and the first to third nonvolatile memory chips 123a to 123 c. The memory package 120 may perform a refresh operation in response to the received refresh command REF. The refresh operation may represent an operation for reading data stored in the volatile memory chip 122 and rewriting the read data to refresh memory cells in the volatile memory chip 122 that have stored the data.
When the refresh operation is performed, the memory package 120 may also perform a migration process of data to be migrated among the data stored in the first to third nonvolatile memory chips 123a to 123 c. In example embodiments, the data to be migrated may be data having a high possibility to be accessed by the processor 101, data having an access frequency greater than or equal to a constant level, data that is thermal data, or data having a specific type, among data stored in the first to third nonvolatile memory chips 123a to 123 c. In an example embodiment, the data to be migrated may be determined by the migration management unit MMU of the logic chip 121.
Fig. 8 is a block diagram for describing the operation shown in fig. 7. Unnecessary components describing the operation shown in fig. 7 may be omitted for brevity. Further, it is assumed that the first page data PD1 is data to be migrated as determined by the migration management unit MMU.
Referring to fig. 2, 7 and 8, the memory package 120 may include a logic chip 121, a volatile memory chip 122 and a non-volatile memory chip 123 a. Logic chip 121 may receive a refresh command REF (r) from an external device (e.g., via RCD 110 of memory module 100). In response to the received refresh command REF, the logic chip 121 may control the volatile memory chip 122 to cause the volatile memory chip 122 to perform a refresh operation. The volatile memory chip 122 may perform a refresh operation under the control of the logic chip 121.
When the refresh operation is performed, the logic chip 121 may also read the first page data PD1 (c) from the nonvolatile memory chip 123 a. In an example embodiment, the first page data PD1 may be data selected as data to be migrated by the migration management unit MMU of the logic chip 121. For example, the migration management unit MMU may include information about which data of the non-volatile memory chip 123a are predetermined to be migrated to the volatile memory chip 122, e.g., because they are frequently accessed data.
When performing the refresh operation, in addition to controlling the refresh of the data existing in the volatile memory chip 122, the logic chip 121 may control the volatile memory chip 122 so that the first page data PD1 (e.g., frequently accessed data) read from the nonvolatile memory chip 123a is written to the volatile memory chip 122 ((c)). For example, the volatile memory chip 122 may perform a refresh operation under the control of the logic chip 121. The refresh operation may include reading data of a specific row and rewriting the read data to the same specific row. While performing the rewriting, the logic chip 121 may additionally control the volatile memory chip 122 so that the first page data PD1 is written in the volatile memory chip 122.
In an example embodiment, a specific row may represent a row corresponding to a refresh address. In addition, the migration address of the volatile memory chip 122 may be selected by the logic chip 121 or the volatile memory chip 122. To write the first page data PD1 in the volatile memory chip 122, the logic chip 121 may select the migration address as the address of a row in which data is not stored among a plurality of rows included in the volatile memory chip 122, for example.
As described above, the memory package 120 may perform a migration operation during a refresh operation with respect to the volatile memory chip 122. As a result, since overhead due to the migration operation is reduced, the memory module 100 having an increased capacity can be provided without reducing performance. Thus, a memory module and a memory package with reduced cost and improved performance may be provided.
Fig. 9 is a block diagram illustrating a memory package as shown in fig. 2 according to another embodiment of the inventive concept. Referring to fig. 2 and 9, the memory package 120 ″ may include a logic chip 121 ', a volatile memory chip 122', and first to third nonvolatile memory chips 123a "to 123 c". The logic chip, the volatile memory chip, and the first to third nonvolatile memory chips are described with reference to fig. 3, and thus detailed descriptions of the logic chip 121 ", the volatile memory chip 122", and the first to third nonvolatile memory chips 123a "to 123 c" may be omitted.
In contrast to the memory packages 120 and 120' illustrated in fig. 3 to 6, the memory package 120 ″ shown in fig. 9 may use a data signal line as a migration channel. For example, the logic chip 121 ″ may include a first data signal line DQL1 and a second data signal line DQL 2. In example embodiments, each of the first and second data signal lines DQL1 and DQL2 may include a plurality of signal lines (e.g., a plurality of wires).
The logic chip 121 ″ may use a signal line, which is not used to exchange data with an external device (e.g., the processor 101), among the first and second data signal lines DQL1 and DQL2, as a migration path. For example, logic chip 121 ″ may receive a data signal DQ and a data strobe signal DQS from processor 101 via a first data signal line DQL 1. The logic chip 121 ″ can exchange data from the first to third nonvolatile memory chips 123a ″ to 123c ″ through the second data signal line DQL 2. Therefore, the logic chip 121 ″ can use the second data signal line DQL2 as a migration path.
Fig. 10 is a block diagram illustrating a memory package according to another embodiment of the inventive concept. For the sake of brevity, overlapping description with the above components may be omitted. Referring to fig. 10, the memory package 220 may include a logic chip 221, a volatile memory chip 222, and first to third nonvolatile memory chips 223a to 223 c. As described above, the components of the memory package 220 may be stacked in a direction perpendicular to a plane and may be connected to each other by through-silicon vias TSV. In example embodiments, the through-silicon via TSV may be used as the migration channel MC. The logic chip, the volatile memory chip, and the first to third nonvolatile memory chips are described with reference to fig. 2 to 9, and thus detailed descriptions of the logic chip 221, the volatile memory chip 222, and the first to third nonvolatile memory chips 223a to 223c may be omitted.
The logic chip 221 may include a migration management unit MMU, a non-volatile memory management unit NMU, and an address management unit AMU. The migration management unit MMU is as described above, and thus a detailed description thereof may be omitted.
The nonvolatile memory management unit NMU may be configured to control the first to third nonvolatile memory chips 223a to 223 c. For example, the nonvolatile memory management unit NMU may generate commands, addresses, control signals, and the like for controlling the first to third nonvolatile memory chips 223a to 223 c. The nonvolatile memory management unit NMU may perform an address translation operation, a garbage collection operation, and a wear leveling operation with respect to the first to third nonvolatile memory chips 223a to 223 c. In example embodiments, the nonvolatile memory management unit NMU may control the first to third nonvolatile memory chips 223a to 223c through the through-silicon vias TSV used as the migration channel MC. Alternatively, the nonvolatile memory management unit NMU may control the first to third nonvolatile memory chips 223a to 223c through separate signal lines.
The address management unit AMU may manage addresses of the volatile memory chip 222 and the first to third nonvolatile memory chips 223a to 223 c. For example, the external device (e.g., the processor 101 shown in fig. 1) may recognize the volatile memory chip 222 and the first to third nonvolatile memory chips 223a to 223c in the memory package 220 as one storage area. That is, the external device may recognize the memory package 220 as a working memory. Here, an external device may provide a command CMD and an address ADDR to the RCD 210 to read data written in the memory package 220. The memory package 220 may output data corresponding to the address ADDR under the control of the RCD 210.
In an example embodiment, the external device may not recognize the migration operation of the memory package 220 but may recognize the volatile memory chip 222 and the first to third non-volatile memory chips 223a to 223c as one address area. Accordingly, when data corresponding to the received address ADDR is migrated from the first to third nonvolatile memory chips 223a to 223c to the volatile memory chip 222, a normal operation may not be performed or operation performance may be degraded.
In an example embodiment, receiving an address ADDR corresponding to the migrated data, the address management unit AMU may manage the address to be accessed to the volatile memory chip 222. Accordingly, when accessing migrated data, data may be output from the volatile memory chip 222, and thus, operational performance may be improved.
In an example embodiment, although not shown in fig. 10, the volatile memory chip 222 may receive a command CMD, an address ADDR, and a clock CK from the RCD 210 and may operate in response to the received signals.
Fig. 11 is a block diagram for describing the operation of the memory package shown in fig. 10. In an example embodiment, the operation of the address management unit AMU will be described collectively with reference to fig. 11. For the sake of brevity, components not necessary for describing the operation of the address management unit AMU may be omitted. Further, descriptions about the same components as those described above may be omitted.
Referring to fig. 10 and 11, the memory package 220 may include a logic chip 221, a volatile memory chip 222, and a first nonvolatile memory chip 223 a.
The memory package 220 may receive the first address ADDR1 and may access data corresponding to the received first address ADDR 1. For example, the data corresponding to the first address ADDR1 may be first page data PD 1. The first page data PD1 may be stored in the first nonvolatile memory chip 223 a. Here, the address management unit AMU may provide the first address ADDR1 to the first nonvolatile memory chip 223a so that the first page data PD1 is read from the first nonvolatile memory chip 223 a.
Thereafter, the first page data PD1 stored in the first nonvolatile memory chip 223a may be migrated to the volatile memory chip 222. For example, as described above, the memory package 220 may select the first page data PD1 stored in the first nonvolatile memory chip 223a as the data to be migrated. The memory package 220 may migrate the first page data PD1 stored in the first non-volatile memory chip 223a to the volatile memory chip 222 during a refresh operation.
Here, the address management unit AMU of the memory package 220 may manage an address corresponding to the migrated first page data PD 1. For example, after the migration of the first page data PD1, when receiving the first address ADDR1 corresponding to the migrated first page data PD1, the address management unit AMU may supply the first address ADDR1 to the volatile memory chip 222 so that the first page data PD1 stored in the volatile memory chip 222 is output.
As described above, when migrating a specific page of data, the address management unit AMU may manage or convert the received address so that the specific page of data is output from the volatile memory chip 222.
Fig. 12 is a block diagram illustrating a memory package according to still another embodiment of the inventive concept. Referring to fig. 12, the memory package 320 may include a logic chip 321, a volatile memory chip 322, and first to third nonvolatile memory chips 323a to 323 c. The logic chip 321 may include a migration management unit MMU and a data management unit DMU. The logic chip 321, the volatile memory chip 322, and the first to third nonvolatile memory chips 323a to 323c are described above, and thus detailed descriptions thereof may be omitted.
The data management unit DMU may manage data received from an external device (e.g., a processor). For example, the data management unit DMU may determine the properties of the received data. The data management unit DMU may selectively write data in the volatile memory chip 322 or the first to third nonvolatile memory chips 323a to 323c based on the determined attribute.
For example, when the received data is thermal data, the data management unit DMU may set an address so that the received data is written in the volatile memory chip 322. Alternatively, when the received data is cold data, the data management unit DMU may set an address such that the received data is written in the first to third nonvolatile memory chips 323a to 323 c. In an example embodiment, the data management unit DMU may determine whether the received data is hot data or cold data based on a data size, a type of data, header information of the data, and the like.
Fig. 13 is a flowchart for describing the operation of the data management unit DMU shown in fig. 12. Referring to fig. 12 and 13, the data management unit DMU may receive data from an external device (e.g., a processor) at step S210. For example, as described above, the data management unit DMU may receive data from an external device through the data signal DQ and the data strobe signal DQs.
In step S220, the data management unit DMU may determine the attributes of the received data. For example, the data management unit DMU may determine whether the received data is hot data or cold data based on the data size, the type of data, header information of the data, and the like.
In step S230, the data management unit DMU may store the received data in the volatile memory chip or the nonvolatile memory chip based on the determined result. For example, when the received data is thermal data, the data management unit DMU may convert an address corresponding to the received data so that the received data is written in the volatile memory chip 322. When the received data is cold data, the data management unit DMU may convert an address corresponding to the received data so that the received data is written in the first to third nonvolatile memory chips 323a to 323 c. In an example embodiment, although not shown in fig. 13, the translated address may be managed by the address management unit AMU described with reference to fig. 10.
In an example embodiment, the data management unit DMU may manage thermal data of data stored in the nonvolatile memory chip. For example, the data stored in the non-volatile memory chip may be cold data. However, data whose type is changed to thermal data may exist among data stored in the nonvolatile memory chip based on the access frequency to the memory package. Here, the data management unit DMU may manage access to the nonvolatile memory chip and may determine data whose type is changed to hot data from among data stored in the nonvolatile memory chip. In example embodiments, data, of which the type is changed to hot data, among data stored in the nonvolatile memory chip may be migrated to the volatile memory chip through a migration operation.
As described above, the memory package may store the received data in the volatile memory chip or the non-volatile memory chip based on the attributes of the received data. That is, hot data whose access frequency is high may be stored in a volatile memory chip having a fast operation speed, and cold data whose access frequency is low may be stored in a non-volatile memory chip having a relatively slow operation speed, thereby maintaining the access speed and increasing the available memory capacity.
Fig. 14 is a block diagram illustrating a user system according to still another embodiment of the inventive concept. Referring to fig. 14, the user system 40 may include a processor 401 and a memory module 400. The processor 401 may include a memory controller 401 a. The memory controller 401a may be configured to control the memory module 400. For example, the memory controller 401a may transmit an address ADDR, a command CMD, and a clock CK for controlling the memory module 400 to the memory module 400. The memory controller 401a may exchange data with the memory module 400 through a data signal DQ and a data strobe signal DQs.
The memory module 400 may include an RCD410 and a memory package 420. The RCD410 and the memory package 420 are described above, and thus detailed descriptions thereof may be omitted. In an example embodiment, the RCD410 as shown in fig. 14 may include the migration management unit MMU, the address management unit AMU, the data management unit DMU, or the nonvolatile memory management unit NMU described above.
For example, the memory packages described with reference to fig. 1 to 13 may operate under the control of a logic chip including a migration management unit MMU, an address management unit AMU, a data management unit DMU or a non-volatile memory management unit NMU.
However, the RCD410 shown in fig. 14 may include a migration management unit MMU, an address management unit AMU, a data management unit DMU, or a nonvolatile memory management unit NMU, may control the migration operation, the address translation operation, and the data management operation of the memory package described above, and may generate various types of control signals for controlling the nonvolatile memory chip. That is, the memory package 420 may include a volatile memory chip and a non-volatile memory chip, and may operate under the control of the RCD 410.
In an example embodiment, the memory controller 401a may include a translation lookaside buffer TLB. The translation lookaside buffer TLB may include address information or index information regarding data stored in the memory module 400. For example, the processor 401 may scan a translation lookaside buffer TLB to determine whether data to be accessed is in the memory module 400. When the data to be accessed is not in the memory module 400, the processor 401 may read the data to be accessed from other storage media. When data to be accessed is in the memory module 400, the memory controller 401a may provide a corresponding address ADDR to the memory module 400. The memory module 400 may output data corresponding to the received address ADDR.
In an example embodiment, when a migration operation is performed in the memory package 420 of the memory module 400, the translation lookaside buffer TLB may be updated based on the data migration results. For example, when the first page of data is migrated from the non-volatile memory device to the volatile memory device, the memory module 400 may update the translation lookaside buffer TLB such that the first page of data corresponds to the volatile memory device.
In an example embodiment, a portion (e.g., a Most Significant Bit (MSB)) of one or more bits of the address ADDR selected by the translation lookaside buffer TLB may be information for indicating at least one of a volatile memory chip and a non-volatile memory chip in the memory package 420. Here, the RCD410 may control at least one of the volatile memory chip and the non-volatile memory chip in the memory package 420 based on the MSB of the address ADDR.
In an example embodiment, in fig. 14, the RCD410 may include a migration management unit MMU, an address management unit AMU, a data management unit DMU, or a nonvolatile memory management unit NMU. For example, the migration management unit MMU, the address management unit AMU, the data management unit DMU and the nonvolatile memory management unit NMU may be included in the processor 401, the memory controller 401a, the RCD410 and the memory package 420, respectively, or may be implemented in separate control circuits.
Fig. 15 is a block diagram exemplarily illustrating a user system according to still another embodiment of the inventive concept. Referring to fig. 15, the user system 50 may include a processor 501 and a memory module 500. The processor 501 may include a memory controller 501 a. The memory module 500 may include an RCD 510 and a memory package 520. The processor 501, the memory controller 501a, the memory module 500, the RCD 510, and the memory package 520 are described above, and thus detailed descriptions thereof may be omitted.
The memory package 520 may output the wait signal WS to the RCD 510. The wait signal WS may be a signal for indicating that the memory package 520 is ready for access. For example, as described above, the memory package 520 may include a volatile memory chip and a non-volatile memory chip. The access speed or operating speed of the non-volatile memory chip may be slower than that of the volatile memory chip. The RCD 510 may control the memory package 520 based on a predefined communication protocol. In an example embodiment, the predefined communication protocol may be a volatile memory chip based communication protocol. That is, when a nonvolatile memory chip having a slow operation speed is accessed, the memory module cannot normally operate.
When performing an access to the nonvolatile memory chip, the memory package 520 may transmit a wait signal WS, which is a signal for indicating that the nonvolatile memory chip is ready for access, to the RCD 510. The RCD 510 may access the nonvolatile memory chip included in the memory package 520 in response to the wait signal WS. In an example embodiment, the RCD 510 may provide the wait signal WS to the memory controller 501 a. The memory controller 501a may access the memory module 500 in response to the wait signal WS.
In an example embodiment, the memory controller 501a of the processor 501 may identify the memory module 500 as an address region. For example, the memory controller 501a of the processor 501 may include a volatile memory chip and a non-volatile memory chip. The memory controller 501a can manage the volatile memory chip and the nonvolatile memory chip as one address area without distinguishing between the volatile memory chip and the nonvolatile memory chip. Here, the processor 501 may not recognize that data to be accessed is stored in a volatile memory device or a non-volatile memory device. That is, the processor 501 may not normally control the memory module 500.
When accessing the nonvolatile memory chip, the memory module 500 according to the embodiment may provide the wait signal WS to the processor 501 and may notify that the processor 501 is notified that the access to the nonvolatile memory chip is ready. The processor 501 may normally access data stored in the nonvolatile memory chip in response to the wait signal WS.
As described above, the memory package of the memory module according to an embodiment of the inventive concept may migrate data from the nonvolatile memory chip to the volatile memory chip during a refresh operation. In addition, the memory package may include a volatile memory chip and a non-volatile memory chip stacked, and may perform a migration operation through the through-silicon via TSV. The memory package may manage the migrated addresses. The memory package may manage the received data. As described above, according to embodiments of the inventive concept, a memory module having an increased storage capacity and improved performance may be provided.
In an example embodiment, each of the migration management unit MMU, the address management unit AMU, the data management unit DMU or the non-volatile memory management unit NMU may be implemented in hardware or software.
Fig. 16 is a block diagram exemplarily illustrating a volatile memory chip as shown in fig. 3. In an example embodiment, the volatile memory chips 122 are assumed to be, but not limited to, DRAMs.
Referring to fig. 16, the volatile memory chip 122 may include a memory cell array 122_1, an address buffer 122_2, an X-decoder 122_3, a Y-decoder 122_4, and a sense amplifier and write driver block 122_ 5.
The memory cell array 122_1 may include a plurality of memory cells. The memory cells may be respectively arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL. The memory cells may be connected to word lines WL and bit lines BL. Each of the memory cells may include a capacitor and a transistor.
The address buffer 122_2 may receive an address ADDR from an external device (e.g., a logic chip or an RCD), and may buffer the received address ADDR. The address buffer 122_2 may provide the received address ADDR to the X-decoder 122_3 or the Y-decoder 122_ 4.
The X-decoder 122_3 may receive a row control command RAS from an external device (e.g., a logic chip or an RCD), and may activate at least one word line in response to the received signal. In an example embodiment, the X-decoder 122_3 may receive a row address (ADDR _ row) from the address buffer 122_2, and the activated word line may be a word line corresponding to the received row address.
The Y-decoder 122_4 may receive a column control command RAS from an external device (e.g., a logic chip or an RCD), and may activate at least one bit line in response to the received signal. In an example embodiment, the Y-decoder 122_4 may receive a column address (ADDR _ col) from the address buffer 122_2, and the activated bit line may be a bit line corresponding to the received column address.
The sense amplifier and write driver block 122_5 may be connected to the Y-decoder 122_4 through a plurality of data lines DL. The sense amplifier and write driver block 122_5 may sense (or detect) fluctuations in the voltage of the data lines DL to amplify and output the fluctuations in the voltage, or may control the voltage of the data lines DL based on data received through the data signal DQ and the data strobe signal DQs.
Fig. 17 is a block diagram exemplarily illustrating a first nonvolatile memory chip of the nonvolatile memory chips shown in fig. 3. Referring to fig. 17, the first nonvolatile memory chip 123a may include a memory cell array 123a _1, an address decoder 123a _2, a control circuit 123a _3, a page buffer 123a _4, and an input/output circuit 123a _ 5.
The memory cell array 123a _1 may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings, and each cell string may include a plurality of memory cells. The memory cells may be connected to a plurality of word lines WL. The memory cells may be arranged in a row direction and a column direction and each page may be composed of memory cells.
The address decoder 123a _2 may be connected to the memory cell array 123a _1 through a string selection line SSL, a word line WL, and a ground selection line GSL. The address decoder 123a _2 may receive an address ADDR _ n from an external device (e.g., a logic chip or an RCD), and may decode the received address ADDR _ n. The address decoder 123a _2 may select at least one word line WL based on the decoded address and may control the selected word line. In an example embodiment, the address ADDR _ n may be an address corresponding to the nonvolatile memory chip 123 a. The address ADDR _ n may be an address converted by the address management unit AMU (refer to fig. 10).
The control circuit 123a _3 may receive a command CMD _ n and a control signal CTRL from an external device (e.g., a logic chip or an RCD), and may control the address decoder 123a _2, the page buffer 123a _4, and the input/output circuit 123a _5 in response to the received signals. In example embodiments, logic chip 121 may provide a command CMD _ n corresponding to the command and a control signal CTRL to nonvolatile memory device NVM in response to command CMD _ n from processor 101.
The page buffer 123a _4 may be connected to the memory cell array 123a _1 through a plurality of bit lines BL, and may be connected to the input/output circuit 123a _5 through a plurality of data lines DL. The page buffer 123a _4 may control the bit lines BL under the control of the control circuit 123a _3 so that data received from the input/output circuit 123a _5 through the data lines DL is stored in the memory cell array 123a _ 1. The page buffer 123a _4 can read data stored in the memory cell array 123a _1 under the control of the control circuit 123a _ 3.
The input/output circuit 123a _5 can exchange data with an external device (e.g., a logic chip or a processor).
In an example embodiment of the inventive concept, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells having an active area disposed above a silicon substrate and circuitry associated with operation of those memory cells, whether such associated circuitry is on or within such substrate. The term "monolithic" refers to the deposition of layers of each stage of the array directly over layers of each lower stage of the array.
In example embodiments of the present inventive concept, a 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge well layer. Each vertical NAND string can include at least one select transistor located above a memory cell, the at least one select transistor having the same structure as the memory cell and being monolithically formed with the memory cell.
The following patent documents, incorporated herein by reference, describe suitable configurations of three-dimensional memory arrays configured as a plurality of levels with word lines and/or bit lines shared between the levels: U.S. patent nos. 7,679,133; no.8,553,466; no.8,654,587; no.8,559,235 and U.S. patent publication No. 2011/0233648.
Fig. 18 is a block diagram illustrating a memory module according to an embodiment of the inventive concept. In an example embodiment, a memory module 1000 as shown in FIG. 18 may have a Load Reducing Dual Inline Memory Module (LRDIMM) configuration. A memory module 1000, as shown in fig. 18, may be mounted on a DIMM socket and may communicate with a processor.
Referring to FIG. 18, a memory module 1000 may include an RCD 1100, an SPD 1200, a plurality of memory packages 1310-1380, and a plurality of data buffers 1410-1480. In an example embodiment, the RCD, SPD, and memory package are described with reference to fig. 1 to 16, and thus detailed descriptions of the RCD 1100, SPD 1200, and memory packages 1310 to 1380 may be omitted.
Each of the data buffers 1410 through 1480 may be configured to exchange a data signal DQ and a data strobe signal DQs with an external device (e.g., a processor). In addition, the data buffers 1410 to 1480 may be configured to exchange data signals DQ and data strobe signals DQs with the memory packages 1310 to 1380, respectively.
In an example embodiment, each of the memory packages 1310 through 1380 described above may be hybrid memory packages. Further, each of the memory packages 1310 to 1380 may operate according to the operation method described with reference to fig. 1 to 18.
Fig. 19 is a block diagram illustrating a memory module according to another embodiment of the inventive concept. In an example embodiment, the memory module 2000 as shown in FIG. 19 may have a structure of a Register Dual Inline Memory Module (RDIMM). A memory module 2000, as shown in fig. 19, may be mounted on a DIMM socket and may communicate with the processor.
Referring to FIG. 19, a memory module 2000 may include an RCD 2100, an SPD 2200, and a plurality of memory packages 2310 through 2380. In contrast to the memory module 1000 shown in FIG. 18, the memory module 2000 shown in FIG. 19 may not include a data buffer. Each of the memory packages 2310 through 2380 may directly communicate with an external device (e.g., a processor) through a data signal DQ and a data strobe signal DQs.
In an example embodiment, each of the memory packages 2310 through 2380 as described above may be a hybrid memory package and may operate according to the operating method described with reference to fig. 1 through 16.
Fig. 20 is a diagram exemplarily illustrating a server system including a memory module according to an embodiment of the inventive concept. Referring to fig. 20, a server system 3000 may include a plurality of server racks 3100. Each of the server racks 3100 may include a plurality of memory modules 3200. The memory modules 3200 may be directly connected to processors respectively included in the server racks 3100. For example, memory module 3200 may be in the form of a dual in-line memory module, may be mounted in a DIMM socket that is electrically connected to the processor, and may communicate with the processor. In an example embodiment, the memory module 3200 may be used as a storage device or an operating memory of the server system 3000. In an example embodiment, the memory module 3200 may operate according to the method described with reference to fig. 1 to 19.
Fig. 21 is a block diagram illustrating an electronic system including a memory module or a memory package according to an embodiment of the inventive concept. Electronic system 4000 may be implemented in a data processing device capable of using or supporting an interface provided by the Mobile Industry Processor Interface (MIPI) alliance. For example, the electronic system 4000 may be implemented in a portable communication terminal, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a smart phone, or a wearable device.
The electronic system 4000 may include an application processor 4100, a display 4220, and an image sensor 4230. The application processor 4100 may include a DigRF master 4110, a Display Serial Interface (DSI) host 4120, a Camera Serial Interface (CSI) host 4130, and a physical layer (PHY) 4140.
DSI host 4120 may communicate with DSI device 4225 of display 4220 through DSI. For example, the optical serializer SER may be implemented in the DSI host 4120 and the optical deserializer DES may be implemented in the DSI device 4225.
The CSI host 4130 may communicate with the CSI device 4235 of the image sensor 4230 through CSI. For example, the optical deserializer may be implemented in the CSI host 4130 and the optical serializer may be implemented in the CSI device 4235.
DSI and CSI may use the physical layer and the link layer. DSI and CSI may be applied to embodiments of the inventive concept. For example, DSI host 4120 and DSI device 4225 may selectively extract error logs through peer-to-peer (P2P) communication between the physical layer and the link layer. Alternatively, CSI device 4235 and CSI host 4130 may selectively extract the error log through P2P communication between the physical layer and the link layer.
The electronic system 4000 may further include a Radio Frequency (RF) chip 4240 for communicating with the application processor 4100. RF chip 4240 may include a physical layer (PHY)4242, a DigRF slave 4244, and an antenna 4246. For example, the physical layer 4242 of the RF chip 4240 and the physical layer 4140 of the application processor 4100 may exchange data with each other through a DigRF interface provided by the MIPI alliance.
The electronic system 4000 may further include a working memory 4250 and an embedded/card storage device 4255. The working memory 4250 and the embedded/card storage 4255 may store data received from the application processor 4100. Further, the working memory 4250 and the embedded/card storage 4255 may provide data stored therein to the application processor 4100. In an example embodiment, the working memory 4250 may be the memory module described with reference to fig. 1 to 20. In an example embodiment, the working memory 4250 may include a plurality of memory packages, and each memory package may include a volatile memory chip and a non-volatile memory chip. Each memory package may perform a migration operation during a refresh operation.
The working memory 4250 may temporarily store data that has been or will be processed by the application processor 4100. The working memory 4250 may include volatile memory chips such as SRAM, DRAM, SDRAM, and the like, and nonvolatile memory chips such as flash memory, PRAM, MRAM, ReRAM, FRAM, and the like.
The embedded/card storage 4255 may store data regardless of power. In an example embodiment, the embedded/card storage device 4255 may operate in accordance with a Universal Flash Storage (UFS) interface protocol, but is not limited thereto. The embedded/card storage 4255 may include the non-volatile memory devices described with reference to fig. 1-20. The nonvolatile memory device included in the embedded/card storage 4255 may perform a programming operation based on the program success/failure determination method described with reference to fig. 1 to 20.
The electronic system 4000 may communicate with external systems through Worldwide Interoperability for Microwave Access (WiMAX)4260, Wireless Local Area Network (WLAN)4262, Ultra Wide Band (UWB)4264, and the like.
The electronic system 4000 may further include a speaker 4270 and a microphone 4275 for processing voice information. The electronic system 4000 may further include a Global Positioning System (GPS) device 4280 for processing the location information. The electronic system 4000 may further include a bridge chip 4290 for managing connections between peripheral devices.
While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, it should be understood that the above embodiments are not limiting, but illustrative.
Embodiments of the inventive concept may provide a memory package, a memory module having the same, and an operating method thereof, which have increased storage capacity and improved performance.

Claims (20)

1. A memory package, comprising:
a non-volatile memory chip;
a volatile memory chip having an access speed faster than an access speed of the non-volatile memory chip; and
a logic chip configured to perform a refresh operation with respect to the volatile memory chip in response to a refresh command from an external device, and to migrate at least a portion of data stored in the non-volatile memory chip to the volatile memory chip when the refresh operation is performed,
wherein all refresh operations and migrating at least a portion of data stored in the non-volatile memory chip to the volatile memory chip are both performed in response to the refresh command.
2. The memory package of claim 1, wherein the logic chip performs migration operations through a separate migration-specific channel.
3. The memory package of claim 1, wherein the non-volatile memory chip and the volatile memory chip are stacked in a direction perpendicular to the logic chip, and
wherein the non-volatile memory chip, the volatile memory chip, and the logic chip are connected to each other by through-silicon vias.
4. The memory package of claim 3, wherein the logic chip performs a migration operation through a through silicon via.
5. The memory package of claim 1, wherein the logic chip determines data to be migrated among data stored in the non-volatile memory chip.
6. The memory package of claim 5, wherein the data to be migrated is data whose access frequency is higher than a constant level.
7. The memory package of claim 1, wherein the logic chip comprises:
a non-volatile memory management unit configured to perform a garbage collection operation and a wear leveling operation with respect to the non-volatile memory chip.
8. The memory package of claim 1, wherein the logic chip comprises:
an address management unit configured to manage addresses of the nonvolatile memory chip and the volatile memory chip so that data corresponding to the address received from the external device is output.
9. The memory package of claim 8, wherein when data corresponding to the received address is stored in the volatile memory chip, the address management unit translates the received address so that the data stored in the volatile memory chip is output.
10. The memory package of claim 1, wherein the logic chip sends a wait signal to the external device as a signal to indicate that the non-volatile memory chip is ready to access when the non-volatile memory chip is accessed.
11. The memory package of claim 1, wherein the memory package communicates with the external device based on a Double Data Rate (DDR) interface.
12. A memory module, comprising:
a memory package including a volatile memory chip and a non-volatile memory chip; and
a random access memory, RAM, control means configured to control the memory package under control of an external device, and to periodically send refresh commands to said memory package,
wherein the memory package performs a refresh operation with respect to the volatile memory chip in response to a refresh command and migrates at least a portion of data stored in the non-volatile memory chip to the volatile memory chip during the refresh operation,
wherein all refresh operations and migrating at least a portion of data stored in the non-volatile memory chip to the volatile memory chip are both performed in response to the refresh command.
13. The memory module of claim 12, wherein the memory package includes a plurality of data signal lines, an
Wherein the memory package exchanges data with an external device through a portion of the data signal line, and migrates at least a portion of the data stored in the non-volatile memory chip to the volatile memory chip through a remaining portion of the data signal line.
14. The memory module of claim 12, wherein the memory package further comprises:
a logic chip configured to control the volatile memory chip and the non-volatile memory chip under the control of the RAM control device.
15. The memory module of claim 14, wherein the volatile memory chip and the non-volatile memory chip are stacked in a direction perpendicular to the logic chip, and the non-volatile memory chip, the volatile memory chip, and the logic chip are connected to each other by through silicon vias.
16. The memory module of claim 15, wherein the memory package migrates at least a portion of the data stored in the non-volatile memory chip to the volatile memory chip by through silicon vias.
17. The memory module of claim 12, wherein the volatile memory chip is a Dynamic Random Access Memory (DRAM) and the non-volatile memory chip is a NAND flash memory.
18. The memory module of claim 17, wherein the non-volatile memory chip comprises a three-dimensional (3D) memory array.
19. The memory module of claim 12, further comprising a serial presence detect chip that includes device information about the memory module.
20. A method of operating a memory package is provided,
wherein the memory package includes a volatile memory chip and a non-volatile memory chip,
the operation method comprises the following steps:
receiving a refresh command from an external device; and
migrating at least a portion of data stored in a non-volatile memory chip to a volatile memory chip upon a refresh operation performed on the volatile memory chip in response to a refresh command,
wherein all refresh operations and migrating at least a portion of data stored in the non-volatile memory chip to the volatile memory chip are both performed in response to the refresh command.
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102353859B1 (en) * 2017-11-01 2022-01-19 삼성전자주식회사 Computing device and non-volatile dual in-line memory module
CN108962301B (en) * 2018-05-24 2022-04-12 济南德欧雅安全技术有限公司 Storage device
CN108665936B (en) * 2018-07-11 2024-03-26 长鑫存储技术有限公司 Systematic packaging aggregate
KR102565904B1 (en) * 2018-07-17 2023-08-11 에스케이하이닉스 주식회사 Memory device and memory system having the same
US10586592B1 (en) 2018-08-23 2020-03-10 Micron Technology, Inc. Disturb management based on write times
EP3839954A4 (en) * 2018-10-16 2021-08-25 Huawei Technologies Co., Ltd. Hybrid storage device and access method
CN109656748B (en) * 2018-12-10 2020-05-19 华中科技大学 Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement
US10770431B1 (en) * 2019-02-27 2020-09-08 Western Digital Technologies, Inc. Memory die layouts for failure protection in SSDs
CN110096366B (en) * 2019-05-10 2022-03-04 苏州浪潮智能科技有限公司 Configuration method and device of heterogeneous memory system and server
EP4002471A1 (en) * 2020-11-12 2022-05-25 Commissariat à l'Energie Atomique et aux Energies Alternatives Hybrid resistive memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281494A (en) * 2002-09-11 2008-10-08 株式会社日立制作所 System and method for using dynamic random access memory and flash memory
CN101960430A (en) * 2007-07-25 2011-01-26 技佳科技有限公司 Hybrid nonvolatile memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070136523A1 (en) * 2005-12-08 2007-06-14 Bonella Randy M Advanced dynamic disk memory module special operations
US20090193186A1 (en) * 2008-01-25 2009-07-30 Barth Jr John E Embedded dram having multi-use refresh cycles
US7983107B2 (en) * 2009-02-11 2011-07-19 Stec, Inc. Flash backed DRAM module with a selectable number of flash chips
KR20130033230A (en) * 2011-09-26 2013-04-03 삼성전자주식회사 Hybrid memory device, system including the same, and method of reading and writing data in the hybrid memory device
US9535831B2 (en) * 2014-01-10 2017-01-03 Advanced Micro Devices, Inc. Page migration in a 3D stacked hybrid memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281494A (en) * 2002-09-11 2008-10-08 株式会社日立制作所 System and method for using dynamic random access memory and flash memory
CN101960430A (en) * 2007-07-25 2011-01-26 技佳科技有限公司 Hybrid nonvolatile memory

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