CN109656748B - Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement - Google Patents
Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement Download PDFInfo
- Publication number
- CN109656748B CN109656748B CN201811506261.5A CN201811506261A CN109656748B CN 109656748 B CN109656748 B CN 109656748B CN 201811506261 A CN201811506261 A CN 201811506261A CN 109656748 B CN109656748 B CN 109656748B
- Authority
- CN
- China
- Prior art keywords
- data
- original data
- flash memory
- proportion
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a method for reducing the error rate of an MLC NAND flash memory through data pattern rearrangement, which comprises the following steps: obtaining the proportion of '1' and the cold and hot degree of the original data; and according to the '1' proportion and the cold and hot degree of the original data, the original data to be written into the LSB page or the MSB page of the MLC NAND flash memory is inverted, and the data mode is rearranged. The invention fully considers the influence of each state of the MLC on the error rate, provides five different data mode re-layout modes according to different proportions and cold and hot degrees of '1' in original data, and overturns the data to be written into the low page or the high page of the multi-layer flash memory under specific conditions. Because the Flash memory errors and the states of the Flash memory are closely related in the MLC NAND Flash, the data mode is rearranged based on the error tendency of each state, and the two errors of programming interference and retention errors can be effectively reduced, so that the error probability of the data in the Flash memory is reduced.
Description
Technical Field
The invention belongs to the technical field of solid-state storage, and particularly relates to a method for reducing the error rate of an MLCNAND flash memory through data pattern rearrangement.
Background
With the development of technology, the process size of the NAND flash memory is continuously reduced, the storage density is increased, the reliability and durability of the flash memory are lower and lower, and the bit error rate is higher and higher. The types of errors in the flash memory are mainly classified into program interference Error (program interference Error), Retention Error (Retention Error), Read Error (Read Error), and Erase Error (Erase Error). The research shows that: the most severe impact on flash reliability is data retention errors and program disturb is second. The hot data that is frequently read and written in the flash memory is mainly affected by program disturb, while the cold data that is updated less frequently is mainly affected by program disturb and retention errors. As the retention time of data in flash memory increases, the interference caused by retention errors becomes more and more serious, and becomes a major source of data errors in flash memory. Program disturb errors are mainly caused by excessive electron injection into the memory cell during programming, which results in a right shift of the threshold voltage distribution. Since a higher programming voltage more readily attracts additional electrons to the floating gate, programming a cell with a higher threshold voltage causes more program disturb to adjacent cells. The retention error is mainly caused by electron leakage in the memory cell, which causes the threshold voltage distribution to shift left, and the more the number of electrons in the memory cell is, the more the electron leakage is easily caused, so the retention error is more easily caused in the state with higher threshold voltage. In addition, since these two errors cause the threshold voltage to move in opposite directions, their effects are partially cancelled.
As shown in fig. 1, in an MLC (Multi-Level-Cell) NAND flash memory, one memory Cell can store 2-bit data, and the memory Cell can be divided into four states of "11", "10", "00", and "01" according to the magnitude of the threshold voltage of the memory Cell. The two bits of each state belong to two different pages, the left side being called LSB (Least Significant Bit), and belonging to the lower page (LSB page); the right side is called MSB (Most Significant Bit) and belongs to the upper page (MSB page). According to the analysis of the source of the program disturbance and the retention error in the NAND Flash, if the number of the memory cells in a higher threshold voltage state is reduced, the phenomena of electron injection and leakage in the memory cells can be effectively inhibited, so that the program disturbance and the retention error are reduced. In particular, for MLC NAND Flash, the erase state "11" has the lowest threshold voltage among the four states, and thus, increasing the number of memory cells in the "11" state can more effectively reduce the two errors.
In order to ensure the reliability of the NAND flash memory, the error rate can be inhibited by depending on the error characteristics of the NAND flash memory from the aspect of not depending on an error correcting code, so that the original error rate of data in the flash memory is reduced. In the prior art, Guo J et al propose a DPA (Data Pattern Aware) scheme, which uses decorrelation and scrambling techniques on preprocessed Data to finally increase the proportion of "1" in the original Data. However, when the pre-and post-correlation of the data to be processed is weak, the DPA will bring extra power consumption and data throughput delay. An Asymmetric Coding (AC) scheme adopted by Doi M et al intercepts a segment from a data stream to be programmed to determine the proportion of "0" to "1", performs bit flipping on the data if the proportion of "0" is higher than the proportion of "1", attaches a flipping flag bit "1" to the data segment, and then stores the data segment, otherwise does not perform flipping and stores the flag bit "0". The AC scheme can effectively reduce the original bit error rate, however, the introduction of the flip flag bit may bring a large space overhead, may also cause misalignment between the data width and the page width, and may aggravate the write amplification of the flash memory. Wei D et al propose a Nibble Remapping (NRC) method to increase the ratio of "1" in the original data stream, first perform frequency statistics on the nibbles, and then sequentially map according to the frequency, so that more memory cells are in the "11" state of the lowest threshold voltage to reduce program disturb errors and retention errors. However, performing nibble frequency statistics on the data stream may cause a large overhead, and an access to the memory mapping table may cause an additional delay.
The above method increases the proportion of the "11" state by encoding more "1" writes, thereby reducing program disturb and retention errors. However, these methods directly increase the proportion of "1" in the original data, so as to increase the proportion of "11" state which does not cause program disturb and retains the minimum error, however, the influence of the other three states ("10", "00", "01") in the flash memory on the error rate is not negligible. Furthermore, they do not consider the counteracting effect between program disturb and retention errors.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to solve the technical problem of low reliability of the NAND flash memory caused by high error rate of the error suppression method in the prior art.
To achieve the above object, in a first aspect, an embodiment of the present invention provides a method for reducing the bit error rate of an MLC NAND flash memory by data pattern re-layout, where the method includes the following steps:
s1, obtaining the proportion of '1' and the cold and hot degree of original data;
and S2, according to the proportion of '1' of the original data and the cold and hot degree, the original data to be written into the LSB page or the MSB page of the MLC NAND flash memory is overturned, and the data mode is rearranged.
Specifically, the original data is data to be written in MLC NAND Flash.
Specifically, the step S2 includes the steps of:
s201, classifying the original data according to the proportion of '1' of the original data and the cold and hot degree, and if the proportion of '1' of the original data is less than 50% and the original data is hot data, entering the step S202; if the "1" ratio of the original data is greater than 50% and the data is thermal data, go to step S203; if the proportion of "1" of the original data is less than 50% and the data is cold data, go to step S204; if the "1" ratio of the original data is greater than 50% and the data is cold data, go to step S205; if the "1" ratio of the original data is 50%, the process proceeds to step S206;
s202, turning over the original data for two times: during the first inversion, the data to be written into the LSB page is inverted, and during the second inversion, when the LSB is '1', the data to be written into the MSB page is inverted;
s203, turning the original data for one time: when the LSB is "0", the data to be written to the MSB page is flipped;
s204, turning the original data for one time: flipping data to be written to the LSB page;
s205, turning over the original data for one time: flipping the data to be written to the MSB page;
s206, no processing is carried out on the original data.
Specifically, the proportion of "1" in the original data is statistically obtained before the entire original data is written.
Specifically, the cold and hot levels of the original data are determined according to the erase and write cycles and the retention time.
In a second aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method for reducing the error rate of the mlc nand flash memory according to the first aspect is implemented.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
the invention fully considers the influence of each state of the MLC on the error rate, provides five different data mode re-layout modes according to different proportions and cold and hot degrees of '1' in original data, and overturns the data to be written into the low page or the high page of the multi-layer flash memory under specific conditions. Because the Flash memory errors and the states of the Flash memory are closely related in the MLC NAND Flash, the data mode is rearranged based on the error tendency of each state, and the two errors of programming interference and retention errors can be effectively reduced, so that the error probability of the data in the Flash memory is reduced.
Drawings
FIG. 1 is a schematic diagram of a threshold voltage distribution model of an MLC NAND Flash memory cell in the prior art;
FIG. 2 is a flowchart of a method for reducing the bit error rate of MLC NAND flash memory by data pattern re-layout according to an embodiment of the present invention;
FIG. 3 is a system structure diagram of a data pattern re-layout method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a processing method H0 for thermal data with a proportion of "1" less than 50% according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a processing method H1 for thermal data with a proportion of "1" greater than 50% according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a processing method C0 for cold data with a proportion of "1" less than 50% according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a processing manner C1 of cold data with a proportion of "1" greater than 50% according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
First, some terms used in the present invention are explained.
Thermal data: data that is more frequent is erased early in the life cycle of the flash memory.
Cold data: data with longer time is retained at the end of the life cycle of the flash memory.
Data mode: the proportionality of the four data states ("11", "10", "00", and "01").
A typical storage system typically contains operating system files, multimedia files, office files, and the like. dll files are the file types of the operating systems occupying the largest data volume in the common Windows operating systems (Windows XP-Windows 10), jpg and mp3 files are the most common multimedia file types, doc, ppt and pdf files are typical office files, and eml files are mail file types and are frequently used in daily office work. By counting the proportion of 1 in the data of the 7 common file types, the proportion of 1 in most files is less than 50%, and particularly, the proportion of 1 in system files is very low and accounts for about 20-35%. Based on the data characteristic, the invention provides a strategy for rearranging the data mode based on the error difference of cold and hot data, and the error rate is restrained by depending on the self characteristic of the flash memory, so that the reliability of the flash memory is improved.
The invention conception of the invention is as follows: by utilizing the characteristics of programming interference error and data retention error of a multi-level Flash memory (MLC NAND Flash) unit and the characteristics of file data in a storage system, five different data mode re-layout methods are respectively provided according to different proportions of '1' in the data and different cold and hot degrees of the data. Specifically, the invention overturns the data to be written into the lower page or the upper page of the multi-layer flash memory under specific conditions, thereby realizing the re-layout of the data mode and reducing the error probability of the data in the flash memory by reducing retention errors or programming interference. The technical scheme of the invention belongs to the category of error suppression without depending on error correction coding, and can suppress flash memory errors through simple hardware logic, reduce the original error rate and improve the reliability of the flash memory.
As shown in fig. 2, the data pattern rearrangement is divided into five types according to the difference between the cold and hot degrees of the original data and the proportion of "1" in the original data, which are respectively: the processing method H0 for hot data with a ratio of "1" less than 50%, the processing method H1 for hot data with a ratio of "1" greater than 50%, the processing method C0 for cold data with a ratio of "1" less than 50%, the processing method C1 for cold data with a ratio of "1" greater than 50%, and the processing method HC for cold data/hot data with a ratio of "1" equal to 50%. Wherein the original data is data to be written in MLC NAND Flash. The cold and hot degree of the original data is determined according to the erasing period and the retention time, and is identified by a Flash Translation Layer (FTL). In addition, the FTL also determines whether the original data is written to the LSB page or the MSB page. The proportion of "1" in the original data is statistically obtained before the entire original data is written.
For thermal data with a proportion of "1" less than 50%, process H0 was: during the first inversion, the data written in the LSB page is inverted, namely the state of 11 is exchanged with the state of 01, and the state of 10 is exchanged with the state of 00; on the second flip, when the LSB is "1", the data to be written to the MSB page is flipped, i.e., the "11" state is interchanged with the "10" state.
For thermal data with a proportion of "1" greater than 50%, process H1 is: when the LSB is "0", the data to be written to the MSB page is flipped, i.e., the "00" state is interchanged with the "01" state.
For cold data with a proportion of "1" less than 50%, process C0 is: flipping the data to be written to the LSB page, i.e., the "11" state is interchanged with the "01" state, and the "10" state is interchanged with the "00" state.
For cold data with a proportion of "1" greater than 50%, process C1 is: the data to be written to the MSB page is flipped, i.e., the "11" state is interchanged with the "10" state, and the "00" state is interchanged with the "01" state.
For a proportion of "1" equal to 50% of the cold data or a proportion of "1" equal to 50% of the hot data, the treatment HC is: the proportion of "1" in the original data is equal to 50%, after the inversion, the proportion of "1" of the original data is still equal to 50%, and in order to make the whole method faster, no processing is done for the original data of this case.
After the above processing, the scale size of each state is "11 >10 ═ 00> 01" for the thermal data. For cold data, the scale size of each state is "10 >11 ═ 00> 01". The magnitude relationship is only related to the degree of heat and cold of the data, and is not related to the proportion of '1' in the original data. Furthermore, since the proportion of most files "1" in the storage system is less than 50% (where the proportion of "1" in dll files is low), the handling of this part of the file is critical to improve reliability.
The invention provides a method for reducing the error rate of an MLC NAND flash memory through data pattern rearrangement, which comprises the following steps:
s1, obtaining the proportion of '1' and the cold and hot degree of original data;
and S2, according to the proportion of '1' of the original data and the cold and hot degree, the original data to be written into the LSB page or the MSB page of the MLC NAND flash memory is overturned, and the data mode is rearranged.
Step S2, according to the proportion of '1' of the original data and the cold and hot degree, the original data to be written into the LSB page or the MSB page of the MLC NAND flash memory is overturned, and the data mode is rearranged specifically, the method comprises the following substeps:
s201, classifying the original data according to the proportion of '1' of the original data and the cold and hot degree, and if the proportion of '1' of the original data is less than 50% and the original data is hot data, entering the step S202; if the "1" ratio of the original data is greater than 50% and the data is thermal data, go to step S203; if the proportion of "1" of the original data is less than 50% and the data is cold data, go to step S204; if the "1" ratio of the original data is greater than 50% and the data is cold data, go to step S205; if the "1" ratio of the original data is 50%, the process proceeds to step S206;
s202, turning over the original data for two times: during the first inversion, the data to be written into the LSB page is inverted, and during the second inversion, when the LSB is '1', the data to be written into the MSB page is inverted;
s203, turning the original data for one time: when the LSB is "0", the data to be written to the MSB page is flipped;
s204, turning the original data for one time: flipping data to be written to the LSB page;
s205, turning over the original data for one time: flipping the data to be written to the MSB page;
s206, no processing is carried out on the original data.
As shown in fig. 3, a Flash Translation Layer (FTL) is responsible for completing the hot and cold data sensing and high and low page allocation process. Whether the original data belongs to hot data or cold data is judged through cold and hot data sensing, and high and low page allocation determines whether the data is written into an LSB page or an MSB page. The data pattern rearrangement is completed in a Hardware Adaptation Layer (HAL), specifically, before data is written into a NAND flash memory array, data to be written into an LSB page or an MSB page is subjected to specific inversion, and the probability of data errors is reduced by changing the data pattern, so that the original error rate is reduced.
For thermal data, program disturb errors dominate, and programming a cell with a higher threshold voltage causes more program disturb to neighboring cells.
As shown in fig. 4, the proportion of "1" in the original data was 40%. The four states of "11", "10", "00" and "01" in the original data account for 16%, 24%, 36% and 24%, respectively, in a ratio of 4:6:9: 6. On the first flip, the data to be written to the LSB page is flipped, i.e., the "11" state is interchanged with the "01" state, and the "10" state is interchanged with the "00" state. After the inversion, the four states of 11, 10, 00 and 01 respectively account for 24%, 36%, 24% and 16%, and the ratio is 6:9:6: 4. After the first flip, the proportion of the "01" and "00" states with higher threshold voltages is reduced, the proportion of the "11" and "10" states with lower threshold voltages is increased, and program disturb and retention errors are reduced. On the second flip, the data to be written to the MSB page is flipped when the LSB is "1", i.e., the "11" state is interchanged with the "10" state. After the inversion, the four states of 11, 10, 00 and 01 respectively account for 36%, 24% and 16%, and the ratio is 9:6:6: 4. After the second flip, the proportion of the "11" state with the lowest threshold voltage is further increased, thereby further reducing program disturb and retention errors. Through two times of overturning, the data mode is rearranged, the error-prone state is reduced, and meanwhile, the probability of data errors is reduced by increasing the state which is not easy to cause interference, so that the error rate is reduced, and the service life of the flash memory is prolonged.
As shown in fig. 5, the proportion of "1" in the original data is 60%. The four states of "11", "10", "00" and "01" in the original data account for 36%, 24%, 16% and 24%, respectively, in a ratio of 9:6:4: 6. The data to be written to the MSB page is flipped when the LSB is "0", i.e., the "00" state is interchanged with the "01" state. After the inversion, the four states of 11, 10, 00 and 01 respectively account for 36%, 24% and 16%, and the ratio is 9:6:6: 4. Through the flipping, the proportion of the "01" state of the high threshold voltage is reduced, thereby reducing retention errors and program disturb.
For cold data, retention errors dominate, and the higher the threshold voltage the lower the state reliability. Of the four states, the "01" state, which has the highest threshold voltage, is most susceptible to retention errors.
As shown in fig. 6, the proportion of "1" in the original data was 40%. The four states of "11", "10", "00" and "01" in the original data account for 16%, 24%, 36% and 24%, respectively, in a ratio of 4:6:9: 6. Flipping the data to be written to the LSB page, i.e., the "11" state is interchanged with the "01" state, and the "10" state is interchanged with the "00" state. After the inversion, the four states of 11, 10, 00 and 01 respectively account for 24%, 36%, 24% and 16%, and the ratio is 6:9:6: 4. After the inversion, the proportion of the states of '01' and '00' with higher threshold voltage is reduced, and the dominant retention error is reduced. Unlike thermal data, a second flip of the data to be written to the MSB page (i.e., the "11" state is interchanged with the "10" state) is not performed because program disturb and retention errors cause the threshold voltage to move in the opposite direction, and program disturb is greater when the proportion of the "11" state is smaller, so that retention errors due to electron leakage can be counteracted with program disturb.
As shown in fig. 7, the proportion of "1" in the original data is 60%. The four states of "11", "10", "00" and "01" in the original data account for 36%, 24%, 16% and 24%, respectively, in a ratio of 9:6:4: 6. The data to be written to the MSB page is flipped, i.e., the "11" state is interchanged with the "10" state, and the "00" state is interchanged with the "01" state. After the inversion, the four states of 11, 10, 00 and 01 respectively account for 24%, 36%, 24% and 16%, and the ratio is 6:9:6: 4. Through the overturning, the proportion of the state of '01' of the high threshold voltage is reduced, so that the retention error is reduced; while the proportion of the "10" state increases, program disturb increases, offsetting more retention errors, thereby reducing the raw bit error rate.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (5)
1. A method for reducing the bit error rate of MLC NAND flash memory by data pattern re-layout, the method comprising the steps of:
s1, obtaining the proportion of '1' and the cold and hot degree of original data;
s2, according to the proportion of '1' of the original data and the cold and hot degree, the original data to be written into the LSB page or the MSB page of the MLC NAND flash memory is turned over, and the data mode is rearranged;
the step S2 includes the steps of:
s201, classifying the original data according to the proportion of '1' of the original data and the cold and hot degree, and if the proportion of '1' of the original data is less than 50% and the original data is hot data, entering the step S202; if the "1" ratio of the original data is greater than 50% and the data is thermal data, go to step S203; if the proportion of "1" of the original data is less than 50% and the data is cold data, go to step S204; if the "1" ratio of the original data is greater than 50% and the data is cold data, go to step S205; if the "1" ratio of the original data is 50%, the process proceeds to step S206;
s202, turning over the original data for two times: during the first inversion, the data to be written into the LSB page is inverted, and during the second inversion, when the LSB is '1', the data to be written into the MSB page is inverted;
s203, turning the original data for one time: when the LSB is "0", the data to be written to the MSB page is flipped;
s204, turning the original data for one time: flipping data to be written to the LSB page;
s205, turning over the original data for one time: flipping the data to be written to the MSB page;
s206, no processing is carried out on the original data.
2. The method of reducing the bit error rate of the MLC NAND Flash memory of claim 1 wherein the raw data is data to be written to MLC NAND Flash.
3. The method of claim 1, wherein the proportion of "1" in the raw data is statistically derived before the entire raw data is written.
4. The method of claim 1, wherein the cold and hot levels of the original data are determined according to the erase and write cycles and the retention time.
5. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the method of reducing the bit error rate of MLC NAND flash memory according to any of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811506261.5A CN109656748B (en) | 2018-12-10 | 2018-12-10 | Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811506261.5A CN109656748B (en) | 2018-12-10 | 2018-12-10 | Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109656748A CN109656748A (en) | 2019-04-19 |
| CN109656748B true CN109656748B (en) | 2020-05-19 |
Family
ID=66113215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811506261.5A Active CN109656748B (en) | 2018-12-10 | 2018-12-10 | Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109656748B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110533414B (en) * | 2019-08-29 | 2024-01-05 | 金邦达有限公司 | Method for converting system in traffic IC card transaction |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009087509A (en) * | 2007-10-03 | 2009-04-23 | Toshiba Corp | Semiconductor storage device |
| CN102693760B (en) * | 2011-03-24 | 2015-07-15 | 扬智科技股份有限公司 | Error correction method for NAND flash memory |
| CN104467871B (en) * | 2014-11-17 | 2018-03-27 | 哈尔滨工业大学 | Improve the date storage method of NAND Flash memory reliabilities |
| CN107039059B (en) * | 2016-02-01 | 2022-05-10 | 三星电子株式会社 | Memory package, memory module including the same, and memory package operation method |
| CN106445740A (en) * | 2016-09-22 | 2017-02-22 | 深圳市先天海量信息技术有限公司 | Control method and control system for NAND flash memory data in solid state disk |
| CN107590021B (en) * | 2017-08-22 | 2020-01-03 | 华中科技大学 | Encoder and decoder for reducing error rate of flash memory and encoding and decoding methods |
-
2018
- 2018-12-10 CN CN201811506261.5A patent/CN109656748B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109656748A (en) | 2019-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101556779B1 (en) | Access method of storage device | |
| US8365030B1 (en) | Nonvolatile memory devices and error correction methods thereof | |
| US9281066B2 (en) | Dynamically configurable MLC state assignment | |
| CN107608628B (en) | Flash memory controller | |
| CN107590021B (en) | Encoder and decoder for reducing error rate of flash memory and encoding and decoding methods | |
| US10553290B1 (en) | Read disturb scan consolidation | |
| JP2019168937A (en) | Memory system, control method and controller | |
| KR101606498B1 (en) | Method, controller, and memory device for correcting data bit(s) of at least one cell of flash memory | |
| US7804726B2 (en) | Apparatuses and methods for multi-bit programming | |
| Tanakamaru et al. | 95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm | |
| KR20100096457A (en) | Memory system and data processing method thereof | |
| KR20100067942A (en) | Access method of non-volatile memory device | |
| US9520184B2 (en) | Method for writing in-system programming code into flash memory for better noise margin | |
| US20220180922A1 (en) | Selective wordline scans based on a data state metric | |
| KR20100090966A (en) | Semiconductor memory device and data processing method thereof | |
| Zhao et al. | CeSR: A Cell State Remapping Strategy to Reduce Raw Bit Error Rate of MLC NAND Flash. | |
| US20100115176A1 (en) | Data transfer and programming in a memory device | |
| CN109656748B (en) | Method for reducing error rate of MLC NAND flash memory through data pattern rearrangement | |
| CN109032514A (en) | A kind of method for reading data, device, equipment and readable storage medium storing program for executing | |
| US10396821B2 (en) | Generating Hamming weights for data | |
| US20180275917A1 (en) | Memory controller, memory system, and control method | |
| Xu et al. | Encoding separately: An energy-efficient write scheme for MLC STT-RAM | |
| Liu et al. | DEPS: Exploiting a dynamic error prechecking scheme to improve the read performance of SSD | |
| US11615858B2 (en) | Media management operations based on health characteristics of memory cells | |
| CN115048040A (en) | Media management operations based on a ratio of valid data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |