TWI737703B - Nonvolatile memory module and method for operating a storage device - Google Patents

Abstract

A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

Description

Non-volatile memory module and method for operating storage device [Cross reference of related applications]

This application claims the rights of U.S. Provisional Patent Application No. 62/325,051 filed on April 20, 2016 based on 35 USC § 119. Korean Patent Application No. 10- No. 2016-0061012. The full texts of the two applications are incorporated into this case for reference.

One or more embodiments described herein are related to computing systems, non-volatile memory modules, and storage device methods.

Attempts have been made to develop non-volatile memory compatible with various interfaces of existing computing systems. For example, try to use flash memory as a data storage device or work by installing flash memory (or working memory) in the same slot or channel as the main memory or working memory of the computer system Memory. However, these attempts have proven to be flawed.

According to one or more embodiments, a method of operating a storage device includes: sending a request for an internal operation time of an internal operation to an external device; receiving an internal operation command corresponding to the request from the external device; and based on the The internal operation command executes the internal operation during the internal operation time. Requesting the internal operation time may include transmitting the request to the external device using a response message of an asynchronous event request command. The request for the internal operation time may include transmitting a message including the internal operation time required to perform the internal operation to the external device.

According to one or more other embodiments, a non-volatile memory module includes: at least one volatile memory; at least one non-volatile memory; and a memory control circuit for controlling the at least one volatile memory And the at least one non-volatile memory, wherein the memory control circuit is used to transmit an internal operation request message to an external device, and receive and receive the internal operation request message from the external device when an internal operation is to be performed Corresponding internal operation command and implement internal operation during internal operation time based on said internal operation command, and wherein said internal operation request message includes said internal operation time.

According to one or more other embodiments, a memory module includes: a plurality of dynamic random access memories (DRAM); and a memory control circuit for controlling the A dynamic random access memory, wherein the memory control circuit is used to: transmit a request for the internal operation time of the internal operation to the host; receive the internal operation time approval/rejection information corresponding to the request from the host; And based on the internal operating time The consent/rejection information implements all or part of the internal operation described.

According to one or more other embodiments, a dynamic random access memory includes: a memory cell array; and a renewed controller for transmitting a message about an internal operation request to an external device, receiving and receiving the message Corresponding internal operation command and execute the internal operation during internal operation time, wherein the internal operation is a renew operation of the memory cell array and wherein the message includes information about the internal operation time.

According to one or more other embodiments, an apparatus includes: a signal line; and a controller for controlling at least one volatile memory or at least one non-volatile memory based on a signal on the signal line, wherein the control The device is used to transmit an internal operation request message to an external device when an internal operation is to be performed, receive an internal operation command corresponding to the internal operation request message from the external device, and receive an internal operation command based on the internal operation command during the internal operation time. Perform internal operation, and wherein the internal operation request message includes the internal operation time.

10, 20, 40: computing system

41: processor

42: Memory module

43: Non-volatile memory

50: Data Server System

51: Database Management System/Related Database Management System

52: Cache server

53: application server

100: host/host device

100a: host

200: storage device

211, 212, 213, 214, 215, 400: dynamic random access memory

220: Memory Module Controller

300: Non-volatile memory module

310L: the first non-volatile memory

310R: second non-volatile memory

320L: the first volatile memory

320R: second volatile memory

330L: the first data buffer

330R: second data buffer

340: Memory control circuit

410: Memory cell array

420: New controller

ACT: Active command

ADDR: address pin

CAD: second command/address

CAN: First command/address

CH: memory channel

CH1: The first channel

CH2: second channel

CMD: Command pin

D0, D1, D2, D3, D4, D5, D6, D7: data

DB: data buffer

DIMM: memory module

DIMM1: the first memory module/memory module

DIMM2: second memory module/memory module

DQ: data/data pin

IOP, Iopa: internal operation commands

IOPB: internal operation command/second internal operation command

MSG: message pin/message channel

NVDIMM: Non-volatile memory module

PRE: Precharge command

RD: Read command/address

RT1: internal operation time/first internal operation time

RT2: Second internal operation time

RT3, RTk: internal operation time

S110, S120, S210, S220, S230: Operation

By describing the exemplary embodiments in detail with reference to the accompanying drawings, various features will become apparent to those skilled in the art. In the accompanying drawings: FIG. 1 illustrates an embodiment of a computing system.

Figure 2 illustrates an embodiment of a storage device.

FIG. 3 illustrates an embodiment of the internal operation time request and the response of the computing system.

Figure 4 illustrates another embodiment of a computing system.

FIG. 5 illustrates an embodiment of a non-volatile memory module.

Figure 6 illustrates an embodiment of the host interface timing.

Figure 7 illustrates another embodiment of the host interface timing.

Figure 8 illustrates another embodiment of a computing system.

FIG. 9 illustrates an embodiment of the timing of multiple memory modules.

Figure 10 illustrates another embodiment of a computing system.

Figure 11 illustrates another embodiment of a computing system.

Figure 12 illustrates an embodiment of a dynamic random access memory.

Figure 13 illustrates another embodiment of a computing system.

Fig. 14 illustrates an embodiment of the operation method of the host.

FIG. 15 illustrates an embodiment of the internal operation method of the storage device.

Figure 16 illustrates an embodiment of a data server system.

FIG. 1 illustrates an embodiment of a computing system 10 that may include a host 100 and a storage device 200. The computing system 10 can be, for example, a computer, a portable computer, an ultra-mobile personal computer (UMPC), a workstation, a data server, a net-book, or a personal digital assistant (personal digital assistant). assistant, PDA), web tablet, wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), digital camera, digital audio recorder/player , Digital picture/video recorder/player, portable game console, navigation system, block box, 3D TV, device and structure capable of transmitting and receiving information in a wireless environment One of the various electronic devices of the home network, one of the various electronic devices that constitute a computer network, one of the various electronic devices that constitute a telematics network, radio-frequency identification (radio-frequency identification) identification, RFID), or one of various electronic devices that constitute a computing system.

The host 100 can control the overall operation of the computing system 10. In an embodiment, the host 100 may include at least one processor, a central processing unit (CPU), a graphics processing unit (GPU), a memory controller, and the like. In an embodiment, the processor may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a combination thereof. In an embodiment, the memory controller can be implemented to control the storage device 200.

In an embodiment, the host 100 may provide the storage device 200 with information indicating approval or rejection of the internal operation time based on the request of the storage device 200. The internal operation time may be the time for performing the internal operation of the storage device 200.

In an embodiment, the internal operation time approval/rejection information can be transmitted or determined based on the type of command or data. In another embodiment, the internal operation time approval/rejection information can be transmitted via a separate line between the host 100 and the storage device 200.

In FIG. 1, an embodiment in which the host 100 transmits the internal operation time to the storage device 200 based on the request of the storage device 200 is illustrated. In another embodiment, the host device 100 may transmit the internal operation time approval/rejection information to the storage device 200 based on an internal policy instead of a request of the storage device 200.

The storage device 200 can be connected to the host 100 to store data about the operation of the host 100. The storage device 200 may be at least one of a volatile memory, a non-volatile memory, or a combination thereof. For example, the storage device 200 may be: dual in-line memory module (dual in-line memory module, DIMM), nonvolatile dual in-line memory module (nonvolatile dual in-line memory module, NVDIMM) ), solid state drive (SSD), universal flash storage (UFS), embedded multimedia card (eMMC), secure digital (SD) card, dynamic random Access memory (DRAM), static random access memory (static RAM, SRAM), reverse flash memory, vertical reverse flash memory, phase change random access memory (phase change RAM, PRAM), or resistive random access memory (resistive RAM, RRAM).

In an embodiment, the storage device 200 may be connected to the host 100 based on a double data rate (DDR) interface standard. For example, the storage device 200 can be implemented by any one of the DDRx series (x is an integer). The storage device 200 can be connected to the host 100 via various types of communication interfaces other than the double data rate interface. For example, the communication interface can meet the following communication standards: non-volatile memory express (NVMe), peripheral component interconnect express (PCIe), serial advanced technology attachment (serial AT attachment, SATA), small computer system interface (SCSI), serial attached SCSI (SAS), universal storage bus (universal storage bus, USB) attached to small computer system interface (USB attached SCSI, UAS), Internet small computer system interface (internet small computer system interface, iSCSI), fiber channel, or fiber channel over Ethernet, FCoE).

In an embodiment, when it is determined that the internal operation is to be performed according to the internal policy, the storage device 200 may request the internal operation time of the internal operation from the host 100. In an embodiment, the internal operation time request can be transmitted to the host 100 in a message format.

In an embodiment, the message with the internal operation time request can be transmitted to the host 100 via at least one data channel, at least one clock channel, at least one control channel, at least one dedicated message channel, or the like between the host 100 and the storage device 200. combination. For example, when an internal operation time request is transmitted via a data channel, the internal operation time request may be included in a response message corresponding to an asynchronous command. The asynchronous command may include an asynchronous event request command. Asynchronous events can be used to inform the software or controller of the host 100 of the status, error and health information of the storage device 200.

The above internal operation time request can be transmitted in the form of a message. In another embodiment, the internal operation time request may be provided to the host 100 in the form of a signal to request the selection of the register corresponding to the internal operation time of the internal operation.

In an embodiment, the storage device 200 can be implemented to perform internal operations after receiving the internal operation time approval/rejection information of the host 100. The internal operations may include various operations associated with, for example, refresh, timing calibration, process-voltage-temperature (PVT) compensation, internal data transmission, or another operation. In the embodiment, the internal operation time can be the same Consent/reject information to implement all or part of internal operations. To this end, the internal operation time approval/rejection information may further include information about the execution of all or part of the internal operation.

In the computing system 10 according to the embodiment, the storage device 200 may directly request the internal operation time of the internal operation of the storage device 200 from the host 100. The host 100 may transfer the authorization regarding time to the storage device 200 during the internal operation time based on the request. Therefore, the storage device 200 can sufficiently perform internal operations. For example, the host 100 may agree to the internal operation time of the internal operation of the storage device 200.

FIG. 2 illustrates an embodiment of a storage device 200 implemented by a memory module. 2, the storage device 200 may include a plurality of dynamic random access memories 211 to 214 and a memory module controller (RCD) 220. Each of the dynamic random access memory 211 to the dynamic random access memory 214 can input and output data DQ under the control of the memory module controller 220. The number of the dynamic random access memory 211 to the dynamic random access memory 214 in FIG. 2 is 4, but it can be a different number in another embodiment.

The memory module controller 220 can receive commands and/or addresses from the host 100 and control the input/output operations from the dynamic random access memory 211 to the dynamic random access memory 214. In an embodiment, the memory module controller 220 may send an internal operation time request for internal operations to the host 100 based on an internal strategy. In an embodiment, the memory module controller 220 may perform internal operations based on the internal operation time approval/rejection information transmitted from the host 100.

In an embodiment, the storage device 200 may further include a dynamic random access memory 215 for parity. In an embodiment, the storage device 200 may further include a data buffer DB for buffering the data DQ between the host 100 and the dynamic random access memory 211 to the dynamic random access memory 214. In an embodiment, the storage device 200 can be implemented to meet the DDRx synchronous dynamic random access memory (SDRAM) specification. For example, the storage device 200 can be implemented to meet the specifications of the next generation DDR4 SDRAM. The internal operation time can be implemented in a register setting method, for example.

FIG. 3 illustrates an embodiment of the internal operation time request and response based on the register set method in the computing system 10. 3, the storage device 200 may include a register set for storing a plurality of internal operation times RT1 to RTk (k is a natural number of 2 or greater). For example, the first internal operating time RT1 may be a time corresponding to 16 clocks and the second internal operating time RT2 may be a time corresponding to 8 clocks.

The memory controller of the host 100 can send a register selection signal to the storage device 200 based on the internal operation time request of the storage device 200. The register selection signal may be a signal for selecting a register corresponding to the internal operation time request from the register of the register group. For example, the register selection signal may include internal operation time approval/rejection information. In an embodiment, the register set may be located in the memory module controller 220 in FIG. 2 or in a different location.

The computing system 10 in FIG. 1 to FIG. 3 illustrates the embodiment in terms of internal operation time. In another embodiment, an internal operation request can be issued and in response to the The computing system 10 is explained in the context of the internal operation command of the internal operation request.

FIG. 4 illustrates another embodiment of a computing system 20 that may include a host 100a and a non-volatile memory module (NVDIMM) 300. The host 100a can receive an internal operation request from the non-volatile memory module 300, issue an internal operation command IOP based on the internal operation request, and send the issued internal operation command IOP to the non-volatile memory module 300. The internal operation command IOP may include the internal operation time of the internal operation. In an embodiment, the internal operation command IOP may further include information corresponding to the approval or rejection of the internal operation request.

In an embodiment, the internal operation request can be transmitted to the host 100a via, for example, a data pin, a data strobe pin, an address/command pin, a control signal pin, a message dedicated pin, or a combination thereof. In an embodiment, the internal operation command IOP can be generated by a command/address pin, a pin reserved for future use (RFU), or a combination thereof.

When an internal operation is to be performed according to the internal strategy, the non-volatile memory module 300 can send an internal operation request to the host 100a. The internal operation request can be implemented as a message/signal type, for example. For example, the internal operation request transmitted in the form of a message/signal may include the internal operation time of the internal operation.

In an embodiment, the non-volatile memory module 300 can be connected to the host 100a via a DDRx interface (x is a natural number). For example, the non-volatile memory module 300 can be implemented to meet the next-generation DDR4 SDRAM specifications.

In an embodiment, for example, a non-volatile electronic device conforming to the joint electronic device engineering council (JEDEC) standard can be used. Develop a dual in-line memory module (NVDIMM) to implement the non-volatile memory module 300. The non-volatile dual-in-line memory module can be a memory module that retains data even in the event of an unexpected power failure or system failure, or even when a power interruption occurs while the system ends normally. Non-volatile dual in-line memory modules can be used to improve application performance, recovery time from data security system failures, and the durability and reliability of solid-state drives.

Non-volatile dual in-line memory modules can have various forms. One embodiment of the non-volatile dual in-line memory module is a memory mapping device that can be accessed at or near memory speed and can be addressed by byte. Non-volatile dual in-line memory modules that support DDR4 SDRAM are commercially available from any of many hardware vendors. Another embodiment of the non-volatile dual in-line memory module is a flash device module located on the interconnection channel. Such non-volatile dual in-line memory modules can be accessed, for example, through the drive block of the host. When a front-end cache miss occurs, the flash device can be accessed. Another embodiment of the non-volatile dual in-line memory module is a module with all the advantages of fast-access dynamic random access memory and high-capacity non-volatile memory.

The non-volatile memory module 300 may include a message channel through which internal operation request messages are transmitted to the host 100a. In an embodiment, a DQ channel, a DQS channel, a clock channel, a control signal channel, or a combination thereof can be used as the message channel. In another embodiment, the message channel may have a dedicated channel for transmitting internal operation request messages.

In an embodiment, the internal operation request message may include the self-initiated internal operation The configured non-volatile memory module 300 requests the internal operation time so that the host 100a will not send a new command to the non-volatile memory module 300 for a predetermined time. In another embodiment, even if the host 100a issues a new command for a predetermined time, the non-volatile memory module 300 that has received the internal operation command can still ignore the new command.

In an embodiment, the internal operation time may vary based on the type of internal operation performed by the non-volatile memory module 300, for example. For example, the internal operation time for a new operation may be about several microseconds. The internal operation time of the internal data transmission operation may be, for example, about several hundred microseconds.

In an embodiment, when an internal operation request is received, the host 100a may approve or reject the internal operation request. For example, if the host 100a agrees to the internal operation request, the host 100a may issue an internal operation command IOP corresponding to the internal operation request and send the internal operation command IOP to the non-volatile memory module 300. For example, if the host 100a rejects the internal operation request, the non-volatile memory module 300 can postpone the internal operation. In an embodiment, the non-volatile memory module 300 can perform internal operations during the internal operation time without an interrupt command from the host 100a.

5 illustrates that the non-volatile memory module 300 may include a first non-volatile memory 310L and a second non-volatile memory 310R, a first volatile memory 320L and a second volatile memory 320R, and first data Another embodiment of the buffer 330L, the second data buffer 330R, and a memory control circuit (MMCD) 340.

First non-volatile memory 310L and second non-volatile memory 310R Each of them may include at least one non-volatile memory. In an embodiment, the at least one non-volatile memory may be a NAND flash memory, a vertical NAND flash memory (VNAND), a NAND flash memory, or a resistive flash memory. Random access memory (RRAM), phase change random access memory (PRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (ferroelectric random access memory) access memory, FRAM), spin transfer torque random access memory (STT-RAM), or thyristor RAM (TRAM).

In addition, non-volatile memory can be implemented with a three-dimensional array structure. In an embodiment, a three-dimensional (3D) memory array is provided. The 3D memory array may be monolithically formed at one or more physical levels of the memory cell array. The memory cell array has an active area on a silicon substrate and is connected to the memory cell array. The circuit system associated with the operation of the soma, regardless of whether the associated circuit system is located above or inside the substrate. The associated circuit system is located above or inside the substrate. The term "in a monolithic form" may correspond to directly depositing each layer of each level of the array on the layer of each underlying level of the array.

In an embodiment, the 3D memory array includes a vertical NAND string oriented vertically such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. Each vertical reverse and string may include at least one option located on the memory cell Selective transistor. The at least one selective transistor may have the same structure as the memory cell and may be formed together with the memory cell in a monolithic form.

The three-dimensional memory array includes multiple levels and has word lines or bit lines shared between the levels. The following files about an exemplary configuration of a three-dimensional memory array including multiple levels (where character lines and/or bit lines are shared among the levels) adopted by Samsung Electronics are incorporated in this case for reference: US Patent No. 7,679,133, No. 8,553,466, No. 8,654,587 and No. 8,559,235 and US Patent Publication No. 2011/0233648. Non-volatile memory can be applied to charge trap flash (CTF) in which an insulating layer is used as a charge storage layer and flash memory devices in which a conductive floating gate is used as a charge storage layer.

Each of the first volatile memory 320L and the second volatile memory 320R may include at least one dynamic random access memory. In an embodiment, the at least one dynamic random access memory may be implemented by a dual-port dynamic random access memory. For example, the first port of the at least one dynamic random access memory can be connected to at least one of the first non-volatile memory 310L and the second non-volatile memory 310R, and the at least one dynamic The second port of the random access memory can be connected to a corresponding one of the first data buffer 330L and the second data buffer 330R.

The memory control circuit 340 can be implemented to receive a command or address from the host 100a and generate a first command/address CAN for controlling the first non-volatile memory 310L and the second non-volatile memory 310R or for A second command/address CAD for controlling the first volatile memory 320L and the second volatile memory 320R.

In an embodiment, the memory control circuit 340 can issue And send the internal operation request to the host 100a. In an embodiment, the memory control circuit 340 may receive the internal operation command IOP from the host 100a and perform internal operations based on the received internal operation command IOP. The internal operation command IOP may include the internal operation time of the internal operation.

The non-volatile memory module 300 in FIG. 5 may include at least one first non-volatile memory 310L, at least one first volatile memory 320L, and a first non-volatile memory 310L arranged on the left side relative to the memory control circuit 340. A data buffer 330L, and at least one second non-volatile memory 310R, at least one second volatile memory 320R, and a second data buffer 330R arranged on the right side relative to the memory control circuit 340. In another embodiment, the non-volatile memory module 300 may have different arrangements of memory, memory control circuits, buffers, etc.

FIG. 6 illustrates an embodiment of the timing of the host interface corresponding to the internal operation request of the non-volatile memory module 300. In this embodiment, the internal operation request can be transmitted to the host 100a through the host interface between the host 100a and the non-volatile memory module 300. The host interface can be, for example, a memory internal channel. In an embodiment, the internal operation request may include internal operation time for completing the internal operation or information about the internal operation time.

When the message including the internal operation request is transmitted to the host 100a via the message pin MSG, the information corresponding to the internal operation time can also be sent to the host 100a. The information corresponding to the internal operation time can be transmitted through the data pin DQ0 to the data pin DQ7. In one embodiment, the information corresponding to the internal operation time can be obtained via commands/addresses such as CKE pin, CS pin, CK pin, or ODT pin. Pin CA transmission.

The information related to the internal operation time can be selectively transmitted to the host 100a through the toggle of the message pin MSG. In an embodiment, the continuous two-state toggle frequency of the message pin MSG can represent the internal operation time. For example, the continuous two-state toggle frequency of the message pin MSG can be the time of internal operation.

In one embodiment, the internal operation request in the message may be an internal operation request for all libraries or some libraries. If the host 100a agrees to the internal operation request for all the libraries, the non-volatile memory module 300 can perform internal operations on all the libraries, and the host 100a cannot access the non-volatile memory module 300 at the same time. If the host 100a agrees to the internal operation request for the partial library, the internal operation can be performed only on the library selected from the partial library by the internal operation request. In this case, a library other than the selected library can be accessed for read/write operations.

In an embodiment, if an internal operation request and information corresponding to the internal operation time are received, the host 100a can determine whether to approve or reject the internal operation request.

If the internal operation request is approved, the host 100a can issue an internal operation command IOP, so that the non-volatile memory module 300 starts the internal operation. Then, the host 100a may not issue a new command to access the non-volatile memory module 300 during the internal operation time.

If the internal operation request is rejected, the host 100a can ignore the internal operation request by not executing an internal operation command and issue a command for notifying the rejection of the internal operation request. The non-volatile memory module 300 can identify the rejection notice of the host 100a And delay or abandon the execution of internal operations. In one embodiment, the internal operation time approval/rejection information may not be in the internal operation request of the non-volatile memory module 300.

FIG. 7 illustrates another embodiment of the timing of the host interface for the internal operation request of the non-volatile memory module 300. In this embodiment, the internal operation request can be provided in a two-operation procedure.

In the first operation, the non-volatile memory module 300 can only send the signal requesting internal operation to the host 100a through the message channel MSG, and store the internal operation time-related information (time information) in the non-volatile memory In the buffer area of the body module 300.

In the second operation, the host 100a can read the buffer area to issue a read command for extracting the internal operation time of the internal operation. In one embodiment, the host 100a can issue an internal operation command IOP based on the read time information. Then, the non-volatile memory module 300 can perform internal operations during the internal operation time based on the internal operation command IOP.

In addition, in the second operation, the host 100a issues a read command for extracting the internal operation time of the buffer area. In another embodiment, the non-volatile memory module 300 can read the internal operation time approval/rejection information stored in the buffer area based on the internal operation command IOP of the host 100a and execute the internal operation to achieve the read internal operation time.

FIG. 8 illustrates another embodiment of a computing system including two memory modules connected to one memory channel. Referring to Figure 8, the host can pass through a memory channel CH is connected to the first memory module DIMM1 and the second memory module DIMM2. Each of the first memory module DIMM1 and the second memory module DIMM2 can perform internal operations. For ease of description, the following assumes that the second memory module DIMM2 performs internal operations.

FIG. 9 illustrates an embodiment of the timing of the first memory module DIMM1 and the second memory module DIMM2 when the second memory module DIMM2 of the computing system shown in FIG. 8 performs internal operations.

8 and 9, the second memory module DIMM2 can perform internal operations during the internal operation time based on the internal operation command IOP. The internal operation can be a data transfer operation performed in the second memory module DIMM2. The host can prohibit access to the second memory module DIMM2 while performing internal operations. Even if the host does not access the second memory module DIMM2, the host can still access the first memory module DIMM1 in an idle state. For example, in FIG. 9, the first memory module DIMM1 can sequentially receive the precharge command PRE, the active command ACT, and the read command/address RD, and output the corresponding command/address RD. Data D0 to Data D7. Then, the first memory module DIMM1 can continue to perform the next read operation.

The computing system can hide the internal operation of the second memory module DIMM2 after the data communication between the host and the first memory module DIMM1. Since the internal operation of the second memory module DIMM2 is hidden, the performance of the system can be improved.

Table 1 illustrates an example of internal operation commands issued by the host computer of the computing system. Referring to Table 1, the host can issue the internal operation command IOPA and the internal operation command IOPB when agreeing to the internal operation based on the internal operation request of the memory module DIMM/non-volatile memory module NVDIMM. The internal operation command IOPA can instruct to perform internal operations on all banks of the memory module DIMM/non-volatile memory module NVDIMM. The second internal operation command IOPB can instruct to perform internal operations on a single bank of the memory module DIMM/non-volatile memory module NVDIMM.

In an embodiment, as in Table 1, the address pins can be used to distinguish the internal operations of all libraries and the internal operations of a single library. In an embodiment, the internal operation command IOPA and the internal operation command IOPB can be generated by a specific combination of command/address pins. This combination can be reserved for typical DDR4 SDRAM (reserved future use, RFU). In an embodiment, the command/address pins associated with the internal operation command IOPA and the internal operation command IOPB may include CKE, CS, CAS, RAS, ACT, bank address and address pins.

In an embodiment, the internal operation command IOPA and the internal operation command IOPB may include an internal operation time that varies according to the programmed value applied to the address pin. For example, the programmed value can be programmed to correspond to the address pin A0 to the address pin A9.

In FIG. 8 and FIG. 9, a computing system connects two memory modules DIMM1 and a memory module DIMM2 that can be identical to each other to a memory channel. In another embodiment, the computing system can connect the memory module DIMM and the non-volatile memory module NVDIMM to one memory channel.

Figure 10 illustrates an embodiment of a server system. 10, the computing system can connect the memory module DIMM and the non-volatile memory module NVDIMM to one memory channel. The host can access the memory module DIMM while performing the above-mentioned internal operations on the non-volatile memory module NVDIMM, and vice versa. For example, the host can access the non-volatile memory module NVDIMM while performing the above-mentioned internal operations on the memory module DIMM.

In the computing system in FIG. 10, the memory module DIMM and the non-volatile memory module NVDIMM are connected to a memory channel. In one embodiment, the computing system includes a memory module DIMM and a non-volatile memory module NVDIMM connected to two memory channels respectively.

Figure 11 illustrates another embodiment of a computing system. 11, the host can connect to the memory module DIMM through the first channel CH1 and connect to the non-volatile memory module NVDIMM through the second channel CH2. The host can access the memory module DIMM while performing the above-mentioned internal operations on the non-volatile memory module NVDIMM. This embodiment can be applied to, for example, a dynamic random access memory implemented in the form of a chip instead of a memory module.

FIG. 12 illustrates an embodiment of a dynamic random access memory 400 that may include a memory cell array 410 and a refresh controller 420. As shown in FIG. Memory cell array 410 can be packaged It includes a plurality of dynamic random access memory cells respectively arranged at the intersection of the word line and the bit line. The refresh controller 420 can perform the refresh operation of the dynamic random access memory cell. In an embodiment, the refresh controller 420 may perform a refresh operation based on a refresh command from the host or an external device.

In an embodiment, the refresh controller 420 may request the internal operation time from the host/external device when the internal operation is to be performed. The host/external device may send internal operation time approval/rejection information to the renew controller 420 based on the internal operation time request. The refresh controller 420 may receive the internal operation time approval/rejection information to perform the refresh operation during the internal operation time. In an embodiment, the renew controller 420 may perform a renew operation on all or some of the libraries. This embodiment can be applied to, for example, 3DX point (Xpoint) memory in which resistors are used as bits.

FIG. 13 illustrates an embodiment of a computing system 40 that may include a processor 41, a memory module (dual in-line memory module) 42, and a nonvolatile memory (NVM) 43. The processor 41 can control the memory module 42 and the non-volatile memory 43. In an embodiment, the processor 41 may issue an internal operation command based on an internal operation request of the memory module 42.

The memory module 42 can be connected to the processor 41 via a double data rate interface. The memory module 42 can send an internal operation request to the processor 41 when an internal operation is to be performed. In addition, the memory module 42 can be implemented to perform internal operations based on internal operation commands from the processor 41.

The non-volatile memory 43 can be connected to the processor 41 via a DDR-T (transaction) interface. In this case, the memory module 42 can implement non-volatile memory 43's cache function. In an embodiment, the non-volatile memory 43 may be a 3D-X point memory. This embodiment can be applied to the internal operation of the non-volatile memory 43, for example.

Figure 14 illustrates an embodiment of a method of operating a host. In this method, the host can connect to the memory channel of various types of storage devices (dual in-line memory module, non-volatile dual in-line memory module, dynamic random access memory, non-volatile memory). The volatile memory, solid-state drive, embedded multimedia card, secure digital card, Unix file system (Unix file system, UFS), etc.) receive an internal operation time request for implementing internal operations (S110). The host may approve or reject internal operations (for example, storage operations) based on the internal operation time request. The host can issue an internal operation command corresponding to the internal operation time request. The issued internal operation command may include the internal operation time (S120). The issued internal operation command can be transferred to the storage device, and the storage device can perform the internal operation during the internal operation time based on the internal operation command.

Figure 15 illustrates an embodiment of a method of operating a storage device. Referring to FIGS. 14 to 15, in this method, the storage device can determine whether internal operations will be performed according to internal policies and can send internal operation time requests for internal operations to the host (S210). The internal operation time request can be transmitted to the host in various forms (for example, a message form or a signal form). For example, the storage device can be implemented to send a message including an internal operation time request to the host.

Then, the storage device may receive an internal operation command including information indicating approval or rejection of the internal operation time from the host (S220). The storage device may perform all or part of the internal operation based on the internal operation command (S230).

In an embodiment, when the internal operation command includes information indicating that the internal operation time is approved, the storage device can ignore the new command issued by the host when performing the internal operation. In an embodiment, when the internal operation command includes information indicating the rejection of the internal operation time, the storage device may receive or process a new command issued by the host. The storage device can receive and buffer new commands issued by the host while performing internal operations. The storage device may first process the new command from the host after maintaining the internal operation based on the new command. This embodiment can be applied to, for example, a data server.

16 illustrates an embodiment of a data server system 50 that may include a related database management system (RDBMS) 51, a cache server 52, and an application server 53. The cache server 52 can maintain and delete different key and value pairs based on a disable notification from the database management system 51. At least one of the related database management system 51, the cache server 52, or the application server 53 can be the host, memory module DIMM, non-volatile memory module NVDIMM, dynamic Random access memory or non-volatile memory is implemented.

The methods, processes, and/or operations described herein can be implemented by codes or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or components other than those described herein. Since the algorithm that forms the basis of the method (or the operation of a computer, processor, controller, or other signal processing device) is described in detail, the code or instruction used to implement the operation of the method embodiment can be used for the computer, The processor, controller, or other signal processing device is transformed into the method used to implement the methods described herein. Dedicated processor for law.

The controllers, processors, and other processing features of the embodiments disclosed herein may be implemented in logic, which may include hardware, software, or both. When implemented at least partially in hardware, the controller, processor, and other processing features can be, for example, any of various integrated circuits including but not limited to the following integrated circuits: application-specific integrated circuits, Field programmable gate array, combination of logic gates, system chip, microprocessor, or another type of processing or control circuit.

When implemented at least partially in software, the controller, processor, and other processing features may include, for example, codes or instructions for storing, for example, a computer, processor, microprocessor, controller, or other signal processing device. Memory or other storage device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or components other than those described herein. Since the algorithm that is the basis of the formation method (or the operation of a computer, processor, microprocessor, controller or other signal processing device) is described in detail, the code or instruction used to implement the operation of the method embodiment A computer, processor, controller, or other signal processing device can be transformed into a dedicated processor for implementing the methods described herein.

According to one or more of the above embodiments, the storage device can directly request the internal operation time of the internal operation of the storage device from the host, and the host can transfer the authorization regarding time to the storage during the internal operation time based on the request. Device. Therefore, the storage device can fully perform internal operations.

Various exemplary embodiments have been disclosed herein, and although specific terms are used, these terms are only used and should be interpreted as general and explanatory meanings, and Not for restrictive purposes. In some cases, unless otherwise specified, the features, characteristics, and/or elements described in conjunction with specific embodiments may be used alone or in combination with features, characteristics, and/or elements described in conjunction with other embodiments. Therefore, it should be understood that various changes in form and details can be made without departing from the spirit and scope of the embodiments described in the scope of the patent application.

100a: host

300: Non-volatile memory module

310L: the first non-volatile memory

310R: second non-volatile memory

320L: the first volatile memory

320R: second volatile memory

330L: the first data buffer

330R: second data buffer

340: Memory control circuit

CAD: second command/address

CAN: First command/address

DB: data buffer

DQ: Information

Claims (20)

A method of operating a storage device, the method comprising: in response to detecting that an internal operation is required without any request from an external device, sending an internal operation request to the external device for obtaining consent for the internal operation of the storage device , The internal operation request includes a message indicating the internal operation time and is generated by the storage device; an internal operation command corresponding to the internal operation request is received from the external device, and the internal operation command indicates approval or rejection of the The internal operation request; and when the requested internal operation is approved by the external device, the internal operation is performed via the storage device during the internal operation time agreed by the internal operation command. The method according to claim 1, wherein the method further includes receiving a message read command for the storage device before sending a message ready signal to the external device and sending the internal operation request. The method according to claim 1, wherein the internal operation time indicates the amount of time required to perform the internal operation. The method according to claim 1, wherein requesting the internal operation time includes: storing the internal operation time in a buffer area of the storage device; and using a message channel to transmit the internal operation request to The external device, The method includes reading the internal operation time stored in the buffer area when the internal operation command is received and executing the internal operation for the read internal operation time. The method according to claim 1, wherein receiving the internal operation command includes receiving the internal operation command via at least one command pin, at least one address pin, or at least one pin reserved for future use (RFU). Describe the internal operation commands. The method according to the first item of the scope of patent application, wherein executing the internal operation includes executing the internal operation on all libraries or some libraries based on the internal operation command. The method according to item 1 of the scope of patent application, wherein: the internal operation command includes information indicating approval or rejection of the internal operation request, and the method includes when the internal operation command includes an indication of consent to the internal operation When requesting the information, ignore the new command issued from the external device. The method according to claim 1, wherein: the internal operation command includes information indicating approval or rejection of the internal operation request, and the method includes when the internal operation command includes an instruction to deny the internal operation When the information is requested, a new command issued from the external device is processed. The method according to claim 1, wherein the internal operation includes at least one of a renew operation, a timing calibration operation, or an internal data transmission operation. According to the method described in item 1 of the scope of patent application, the storage device includes dual in-line memory module (DIMM), non-volatile dual in-line memory module (NVDIMM), solid state drive (SSD) ), universal flash memory (UFS), embedded multimedia card (eMMC), secure digital (SD) card, dynamic random access memory (DRAM), static random access memory (SRAM), reverse and fast Flash memory, vertical reverse flash memory, phase change random access memory (PRAM), or resistive random access memory (RRAM). A non-volatile memory module includes: at least one volatile memory; at least one non-volatile memory; and a memory control circuit that controls the at least one volatile memory and the at least one non-volatile memory In response to detecting any request for internal operations without external devices, an internal operation request message for obtaining consent for the internal operation of the at least one volatile memory or the at least one non-volatile memory is generated , Wherein the memory control circuit is used to transmit the internal operation request message to the external device, receive an internal operation command corresponding to the internal operation request message from the external device, and the internal operation command indicates consent Or reject the internal operation request message, and when the internal operation is approved by the external device, execute the internal operation during the internal operation time through the memory control circuit, and wherein the internal operation request message Including the internal operation time. The non-volatile memory module as described in the 11th item of the scope of patent application, wherein while the internal operation is being performed, the memory control circuit ignores the A new command issued by an external device. The non-volatile memory module described in claim 11, wherein when the internal operation command including information corresponding to the rejection of the internal operation request is received, the memory control circuit is processed by all State the new command issued by the external device. According to the non-volatile memory module described in claim 11, the internal operation command includes the internal operation time or information corresponding to the internal operation time. The non-volatile memory module described in item 11 of the scope of patent application, wherein the memory control circuit passes through at least one command pin, at least one address pin, or at least one pin reserved for future use Receiving the internal operation command. According to the non-volatile memory module described in claim 11, wherein the memory control circuit uses at least one data pin or at least one data strobe pin to transmit the internal operation request message to the External device. The non-volatile memory module according to claim 11, wherein the memory control circuit transfers the internal operation request message to the external by using a signal toggle through at least one message pin Device. The non-volatile memory module described in claim 11, wherein the memory control circuit stores the internal operation time of the internal operation in a buffer area, and communicates with the The signal corresponding to the internal operation request message is transmitted to the external device, and the signal received from the external device is paired with the signal Corresponding read command, read the internal operating time stored in the buffer area based on the received read command, and receive from the external device corresponding to the read internal operating time The internal operation command. The non-volatile memory module according to claim 11, wherein the internal operation includes data performed between the at least one volatile memory or between the at least one non-volatile memory Transmission operation. As for the non-volatile memory module described in item 11 of the scope of patent application, the internal operation command includes a first internal operation command that instructs internal operations on all libraries or a second internal operation command that instructs internal operations on a single library. Operation command.

Images