CN104570849A - Method for estimating programming condition of anti-fuse FPGA (field-programmable gate array) - Google Patents
Method for estimating programming condition of anti-fuse FPGA (field-programmable gate array) Download PDFInfo
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- CN104570849A CN104570849A CN201410758848.0A CN201410758848A CN104570849A CN 104570849 A CN104570849 A CN 104570849A CN 201410758848 A CN201410758848 A CN 201410758848A CN 104570849 A CN104570849 A CN 104570849A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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Abstract
The invention discloses a method for estimating the programming condition of an anti-fuse FPGA (field-programmable gate array). The method comprises the following steps: dividing a wafer for bearing the anti-fuse FPGA into a plurality of regions; respectively implanting a plurality of anti-fuse devices for testing in the regions; applying a testing voltage to an upper electrode and a lower electrode of each anti-fuse device for testing and programming for each anti-fuse device for testing; acquiring estimation resistance values of intermediate medium layers of the programmed anti-fuse devices for testing in different regions and comparing the estimation resistance values with a preset reference resistance value so as to determine FPGA function normal ratios corresponding to the different regions; according to the actual condition, estimating the programming condition that the anti-fuse FPGA programs a region to be selected. According to the method, by estimating the programming condition of the anti-fuse FPGA, not only can product quality be greatly improved and reliability of the product is ensured, but also development cost can be reduced.
Description
Technical field
The present invention relates to antifuse field programmable gate array field, particularly a kind of predictor method of antifuse field programmable gate array program condition.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA) is the product further developed on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, overcomes again the shortcoming that original programming device gate circuit number is limited.In view of the advantage of FPGA, FPGA programming technique seems more important, and programming technique popular is now as follows: fuse Fuse, antifuse Anti-fuse, Eprom, Eeprom, Sram.There are some defects in some of them technique, such as SRAM programming technique, because programming information leaves in RAM, will lose after power-off, when again powering on, then need to reconfigure, in addition, FPGA easily affects by single-particle radiation effect under space space environment, such as: in severe space environment, be easily subject to the impact such as intense radiation, energetic particle hits from district's sun at sunshine, form Space Radiation Effects, Space Radiation Effects mainly comprises total dose effect, single-particle inversion, single event latch-up, single event burnout etc.The performance of often kind of effect to FPGA has damage, causes loss of vital data in gatherer process, and particularly for spaceborne telemetry equipment, this Space Radiation Effects defect has been a very important problem.
Because anti-fuse FPGA has, capability of resistance to radiation is strong, reliability high feature, and becomes a kind of mainstream technology of outer space electronic system as main control chip, is applicable to each fields such as space flight, military affairs, industry.
But, anti-fuse FPGA is disposal programmable device (One-Time-Programming), because its programming test belongs to destructive test, and the factor affecting its program condition is a lot, so after anti-fuse FPGA programming all terminates, anti-fuse FPGA Programming's quality is also determined, owing to affecting the uncertainty of program condition factor, be difficult to the factor of going its quality of analyzing influence according to finished product after programming, so, the blindness of producing causes anti-fuse FPGA processing yields not high, the corresponding cost of development too increasing system.
Summary of the invention
For the various defects that prior art exists, the present invention proposes a kind of predictor method of antifuse field programmable gate array program condition, comprising:
1) wafer being used for carrying antifuse field programmable gate array is divided into multiple region; Multiple test antifuse device is implanted respectively in described multiple region;
2) to top electrode and the bottom electrode applying test voltage of described test antifuse device, the middle dielectric layer of described test antifuse device is punctured, for each test antifuse device is programmed;
3) obtain the assessment resistance value of the middle dielectric layer of the test antifuse device after the programming in zones of different, compare with the reference resistance value preset, determine the field programmable gate array function natural rate of interest corresponding to described zones of different;
4) carry out the programming of antifuse field programmable gate array and estimate program condition according to actual for the region chosen.
According to the present invention, the carrier of antifuse field programmable gate array is Wafer (wafer), it is the carrier producing used in integrated circuits, refer generally to monocrystalline silicon disk, monocrystalline silicon disk is drawn by common silica sand and refines, make silicon single crystal rod through dissolving, purifying, distill series of measures, silicon single crystal rod, after polishing, section, just becomes wafer.Wafer is the most frequently used semiconductor material, by its diameter be divided into 4 inches, 5 inches, 6 inches, 8 inches, 12 inches 14 inches, 15 inches, 16 inches ... 20 inches with first-class.Wafer is larger, and on same disk, producible IC is more, can reduce costs; But require material technology and production technology higher.
Through a large amount of tests, the discovery that applicant is pleasantly surprised: for specific antifuse manufacture craft, the biggest factor affecting antifuse device program condition is the positional factor of antifuse device on Wafer.As shown in Figure 1, antifuse device be a kind of by two conductive layers and between the semiconductor devices that forms of insulating medium layer.When not programming, conductive layer separates due to insulating medium layer, the open circuit of antifuse two ends.When plus high-pressure (during programming), insulating medium is by high electric field breakdown, and form conductive channel, now the resistance of antifuse is minimum, forms electrical connection, antifuse short circuit (being melt through) between the conductive layer of both sides.Namely antifuse device programming is be added in by high pressure on antifuse device two conductive plates for programming, the insulating medium between pole plate is punctured the process forming resistance.By the resistance value after surveying program, the program condition of antifuse device just can be derived.Therefore, the quality forming the dielectric layer of antifuse becomes the biggest factor affecting antifuse device program condition.And medium is generally generated by CVD (chemical meteorology deposition) technique, CVD technique is more responsive in the position of Wafer to device, generally speaking, the device medium being positioned at Wafer central area is thinner, and the device medium being positioned at Wafer edge is thicker, the thickness of medium directly has influence on the program condition of antifuse device, therefore monitor that the antifuse programming characteristic of zones of different on Wafer just can reflect the program condition of the antifuse device on whole Wafer indirectly, namely achieves and estimates the program condition of antifuse device.
Adopt predictor method of the present invention, can instruct and select preferably arrangement, Improving The Quality of Products, guarantee the reliability of product, reduce volume production cost.
In some embodiments, wherein in described step 3) in, average to the resistance value of the middle dielectric layer of all test antifuse devices in each region and calculate described assessment resistance value, described reference resistance value is the conventional resistive value after adopting single antifuse resistance programming.
In some embodiments, in step 3) in, when the described assessment resistance value in a certain region and reference resistance value deviation ratio are less than or equal to [0,20%], determine that the function natural rate of interest of the antifuse field programmable gate array in this region is 100%.
In some embodiments, when the described assessment resistance value in a certain region and reference resistance value deviation ratio interval (20%, 40%] interior time, determine that the function natural rate of interest of the antifuse field programmable gate array in this region is 90%.
In some embodiments, when the described assessment resistance value in a certain region and reference resistance value deviation ratio interval (40%, 100%] interior time, determine that the function natural rate of interest of the antifuse field programmable gate array in this region is 70%.
In some embodiments, when the described assessment resistance value in a certain region and reference resistance value deviation ratio are greater than 100% in interval, determine that the function natural rate of interest of the antifuse field programmable gate array in this region is less than 50%.
In some embodiments, in described step 1) in, described wafer is divided into multiple region equably.
In some embodiments, in described step 1) in, when described wafer is of a size of 4 inches, described wafer is divided into 5 regions equably.
In some embodiments, in described step 1) in, when described wafer is of a size of 8 inches, described wafer is divided into 11 regions equably.
The present invention, not only can significantly Improving The Quality of Products by estimating the program condition of anti-fuse FPGA, guarantees the reliability of product, and can reduce cost of development.
Accompanying drawing explanation
Fig. 1 is the structural profile schematic diagram of the antifuse of an embodiment of the present invention;
Fig. 2 be an embodiment of the present invention Wafer on the capable of being monitored program regions schematic diagram of uniform design.
Embodiment
For estimating the program condition of anti-fuse FPGA, the present invention select selection A, B, C, D, E these five on the Wafer of 4 inches equally distributed monitor program regions (in other test also the size of visual Wafer can suitably adjust subregion number, such as just subregion can be increased on the Wafer of 8 inches 11 even more.More subregion can make estimation results more accurate, but this can take more Wafer area, the area normally producing antifuse device is diminished, also can increase the workload of test in addition.)。In above-mentioned five subregions, implant the test antifuse device of some respectively, these antifuse devices only for manufacturer's test, can not produce any impact to normal antifuse device.After treating whole Wafer completion of processing, programming and testing is carried out to the test antifuse device in the zones of different on whole Wafer, the antifuse device program condition in this region is representatively assessed with these test antifuse devices, thus the object that realization is estimated the antifuse device program condition on whole Wafer.
The predictor method of Fig. 2 to antifuse field programmable gate array program condition is coordinated to be described in further detail as follows below by experimental data:
1, the wafer being used for carrying described antifuse field programmable gate array is evenly divided into five regions of A, B, C, D, the E shown in Fig. 2 as monitoring program regions, implants two test antifuse devices respectively in this region;
2, to top electrode and the bottom electrode applying test voltage of described test antifuse device, the middle dielectric layer of described test antifuse device is punctured, for each test antifuse device is programmed;
3, the resistance value of the middle dielectric layer of the test antifuse device of two in each region is averaged calculate described assessment resistance value, with preset reference resistance value (described reference resistance value be adopt single antifuse resistance programming after conventional resistive value) compare, determine the field programmable gate array function natural rate of interest corresponding to described zones of different;
4, carry out the programming of antifuse field programmable gate array and estimate program condition according to actual for the region chosen.
Specific experiment data are as shown in following table (1):
Table (1)
Arithmetic draw value is asked to the resistance value in above-mentioned zone, and makes comparisons with reference resistance value (after antifuse resistance programming herein, conventional value is 1000 ohm), draw and estimate conclusion below:
A district resistance value: (1082+786)/2=934 ohm
Estimate conclusion: belong within the scope of conventional resistive value, the FPGA yield in this region is higher.
Actual measurement (finished product test) result: the equal function of FPGA in this region is normal.
B district resistance value: (1352+1375)/2=1363.5 ohm
Estimate conclusion: exceed conventional resistive value 30%, the FPGA yield in this region can be influenced.
Measured result: the FPGA function natural rate of interest in this region is 90%.
C district resistance value: (998+764)/2=881 ohm
Estimate conclusion: belong within the scope of conventional resistive value, the FPGA yield in this region is higher.
Measured result: the equal function of FPGA in this region is normal.
D district resistance value: (942+836)/2=889 ohm
Estimate conclusion: belong within the scope of conventional resistive value, the FPGA yield in this region is higher.
Measured result: the equal function of FPGA in this region is normal.
E district resistance value: (1256+1478)/2=1367 ohm
Estimate conclusion: exceed conventional resistive value 30%, the FPGA yield in this region can be influenced.
Measured result: the equal function of FPGA in this region is normal.
In sum, by choosing A, B, C, D, E five regions as monitoring program regions, the resistance value of the middle dielectric layer of described antifuse device after the programming in acquisition zones of different; And compare with reference number, determine the program condition of the described antifuse field programmable gate array in zones of different.
By comparing discovery, above-mentioned conclusion of estimating meets following table (2):
Table (2)
The foregoing is only part embodiment of the present invention; only unrestricted the present invention for illustration of the present invention; the any amendment done within every the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a predictor method for antifuse field programmable gate array program condition, comprising:
1) wafer being used for carrying antifuse field programmable gate array is divided into multiple region; Multiple test antifuse device is implanted respectively in described multiple region;
2) to top electrode and the bottom electrode applying test voltage of described test antifuse device, the middle dielectric layer of described test antifuse device is punctured, for each test antifuse device is programmed;
3) obtain the assessment resistance value of the middle dielectric layer of the test antifuse device after the programming in each zones of different, compare with the reference resistance value preset, determine the field programmable gate array function natural rate of interest corresponding to described zones of different;
4) carry out the programming of antifuse field programmable gate array and estimate program condition according to actual for the region chosen.
2. method according to claim 1, it is characterized in that, in described step 3) in, average to the resistance value of the middle dielectric layer of all test antifuse devices in each region and calculate described assessment resistance value, described reference resistance value is the conventional resistive value after adopting single antifuse resistance programming.
3. method according to claim 1, is characterized in that, in described step 3) in,
When the described assessment resistance value in a certain region and reference resistance value deviation ratio are less than or equal to [0,20%], determine that the function natural rate of interest of the antifuse field programmable gate array in this region is 100%.
4. method according to claim 1, is characterized in that,
When the described assessment resistance value in a certain region and reference resistance value deviation ratio interval (20%, 40%] interior time, determine that the function natural rate of interest of the antifuse field programmable gate array in this region is 90%.
5. method according to claim 1, is characterized in that,
When the described assessment resistance value in a certain region and reference resistance value deviation ratio interval (40%, 100%] interior time, determine that the function natural rate of interest of the antifuse field programmable gate array in this region is 70%.
6. method according to claim 1, is characterized in that,
When the described assessment resistance value in a certain region and reference resistance value deviation ratio are greater than 100% in interval, determine that the function natural rate of interest of the antifuse field programmable gate array in this region is less than 50%.
7. the method according to any one of claim 1-6, is characterized in that, in described step 1) in, described wafer is divided into multiple region equably.
8. method according to claim 7, is characterized in that, in described step 1) in, when described wafer is of a size of 4 inches, described wafer is divided into 5 regions equably.
9. method according to claim 7, is characterized in that, in described step 1) in, when described wafer is of a size of 8 inches, described wafer is divided into 11 regions equably.
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