CN104570849B - Method for estimating programming condition of anti-fuse FPGA (field-programmable gate array) - Google Patents
Method for estimating programming condition of anti-fuse FPGA (field-programmable gate array) Download PDFInfo
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- CN104570849B CN104570849B CN201410758848.0A CN201410758848A CN104570849B CN 104570849 B CN104570849 B CN 104570849B CN 201410758848 A CN201410758848 A CN 201410758848A CN 104570849 B CN104570849 B CN 104570849B
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- antifuse
- resistance value
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- programmable gate
- gate array
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
Abstract
The invention discloses a method for estimating the programming condition of an anti-fuse FPGA (field-programmable gate array). The method comprises the following steps: dividing a wafer for bearing the anti-fuse FPGA into a plurality of regions; respectively implanting a plurality of anti-fuse devices for testing in the regions; applying a testing voltage to an upper electrode and a lower electrode of each anti-fuse device for testing and programming for each anti-fuse device for testing; acquiring estimation resistance values of intermediate medium layers of the programmed anti-fuse devices for testing in different regions and comparing the estimation resistance values with a preset reference resistance value so as to determine FPGA function normal ratios corresponding to the different regions; according to the actual condition, estimating the programming condition that the anti-fuse FPGA programs a region to be selected. According to the method, by estimating the programming condition of the anti-fuse FPGA, not only can product quality be greatly improved and reliability of the product is ensured, but also development cost can be reduced.
Description
Technical field
The present invention relates to antifuse field programmable gate array field, more particularly to a kind of antifuse field-programmable gate array
The predictor method of row program condition.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA) is in PAL, GAL, CPLD
Deng the product further developed on the basis of programming device.It is as one kind in special IC (ASIC) field half
Custom circuit and occur, both solved the deficiency of custom circuit, overcome original programming device gate circuit number again limited
Shortcoming.In view of the advantage of FPGA, FPGA programming techniques seem more important, and current popular programming technique is as follows：Fuse Fuse,
Antifuse Anti-fuse, Eprom, Eeprom, Sram.There are some defects, such as SRAM programmings technique in some of them technique,
As programming information is stored in RAM, will lose after power-off, when going up electricity again, then need to reconfigure, in addition, FPGA exists
Easily affected by single-particle radiation effect under space spatial environmentss, such as：Easily by from day in severe spatial environmentss
Intense radiation, energetic particle hits according to area's sun etc. affect, and form Space Radiation Effects, and Space Radiation Effects mainly include total
Dosage effect, single-particle inversion, single event latch-up, single event burnout etc..Every kind of effect has damage to the performance of FPGA, causes
Loss of vital data in gatherer process, especially for spaceborne remote-measuring equipment, this Space Radiation Effects defect has been one
Very important problem.
As anti-fuse FPGA has, capability of resistance to radiation is strong, the high feature of reliability, and becomes the outer space as main control chip
A kind of mainstream technology of electronic system, is adapted to each fields such as space flight, military affairs, industry.
However, anti-fuse FPGA is disposal programmable device (One-Time-Programming), due to its programming examination
Test and belong to destructive testing, and affect the factor of its program condition a lot, so after anti-fuse FPGA programming all terminates, instead
Fuse FPGA Programming's qualities have also determined that, the uncertainty due to affecting program condition factor, after programming it is difficult to according to into
Product go the factor of its quality of analyzing influence, so, the blindness of production causes anti-fuse FPGA processing yields not high, accordingly
Increased the development cost of system.
The content of the invention
For the various defects that prior art is present, the present invention proposes a kind of antifuse field programmable gate array programming
The predictor method of situation, including：
1) multiple regions will be divided into for the wafer for carrying antifuse field programmable gate array；In the plurality of region
Multiple test antifuse devices are implanted into respectively inside；
2) Top electrode and bottom electrode to the test antifuse device applies test voltage, and the test is melted with anti-
The middle dielectric layer of silk device punctures, and is that each test is programmed with antifuse device；
3) the assessment resistance value of the middle dielectric layer of the test antifuse device after the programming in zones of different is obtained,
Compare with default reference resistance value, determine the field programmable gate array function natural rate of interest corresponding to the zones of different；
4) program condition is estimated according to actually carrying out the region to be chosen of antifuse field programmable gate array programming.
According to the present invention, the carrier of antifuse field programmable gate array is Wafer (wafer), and it is production integrated circuit
Carrier used, refers generally to monocrystalline silicon wafer, and monocrystalline silicon wafer is drawn by common silica sand and refined, through dissolving, purification, distillation one
Silicon single crystal rod is made in series of measures, and silicon single crystal rod just becomes wafer after polishing, section.Wafer is the most frequently used half
Conductor material, by its diameter be divided into 4 inches, 5 inches, 6 inches, 8 inches, 12 inches 14 inches, 15 inches, 16 inches ...
20 inches with first-class.Wafer is bigger, and on same disk, producible IC is more, it is possible to decrease cost；But require material technology and
Production technology is higher.
Through substantial amounts of test, the pleasantly surprised discovery of applicant：For specific antifuse processing technology, antifuse is affected
The biggest factor of device programming situation is positional factor of the antifuse device on Wafer.As shown in figure 1, antifuse device is
A kind of semiconductor device being made up of two conductive layers and the insulating medium layer between.When unprogrammed, conductive layer is due to exhausted
Edge dielectric layer separates, the open circuit of antifuse two ends.In the case of plus high-pressure (during programming), dielectric is punctured by high electric field,
Conductive channel is formed, now the resistance of antifuse is minimum, between the conductive layer of both sides, form electrical connection, antifuse short circuit is (molten
It is logical).Antifuse device programming is to be added in high pressure on two conductive plates of antifuse device to be programmed, will be exhausted between pole plate
Edge dielectric breakdown forms the process of resistance.Resistance value after surveying program, so that it may derive the programming shape of antifuse device
Condition.Therefore, the quality for forming the dielectric layer of antifuse becomes the biggest factor for affecting antifuse device program condition.And medium
As by CVD (chemical meteorology deposition) techniques generating, CVD techniques are more sensitive in the position of Wafer to device, it is however generally that,
Device medium positioned at Wafer central areas is relatively thin, and the device medium for being located at Wafer edges is thicker, and the thickness of medium is direct
Have influence on the program condition of antifuse device, thus monitor zones of different on Wafer antifuse programming characteristic can between it is reversed
The program condition of the antifuse device on whole Wafer is mirrored, that is, is realized the program condition to antifuse device and is estimated.
Using the predictor method of the present invention, selection preferably arrangement, Improving The Quality of Products, it is ensured that product can be instructed
Reliability, reduce volume production cost.
In some embodiments, wherein in the step 3) in, to all tests antifuse device in each region
The resistance value of the middle dielectric layer of part averages to calculate the assessment resistance value, and the reference resistance value is using single
Conventional resistive value after antifuse resistance programming.
In some embodiments, in step 3) in, when some region of assessment resistance value and reference resistance value
When deviation ratio is less than or equal to [0,20%], determine that the function natural rate of interest of the antifuse field programmable gate array in the region is
100%.
In some embodiments, when some region of assessment resistance value and reference resistance value deviation ratio are in interval
(20%, 40%] it is interior when, determine the region antifuse field programmable gate array function natural rate of interest be 90%.
In some embodiments, when some region of assessment resistance value and reference resistance value deviation ratio are in interval
(40%, 100%] it is interior when, determine the region antifuse field programmable gate array function natural rate of interest be 70%.
In some embodiments, when some region of assessment resistance value and reference resistance value deviation ratio are in interval
During more than 100%, determine that the function natural rate of interest of the antifuse field programmable gate array in the region is less than 50%.
In some embodiments, in the step 1) in, the wafer is divided evenly into multiple regions.
In some embodiments, in the step 1) in, when the size of the wafer is 4 inches, the wafer is equal
It is divided into 5 regions evenly.
In some embodiments, in the step 1) in, when the size of the wafer is 8 inches, the wafer is equal
It is divided into 11 regions evenly.
The present invention is estimated by the program condition to anti-fuse FPGA, not only can significantly improving product matter
Amount, it is ensured that the reliability of product, and development cost can be reduced.
Description of the drawings
Structural profile schematic diagrams of the Fig. 1 for the antifuse of an embodiment of the present invention；
Capable of being monitored program regions schematic diagrams of the Fig. 2 for uniform design on the Wafer of an embodiment of the present invention.
Specific embodiment
To estimate the program condition of anti-fuse FPGA, the present invention selects selection A, B, C, D, E on 4 inches of Wafer
This five equally distributed to monitor that (also the size of visual Wafer suitably can be adjusted point program regions in other tests
The number in area, such as on 8 inches of Wafer just can by subregion increase to 11 it is even more many.More subregions can make pre-
Estimate result more accurate, but this can take more Wafer areas so that the area of normal production antifuse device diminishes, separately
The outer workload that can also increase test.).A number of test antifuse device is implanted into respectively in above-mentioned five subregions,
These antifuse devices are only used for manufacturer's test, will not produce any impact to normal antifuse device.Treat that whole Wafer adds
After work is finished, test is programmed to the test antifuse device in the zones of different on whole Wafer, with these tests
With antifuse device as the antifuse device program condition for representing the assessment region, so as to realize to anti-on whole Wafer
The purpose estimated by fuse-wire device program condition.
Below by experimental data coordinate Fig. 2 the predictor method of antifuse field programmable gate array program condition is made into
One step describes in detail as follows：
1st, by for the wafer for carrying the antifuse field programmable gate array be evenly dividing the A shown in Fig. 2, B, C,
Five regions of D, E are implanted into two test antifuse devices respectively as monitoring program regions, in this region；
2nd, to the test antifuse device Top electrode and bottom electrode applies test voltage, and the test is melted with anti-
The middle dielectric layer of silk device punctures, and is that each test is programmed with antifuse device；
3rd, two tests in each region are averaged to count with the resistance value of the middle dielectric layer of antifuse device
The assessment resistance value is calculated, (the reference resistance value is using single antifuse resistance programming with default reference resistance value
Conventional resistive value afterwards) compare, determine the field programmable gate array function natural rate of interest corresponding to the zones of different；
4th, program condition is estimated according to actually carrying out the region to be chosen of antifuse field programmable gate array programming.
Shown in specific experiment data such as following table (1)：
Table (1)
Seek arithmetic draw value to the resistance value in above-mentioned zone, and with reference resistance value (antifuse resistance programming herein
Conventional value is 1000 ohm afterwards) make comparisons, draw and following estimate conclusion：
A areas resistance value：(1082+786)/2=934 ohms
Estimate conclusion：Belong in the range of conventional resistive value, the FPGA yields in the region are higher.
Actual measurement (finished product test) result：The equal functions of FPGA in the region are normal.
B areas resistance value：(1352+1375)/2=1363.5 ohms
Estimate conclusion：More than conventional resistive value 30%, the FPGA yields in the region can be impacted.
Measured result：The FPGA functions natural rate of interest in the region is 90%.
C areas resistance value：(998+764)/2=881 ohms
Estimate conclusion：Belong in the range of conventional resistive value, the FPGA yields in the region are higher.
Measured result：The equal functions of FPGA in the region are normal.
D areas resistance value：(942+836)/2=889 ohms
Estimate conclusion：Belong in the range of conventional resistive value, the FPGA yields in the region are higher.
Measured result：The equal functions of FPGA in the region are normal.
E areas resistance value：(1256+1478)/2=1367 ohms
Estimate conclusion：More than conventional resistive value 30%, the FPGA yields in the region can be impacted.
Measured result：The equal functions of FPGA in the region are normal.
In sum, it is used as by five regions of selection A, B, C, D, E and can monitors program regions, is obtained in zones of different
The resistance value of the middle dielectric layer of the antifuse device after programming；And compare with reference number, determine described in zones of different
The program condition of antifuse field programmable gate array.
By comparing discovery, above-mentioned conclusion of estimating meets following table (2)：
Table (2)
The foregoing is only the present invention part specific embodiment, be merely to illustrate the present invention and unrestricted send out
Bright, any modification, equivalent and improvement for being made within every the spirit and principles in the present invention etc. should be included in the present invention
Protection domain within.
Claims (9)
1. a kind of predictor method of antifuse field programmable gate array program condition, including：
1) multiple regions will be divided into for the wafer for carrying antifuse field programmable gate array；Divide in the plurality of region
Multiple test antifuse devices are not implanted into；
2) Top electrode and bottom electrode to the test antifuse device applies test voltage, by test antifuse device
The middle dielectric layer of part punctures, and is that each test is programmed with antifuse device；
3) the assessment resistance value of the middle dielectric layer of the test antifuse device after the programming in each zones of different is obtained,
Compare with default reference resistance value, determine the field programmable gate array function natural rate of interest corresponding to the zones of different；
4) program condition is estimated according to actually carrying out the region to be chosen of antifuse field programmable gate array programming.
2. method according to claim 1, it is characterised in that in the step 3) in, to all surveys in each region
The resistance value of the middle dielectric layer of antifuse device on probation averages to calculate the assessment resistance value, the reference resistance
Value is using the conventional resistive value after single antifuse resistance programming.
3. method according to claim 1, it is characterised in that in the step 3) in,
When some region of assessment resistance value is less than or equal to [0,20%] with reference resistance value deviation ratio, it is determined that
The function natural rate of interest of the antifuse field programmable gate array in the region is 100%.
4. method according to claim 1, it is characterised in that
When some region of assessment resistance value and reference resistance value deviation ratio it is interval (20%, 40%] it is interior when, it is determined that
The function natural rate of interest of the antifuse field programmable gate array in the region is 90%.
5. method according to claim 1, it is characterised in that
When some region of assessment resistance value and reference resistance value deviation ratio it is interval (40%, 100%] it is interior when, it is determined that
The function natural rate of interest of the antifuse field programmable gate array in the region is 70%.
6. method according to claim 1, it is characterised in that
When some region of assessment resistance value is more than 100% in interval with reference resistance value deviation ratio, the area is determined
The function natural rate of interest of the antifuse field programmable gate array in domain is less than 50%.
7. the method according to any one of claim 1-6, it is characterised in that in the step 1) in, the wafer quilt
It is divided evenly into multiple regions.
8. method according to claim 7, it is characterised in that in the step 1) in, when the size of the wafer is 4 English
Very little, the wafer is divided evenly into 5 regions.
9. method according to claim 7, it is characterised in that in the step 1) in, when the size of the wafer is 8 English
Very little, the wafer is divided evenly into 11 regions.
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| CN104124181A (en) * | 2013-04-23 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for debugging chip yield and wafer |
-
2014
- 2014-12-10 CN CN201410758848.0A patent/CN104570849B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5786240A (en) * | 1996-06-27 | 1998-07-28 | Xilinx, Inc. | Method for over-etching to improve voltage distribution |
| CN1450561A (en) * | 2002-04-09 | 2003-10-22 | 惠普公司 | Non-volatile, multi-level memory device |
| CN101154711A (en) * | 2006-09-27 | 2008-04-02 | 中国科学院微电子研究所 | Organic anti-fuse and method for preparing the same |
| CN102142045A (en) * | 2010-01-29 | 2011-08-03 | 吕一云 | Method for simulating leakage current distribution of integrated circuit design |
| CN104124181A (en) * | 2013-04-23 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for debugging chip yield and wafer |
Non-Patent Citations (1)
| Title |
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| 基于CMOS工艺平台反熔丝FPGA实现;陶 伟等;《电子与封装》;20120831;第12卷(第8期);第2节第1-6段、第3节第1段，图1，表1 * |
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