JP2006041420A - Evaluation element for electronic device, and evaluation method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an evaluation element for an electronic device that can evaluate the resistance dispersion of a specific structure within an electronic device for each formation position of the electronic device, and to provide its evaluation method. <P>SOLUTION: An evaluation element 100, which evaluates the contact resistance dispersion within a flash memory 300's cell formed on a silicon wafer W, has a hole chain 20 containing a plurality of units, having a structure similar to a contact region in the cell to evaluate a resistance value between a first and second electrode pads 2a and 2b. Next, the resistance value between the first and third electrode pads 2a and 2c is evaluated, a resistance value between the first and the fourth pads 2a and 2d is evaluated, and then a resistance value between the first and fifth electrode pads 2a and 2e is evaluated. From the extent of the resistance value of a hole chain increased with respect to the number of units, the contact resistance dispersion inside a flash memory 300 cell can be found. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic device evaluation element and an electronic device evaluation method.

  On the scribe line of a wafer on which a large number of IC chips to be manufactured are formed, a TEG (test element) is usually used for alternative evaluation of the basic structure and electrical characteristics of the IC chip at the element level and IC level. group). Such TEGs are composed of element groups of various types and sizes depending on the object and purpose of evaluation, and in many cases, a plurality of TEGs are provided at regular intervals on the wafer surface.

  For example, when evaluating a contact resistance generated between an impurity diffusion layer provided on a silicon wafer and a metal wiring, an evaluation element having a hole chain is included in the TEG. A method of indirectly evaluating the contact resistance between the impurity diffusion layer and the metal wiring by measuring the total resistance value of the hole chain is known (see, for example, Patent Document 1).

  FIG. 8 is a plan view showing a configuration example of an evaluation element 90 according to a conventional example. As shown in FIG. 8, the evaluation element 90 includes a hole chain 80 and a pair of electrode pads 95. Among these, the hole chain 80 is composed of a plurality of impurity diffusion layers 93 provided at regular intervals in the TEG formation region, and metal wiring 91 that electrically connects the adjacent impurity diffusion layers 93 to each other. Yes. The electrode pad 95 is for contacting the probe needle.

  A combination of one metal wiring 91 in the hole chain 80, one impurity diffusion layer 93, and two contact holes (plug electrodes) that connect the impurity diffusion layer 93 to the metal wiring 91 overlying the impurity diffusion layer 93 (hereinafter, referred to as a "metal electrode 91"). The number is also called a chain number. Conventionally, the number of chained hole chains is only one level, for example, about 150 to 200.

  When the contact resistance between the metal wiring 91 and the impurity diffusion layer 93 is indirectly evaluated using such a hole chain 80, a predetermined voltage is applied between the pair of electrode pads 95 shown in FIG. , Current is passed through the hole chain 80. Then, the current value flowing at this time is measured. From this current value and the applied voltage value, the total resistance value of the hole chain 80 (that is, the resistance value of the impurity diffusion layer 93, the resistance value of the metal wiring 91, and between the metal wiring 91 and the impurity diffusion layer 93). The sum of the contact resistance value and the contact resistance value.

  Next, the resistance value per unit is calculated by dividing the total resistance value by the number of chains. Strictly speaking, the resistance value per unit includes not only the contact resistance but also the resistance value of one metal wiring 91 and the resistance value of one impurity diffusion layer 93. Therefore, if the resistance value per unit is within the standard range, the contact resistance is normal. It is judged.

In the conventional semiconductor device manufacturing process, the contact resistance mainly focuses on variations in the wafer plane. This is because, in order to make the electrical characteristics of the IC chip uniform, it has been considered important to minimize the variation in contact resistance across the wafer.
JP-A-10-135298

  Incidentally, in recent years, miniaturization and power saving of semiconductor devices are progressing, and the amount of current flowing through metal wiring in an IC chip is also decreasing. In particular, in the flash memory, the cell current has become extremely small as several tens [μA] or less. In order to stabilize the electrical characteristics of flash memory, etc., which have significant power savings, rather than reducing variations in contact resistance within the wafer surface, contacts in extremely narrow areas such as cells It has become important to reduce the resistance variation (ie, to reduce irregular contacts in the cell).

However, the conventional method for evaluating contact resistance is intended to know the variation in contact resistance across the entire surface of the wafer, and the data calculated from this evaluation method is based on the variation in contact resistance within the hole chain 80. And variations in contact resistance within the wafer plane.
Therefore, the conventional evaluation method can obtain only data in which the variation in contact resistance within the cell and the variation in contact resistance within the wafer surface are mixed, and the extremely small contact in the cell (or IC chip). Resistance variation could not be evaluated correctly. Conventionally, there has been no evaluation method for evaluating only such extremely small variations in contact resistance in the cell, TEG suitable for the evaluation, and the like.

  The present invention has been made paying attention to such an unsolved problem of the prior art, and it is possible to evaluate resistance variation of a predetermined structure in an electronic device for each formation position of the electronic device. An object of the present invention is to provide an electronic device evaluation element and an electronic device evaluation method that can be performed.

[Invention 1] In order to achieve the above object, an evaluation element of an electronic device according to Invention 1 is an evaluation element for evaluating resistance variation of a predetermined structure in an electronic device formed on a substrate. A plurality of evaluation patterns including a structure to be tested of the same type as the structure are provided, the evaluation patterns are different in the number of the structures to be tested, and the evaluation patterns are formed close to each other in the substrate. It is characterized by that.

Here, the evaluation element is formed in a predetermined region, for example, a region where a TEG near the electronic device is formed (hereinafter referred to as “TEG formation region”). The TEG formation region is often defined on a scribe line that separates one electronic device and another electronic device that are adjacent to each other in the substrate. A plurality of such TEG formation regions are usually provided in the substrate.
The “predetermined structure” of the electronic device is, for example, a conductive layer provided on a substrate and an insulating film covering the conductive layer, and a through hole (contact hole, via hole) provided in the insulating film. Etc.) and a wiring layer and the like electrically connected to the conductive layer. The “structure to be tested” has the same structure and size as the “predetermined structure”, and includes, for example, the conductive layer and the wiring layer.

  Further, the quantity (number) of the structures under test included in each evaluation pattern should straddle the boundary line (border line) that is likely to include even one structure under test having an abnormal resistance value. It is preferable to set to. For example, when about one defect is expected in 500, the number of structures under test included in one evaluation pattern is set to 100, and the number of structures under test included in another evaluation pattern is 1000. Individual.

According to the evaluation element of the electronic device according to the first aspect, the degree of increase in the resistance value of the evaluation pattern with respect to the number of the structures to be tested by measuring the resistance values of the plurality of evaluation patterns having different numbers of the structures to be tested. Can be requested. The variation in resistance value of the structure under test can be known from the degree of increase.
That is, the resistance variation of the structure under test within the limited position range of the substrate can be known. Therefore, it is possible to evaluate the resistance variation of the predetermined structure from only the electronic devices in the vicinity of the predetermined region from the resistance variation of the structure under test formed in the predetermined region of the substrate. Thereby, for example, variation in contact resistance between the impurity diffusion layer and the plug electrode in the electronic device can be evaluated for each formation position of the electronic device.

[Invention 2] The evaluation element of the electronic device of Invention 2 is characterized in that in the evaluation element of the electronic device of Invention 1, the evaluation patterns share the same structure to be tested.
With such a configuration, the number of test structures formed in a predetermined region of the substrate can be reduced, and an increase in the area occupied by the evaluation element can be suppressed to some extent.

[Invention 3] The evaluation element of the electronic device of the invention 3 is an evaluation element for evaluating the resistance variation of the predetermined structure in the electronic device formed on the substrate, and is the same type of structure to be tested as the predetermined structure. A plurality of evaluation patterns including a body, wherein the evaluation patterns are different in size of the structure to be tested, and the evaluation patterns are formed close to each other in the substrate. It is.

Here, the “structure to be tested” has the same structure as the “predetermined structure”, but a part or all of the parts constituting the structure are different.
According to the evaluation element of the electronic device according to the third aspect, the resistance value of the evaluation pattern with respect to the size of the structure under test is measured by measuring the resistance values of the plurality of evaluation patterns having different sizes of the structure under test. The degree of increase can be obtained. The variation in resistance value per unit size of the structure under test can be known from the degree of increase.

  That is, it is possible to know the resistance variation per unit size of the structure under test within the limited position range of the substrate. Therefore, it is possible to evaluate the resistance variation of the predetermined structure from only the electronic devices in the vicinity of the predetermined region from the resistance variation of the structure under test formed in the predetermined region of the substrate. Thereby, for example, it is possible to evaluate the variation in poly resistance in an electronic device for each formation position of the electronic device.

[Invention 4] The electronic device evaluation method according to Invention 4 is a method for evaluating resistance variation of a predetermined structure in an electronic device formed on a substrate, and includes any one of Inventions 1 to 3. Each of the resistance values of the plurality of evaluation patterns included in the evaluation element is measured.

  With such a configuration, it is possible to know variation in resistance of the structure under test within a limited position range of the substrate. Therefore, it is possible to evaluate the resistance variation of the predetermined structure from only the electronic devices in the vicinity of the predetermined region from the resistance variation of the structure under test formed in the predetermined region of the substrate.

Hereinafter, an evaluation element for an electronic device and an evaluation method for an electronic device according to the present invention will be described with reference to the drawings.
(1) First Embodiment FIG. 1 is a plan view illustrating a configuration example of an evaluation element 100 according to a first embodiment of the present invention. The evaluation element 100 is an element for evaluating variation in resistance (that is, contact resistance) of a contact portion in a cell of a flash memory formed on, for example, a silicon wafer.

As shown in FIG. 1, the evaluation element 100 includes a hole chain 20 and a plurality of electrode pads 2 electrically connected to both ends and the middle of the hole chain 20. For example, as shown in FIG. 1, the evaluation element 100 is provided with five electrode pads 2 a to 2 e. FIGS. 2A and 2B are a plan view illustrating a configuration example of the hole chain 20. , A-A 'arrow cross-sectional view.

  As shown in FIG. 2A, the hole chain 20 includes a metal wiring 21, an impurity diffusion layer 23 formed on the silicon wafer, and a plug for electrically connecting the metal wiring 21 and the impurity diffusion layer 23. And an electrode 25. As shown in FIG. 2 (B), for example, a plurality of impurity diffusion layers 23 are formed in an island shape on the surface of the silicon wafer W and in the vicinity thereof, and one impurity diffusion layer 23 adjacent on the silicon wafer W and another impurity diffusion layer 23 are formed. An element isolation layer 27 is formed between the impurity diffusion layer 23.

As shown in FIG. 2B, the metal wiring 21 is formed on an interlayer insulating film 29 formed on the silicon wafer W. Further, a contact hole H is formed in a portion of the interlayer insulating film 29 sandwiched between the metal wiring 21 and the impurity diffusion layer 23. The plug electrode 25 is embedded in the contact hole H.
As shown in FIG. 2B, the impurity diffusion layer 23 has an N-type conductivity, for example. The silicon wafer W has a P-type conductivity, for example. With such a structure, the plurality of metal wirings 21 formed on the interlayer insulating film 29 are connected in series by the plug electrode 25 and the impurity diffusion layer 23 (in other words, formed on the silicon wafer W). The plurality of impurity diffusion layers 23 are connected in series by the plug electrode 25 and the metal wiring 21.)

  Incidentally, the evaluation element 100 including the impurity diffusion layer 23, the element isolation layer 27, the interlayer insulating film 29, the contact hole H, the plug electrode 25, the metal wiring 21, and the like performs a wafer process when forming a flash memory on the silicon wafer W. It is formed in parallel with the flash memory. The evaluation element 100 is obtained by copying the impurity diffusion layer in the cell of the flash memory, the metal wiring, the contact portion made of the plug electrode and the like and the structure in the vicinity thereof, and connecting them together.

Accordingly, the diffusion depth (Xj) of the impurity diffusion layer 23, its impurity species and its concentration, the film isolation and thickness of each of the element isolation layer 27, the interlayer insulating film 29, the plug electrode 25, and the metal wiring 21, and its contact. The opening diameter or the like of the hole H is the same type and the same size as the contact portion of the flash memory and the vicinity thereof.
Hereinafter, a combination of this one impurity diffusion layer 23, two plug electrodes 25 formed on this one impurity diffusion layer 23, and one metal wiring 21 connected to one of these two plug electrodes 25. A structure consisting of is called a unit. Further, the number of units in the hole chain 20 is also called a chain number.

Returning to FIG. The number of units (that is, the number of chains) of the hole chain 20 between the first electrode pad 2a and the second electrode pad 2b is n ₁ , and between the first electrode pad 2a and the third electrode pad 2c. The chain number of the hole chain 20 is n ₂ , the chain number of the hole chain 20 between the first electrode pad 2a and the fourth electrode pad 2d is n ₃ , and the first electrode pad 2a and the fifth electrode pad when the number of chains of the hole chain 20 between 2e was _{n 4,} n1 to n4 _are, for _{example, (n 1, n 2, n} 3, n 4) = (10,100,500,1000).

  FIG. 3 is a plan view showing an example of the formation position of the evaluation element 100. As shown in FIG. 3, a plurality of flash memories 300 as products are formed on the silicon wafer W. Adjacent flash memories 300 are partitioned by scribe lines S that intersect vertically and horizontally within the plane of the silicon wafer W. A plurality of TEG formation regions 200 are provided on a scribe line S that partitions the flash memory 300. As shown in FIG. 3, these TEG formation regions 200 are arranged at relatively equal intervals in the silicon wafer W plane. The evaluation element 100 is formed in each TEG formation region 200.

Next, a method for evaluating the variation in contact resistance in the cell of the flash memory 300 formed in the vicinity of the evaluation element 100 using the evaluation element 100 described above will be described.
FIG. 4 is a flowchart showing a contact resistance evaluation method using the evaluation element 100. The contact resistance evaluation method will be described with reference to FIG. 4 and FIG.

First, in step S1 of FIG. 4, probe needles (not shown) are applied to the first electrode pad 2a and the second electrode pad 2b, respectively. Then, a constant voltage is applied to the hole chain 20 between the first electrode pad 2a and the second electrode pad 2b through this probe needle to pass a current. In this manner, the resistance value of the hole chain 20 between the first and second electrode pads 2a and 2b (that is, when the number of chains is n1) is measured. Here, the resistance value obtained in step S1 and R _1.

Similarly, in step S2 of FIG. 4, a probe needle is applied to each of the first electrode pad 2a and the third electrode pad 2c, and the first and third electrode pads 2a and 2c are connected (ie, chained). The resistance value R ₂ of the hole chain 20 (when the number is n ₂ ) is measured. In step S3, probe needles are applied to the first electrode pad 2a and the fourth electrode pad 2d, respectively, and the distance between the first and fourth electrode pads 2a, 2d (that is, when the chain number is n ₃ ). ) of measuring a resistance value _{R 3} of the hole chain 20. In step S4, probe needles are applied to the first electrode pad 2a and the fifth electrode pad 2e, respectively, and the first and fifth electrode pads 2a, 2e (ie, when the chain number is n ₄ ). ) of measuring the resistance value _{R 4} of hole chain 20.

Next, in step S5 of FIG. 4, the relationship between the chain number n and the resistance value R in the hole chain 20 is clarified from the resistance values R _{1 to} R ₄ obtained in steps S1 to S4 of FIG. Here, for example, FIG. 5 shown below is drawn, the relationship between the chain number n and the resistance value R is represented by a straight line, and the correlation coefficient and the slope of this straight line are calculated.
FIG. 5 is a diagram illustrating the relationship between the number of chains n _{1 to} n ₄ in the hole chain 20 and the resistance values R _{1 to} R ₄ . In FIG. 5, the horizontal axis indicates the chain number n of the hole chain 20, and the vertical axis indicates the resistance value R of the hole chain 20. Ideally, a straight line indicated by a two-dot chain line in FIG. 5, that is, a relationship as shown in Expression (1) holds between the chain number n of the hole chain 20 and the resistance value R thereof.
R = A + n × R _unit (1)
R: resistance value of the hole chain A: constant n: number of chains, R _unit : resistance value per unit The resistance value R of the hole chain 20 is the resistance of the metal wiring 21 shown in FIG. , The sum of the resistance of the impurity diffusion layer 23, and the sum of the contact resistance between the impurity diffusion layer 23 and the metal wiring 21, and is expressed by the equation (2).
R = ΣR _metal + ΣR _diff + ΣR _cont (2)
ΣR _metal : Sum of resistance of metal wiring 21 ΣR _diff : Sum of resistance of impurity diffusion layer 23 ΣR _cont : Sum of contact resistance As shown in equation (1), the chain number n of hole chain 20 and its resistance value R Ideally, there should be a linear relationship between However, in practice, the relationship between the number n of chained holes 20 and the resistance value R is usually not a perfect straight line such that the correlation coefficient r = 1. The reason is as follows.

That is, the resistance value R of the hole chain 20 is a value obtained by adding ΣR _metal , ΣR _diff , and ΣR _cont as shown in Expression (2). Among these, R _cont has a larger value than R _metal and R _diff, and there is a high possibility that an abnormal value suddenly appears. From such a situation, as shown in FIG. 5, the relationship between the chain number n and the resistance value R is determined by the least square method or the like from the chain numbers n1 to n4 and the actually measured resistance values R _{1 to} R _4. When formulated, the correlation coefficient is not r = 1, and in most cases, r <1.

The four actual measurement points R _{1 to} R ₄ shown in FIG. 5 will be described as an example. As shown in FIG. 5, when the chain number of the hole chain 20 through which current flows is n ₂ = 100, the resistance value R ₂ The value is on an ideal straight line R _{ideal of the} resistance R indicated by a two-dot chain line. This suggests that units with abnormal contact resistance are at least less than 1% of all units.
Next, when the number of chained hole chains 20 through which current flows is n ₃ = 500, the value of the resistance value R ₃ slightly _deviates from the ideal straight line R _ideal . This suggests that there is a high possibility that the 500 units include a unit whose contact resistance value is an abnormal value (hereinafter referred to as “abnormal unit”).

Anomalous units usually occur with a certain degree of probability, although their appearance frequency may vary depending on the quality of the hole chain 20. For this reason, when the number of chains n of the hole chain 20 is small, for example, 10 or 100, it is rare that the hole chain 20 includes an abnormal unit. However, as the number of chains n increases, the hole chain eventually becomes long. 20 includes an abnormal unit, and its resistance value R is somewhat deviated from the ideal straight line R _ideal .

The variation degree of the resistance value R of the hole chain 20 can be grasped from the value of the correlation coefficient r of a straight line (relational expression) indicated by a solid line in FIG. It can be said that the degree of variation of the resistance value R of the hole chain 20 is smaller as the correlation coefficient r is closer to 1.
Next, in step S6 of FIG. 4, it is determined whether or not the correlation coefficient r of the straight line (relational expression) obtained in step S5 and its slope R _unit are within a predetermined management value (within an allowable range). judge. Here, when the correlation coefficient r and the slope R _unit are within the control values, that is, when the variation of the contact resistance R _cont in the evaluation element 100 is small and there is no problem with the value of R _cont itself, Proceed to S7. In step S7, the flash memory 300 (see FIG. 3) in the vicinity of the evaluation element 100 determines that there is no problem in the contact resistance in the cell as in the case of the evaluation element 100, and that it is a pass. Thereby, the flowchart of FIG. 4 is completed.

On the other hand, in step S6, when one or both of the correlation coefficient r and the slope R _unit are not within the control value, that is, the contact resistance R _cont of the evaluation element 100 varies, or the value itself has a problem. If there is, the process proceeds to step S8. In step S8, the flash memory 300 (see FIG. 3) in the vicinity of the evaluation element 100 is presumed to have a problem with the contact resistance in the cell similarly to the evaluation element 100. Determination is made and the flowchart of FIG. 4 is terminated.

Thus, according to the evaluation element 100 according to the first embodiment of the present invention, the chain number of the hole chain 20 is set to a multilevel of n _{1 to} n ₄ , and the resistance values R _{1 to} R ₄ at that time are respectively set. By measuring, the increase degree of the resistance value of the hole chain 20 with respect to the number of chains can be obtained. Then, the variation in the resistance value R _unit per _unit can be known from the degree of increase. That is, the variation of R _unit in each of the plurality of TEG formation regions 200 on the silicon wafer W can be known.

Therefore, for example, if the variation of R _unit in the TEG formation region 200a shown in FIG. 3 is known, the variation of the contact resistance R _cont in the cell is limited only to the flash memory 300 in the vicinity of the TEG formation region 200a. It is possible to evaluate. That is, the variation in the contact resistance R _cont can be evaluated for each formation position of the flash memory 300.

Further, since the hole chain 20 adopts a form in which units are shared among the chain numbers n _{1 to} n ₄ , the number of units can be suppressed with respect to the number of chains. Thereby, an increase in the occupied area of the evaluation element 100 can be effectively suppressed.
In the first embodiment, the silicon wafer W corresponds to the substrate of the present invention, and the flash memory 300 corresponds to the electronic device of the present invention. Further, the contact portion in the cell of the flash memory 300 corresponds to the predetermined structure of the present invention, and the contact resistance in the cell corresponds to the resistance of the predetermined structure of the present invention.

Further, it is a combination of one impurity diffusion layer 23, two plug electrodes 25 formed on the one impurity diffusion layer 23, and one metal wiring 21 connected to one of the two plug electrodes 25. The unit corresponds to the structure under test of the present invention. The first and second electrode pads 2a, sandwiched 2b (i.e., when the number of the chain is _{n 1)} and hole chain 20, each hole chain 20 when the number of chains is n2~n4 Corresponds to a plurality of evaluation patterns of the present invention.
(2) Second Embodiment FIG. 6 is a cross-sectional view showing a configuration example of a hole chain 120 according to a second embodiment of the present invention. 6, parts having the same functions and configurations as those of the hole chain 20 shown in FIGS. 2A and 2B are denoted by the same reference numerals, and detailed description thereof is omitted.

  The hole chain 120 shown in FIG. 6 differs from the hole chain 20 shown in FIGS. 2A and 2B in that the impurity diffusion layer 23 is replaced with a lower metal wiring 123 and the lower metal wiring 123. A via hole h, not a contact hole H, is formed between the contact hole H and the metal wiring (hereinafter also referred to as “upper layer metal wiring”) 21, and the cross section of the via hole h rather than the plug electrode 25 is formed in the via hole h. The second plug electrode 125 having a small diameter is provided. As shown in FIG. 6, an insulating film 124 is provided between the lower metal wiring 123 and the silicon wafer W.

With such a configuration, the resistance value R ′ of the hole chain 120 is the sum of the resistance of the upper metal wiring 121, the sum of the resistance of the lower metal wiring 123, and between the lower metal wiring 123 and the upper metal wiring 21. And the sum of the resistances (hereinafter referred to as “via resistance”) and is expressed by Equation (3).
R'= ΣR _{U. metal} + ΣR _{L. metal} + ΣR _via (3)
ΣR _{U. metal} : Sum of resistance of upper metal wiring 21 ΣR _{L. metal} : sum of resistance of lower layer metal wiring 123 ΣR _via : sum of via resistance Among these three parameters, the via resistance is particularly large compared to the other two parameters, and suddenly abnormal. The value is likely to come out.

Therefore, in the case of evaluating the via resistance variation using the evaluation element 100 ′ having such a hole chain 120, the relationship between the unit chain number n and the resistance value R ′ in the hole chain 120 is represented by a straight line, The correlation coefficient and the slope of this straight line (relational expression) are obtained. Thereby, in each of the plurality of TEG formation regions 200 in the silicon wafer W, it is possible to know the variation of the via resistance R _via in the region. Then, from the result, it is possible to evaluate the variation of the via resistance in the cell of the flash memory 300 for each formation position of the flash memory 300.

In the second embodiment, the via resistance in the cell of the flash memory 300 corresponds to the resistance of the predetermined structure of the present invention. Further, a combination of one lower metal wiring 123, two plug electrodes 125 formed on the one lower metal wiring 123, and one upper metal wiring 21 connected to one of the two plug electrodes 125. A unit corresponds to the structure under test of the present invention.
(3) Third Embodiment FIGS. 7A and 7B are a plan view showing a configuration example of a hole chain 220 according to a third embodiment of the present invention and a cross-sectional view taken along line BB ′. 7, parts having the same functions and configurations as those of the hole chain 20 shown in FIGS. 2A and 2B are denoted by the same reference numerals, and detailed description thereof is omitted.

  The hole chain 220 shown in FIGS. 7A and 7B is different from the hole chain 20 shown in FIGS. 2A and 2B in that the impurity diffusion layer 23 is a polysilicon resistor (hereinafter referred to as “polyester”). It is referred to as “resistors”.) The contact between 223 a and 223 b, the point where the metal wiring 21 is replaced with a plurality of electrode pads 221, and the contact between these polyresistors 223 a and 223 b and the electrode pad 221. A via hole h is formed instead of the hole H, and a third plug electrode 225 having a smaller cross-sectional diameter than the plug electrode 25 is provided in the via hole h.

Further, as shown in FIG. 7, an insulating film 224 is provided between the polyresistors 223 a and 223 b and the silicon wafer W. Here, the poly resistor is a pattern made of polysilicon doped with a conductive impurity such as phosphorus.
By the way, in the hole chain 220, as shown in FIG. 7A, when the length of the poly resistor 223a in plan view is L1, and the length of the poly resistor 223b in plan view is L2, There is a relationship as shown in Expression (4) between L1 and L2.
L2 = x × L1 (4)
x: natural number such as 1, 10, 100, 500,... Further, when the width of the poly resistor 223a in plan view is W1, and the width of the poly resistor 223b in plan view is W2, W1 = W2. is there. 7A and 7B, only two poly resistors are shown for convenience of drawing, but the hole chain 220 is, for example, x times as long as L1 in plan view, and the x Are provided with a plurality of poly resistors 223c, 223d,.

With such a configuration, the resistance value R ″ of the hole chain 220 includes the sum of the resistances of the electrode pads 221, the sum of the resistances of the poly resistors 223 a, 223 b, 223 c,..., And the poly resistors 223 a. And the sum of resistances (via resistances) between the electrode pads 221 and the like, and is represented by Expression (5).
R ″ = ΣR _pad + ΣR _poly + ΣR _via (5)
ΣR _pad : sum of resistances of electrode pads 221 a, 221 b,... ΣR _poly : sum of resistances of poly resistors 223 a, 223 b... ΣR _via : sum of via resistances Of the three parameters shown in equation (5), In particular, the resistance value of the poly resistor 223a or the like is larger than that of the other two parameters, and there is a high possibility that an abnormal value appears suddenly.

Therefore, when evaluating the variation of poly resistance using the evaluation element 100 ″ having such a hole chain 220, the resistance value R ″ of the hole chain 220 at that time is increased while increasing the numerical value of x. Measure sequentially.
The relationship between the value of x and the resistance value R ″ is represented by a straight line, and the correlation coefficient and the slope of this straight line (relational expression) are obtained. Thereby, it is possible to know the variation in resistance per unit length of the poly resistor in each of the plurality of TEG formation regions 200 in the silicon wafer W. Then, from the result, it is possible to evaluate the variation of the poly resistance in the cell of the flash memory 300 for each formation position of the flash memory 300.

  In the third embodiment, the poly resistor 223a and the poly resistor 223b correspond to the structure under test of the present invention. Also, a combination of a poly resistor 223a, two plug electrodes 225 formed on the poly resistor 223a, and a pair of electrode pads 221 sandwiching the poly resistor 223a from both sides in plan view, a poly resistor The combination of 223b, two plug electrodes 225 formed on the poly resistor 223b, and a pair of electrode pads 221 sandwiching the poly resistor 223b from both sides in plan view corresponds to the evaluation pattern of the present invention. Yes.

The top view which shows the structural example of the evaluation element 100 which concerns on 1st Embodiment. The top view which shows the structural example of the hole chain 20, and AA 'arrow sectional drawing. FIG. 6 is a plan view illustrating an example of a formation position of an evaluation element 100. 9 is a flowchart showing a method for evaluating contact resistance using the evaluation element 100. Shows the chain number _n 1 ~n ₄ in hole chain 20, the relationship between the resistance value _R 1 to R _4. Sectional drawing which shows the structural example of the hole chain 120 which concerns on 2nd Embodiment. The top view which shows the structural example of the hole chain 220 which concerns on 3rd Embodiment, and BB 'arrow sectional drawing. The top view which shows the structural example of the evaluation element 90 which concerns on a prior art example.

Explanation of symbols

  2, 2a to 2e, 221 electrode pad, 20, 120, 220 hole chain, 21, 121 (upper layer metal) wiring, 23 impurity diffusion layer, 25, 125, 225 plug electrode, 27 element isolation layer, 29 interlayer insulating film, 123 Lower layer metal wiring, 124, 224 Insulating film, 223a to 223d Poly resistor, 100, 100 ′, 100 ″ Evaluation element, 300 Flash memory, H contact hole, h via hole, S scribe line, W wafer

Claims (4)

An evaluation element for evaluating resistance variation of a predetermined structure in an electronic device formed on a substrate,
A plurality of evaluation patterns including a structure under test of the same type as the predetermined structure,
The evaluation patterns are different from each other in the number of the structures to be tested included,
The evaluation element of an electronic device, wherein the evaluation patterns are formed close to each other in the substrate.   The evaluation element of an electronic device according to claim 1, wherein the evaluation patterns share the same structure under test. An evaluation element for evaluating resistance variation of a predetermined structure in an electronic device formed on a substrate,
A plurality of evaluation patterns including a structure under test of the same type as the predetermined structure,
The evaluation patterns are different from each other in the size of the structure to be tested,
The evaluation element of an electronic device, wherein the evaluation patterns are formed close to each other in the substrate. A method for evaluating resistance variation of a predetermined structure in an electronic device formed on a substrate,
4. The electronic device evaluation method according to claim 1, wherein the resistance values of the plurality of evaluation patterns included in the evaluation element of the electronic device according to claim 1 are respectively measured.

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