WO2023240596A1

WO2023240596A1 - Semiconductor test structure and test method thereof

Info

Publication number: WO2023240596A1
Application number: PCT/CN2022/099452
Authority: WO
Inventors: 钱龙
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-06-13
Filing date: 2022-06-17
Publication date: 2023-12-21
Also published as: CN117276247A

Abstract

The present disclosure relates to a semiconductor test structure and a test method thereof. The semiconductor test structure comprises: a substrate, and a first test part, a second test part and a third test part, which are arranged on one side of the substrate. The first test part is configured to test the electrical properties of a first test structure to obtain a first test result. The first test structure comprises: a conductive via hole, and a first conductive part and a second conductive part, which are located at two ends of the conductive via hole and connected to the conductive via hole. The second test part is configured to test the electrical properties of the first conductive part to obtain a second test result. The third test part is configured to test the electrical properties of the second conductive part to obtain a third test result. The electrical properties of the conductive via hole are determined according to the first test result, the second test result and the third test result. By means of the semiconductor test structure, a preparation process for a conductive via hole in the back end of line can be effectively monitored.

Description

Semiconductor test structure and test method

Cross-references to related applications

This disclosure claims priority to the Chinese patent with application number 202210663352. incorporated in this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor testing structure and a testing method thereof.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor memory commonly used in electronic equipment such as computers. It is composed of multiple storage units. Wherein, the storage unit includes: a storage capacitor and a transistor electrically connected to the storage capacitor.

When preparing DRAM, transistors can be prepared on the substrate in advance. After the transistors are prepared, a back end of line (BEOL) process needs to be performed to connect multiple transistors on the substrate according to design requirements through conductive vias and conductive pattern layers to achieve specific functions.

For subsequent processes, process monitoring during their execution is an important link. However, the test data obtained based on the existing test structure may not reflect some of the process problems in the subsequent processes.

Contents of the invention

According to various embodiments of the present disclosure, a semiconductor test structure and a test method thereof are provided.

According to some embodiments, one aspect of the present disclosure provides a semiconductor test structure, including: a substrate and first, second and third test parts respectively disposed on one side of the substrate. Wherein, the first testing part is configured to test the electrical performance of the first testing structure to obtain the first detection result. The first test structure includes: a conductive via hole, and a first conductive part and a second conductive part located at both ends of the conductive via hole and connected to the conductive via hole. The second testing part is configured to test the electrical performance of the first conductive part to obtain a second detection result. The third testing part is configured to test the electrical performance of the second conductive part to obtain a third detection result. Wherein, the electrical performance of the conductive via is determined based on the first detection result, the second detection result and the third detection result.

According to some embodiments, the first test part includes: a first test structure, and a first test pad correspondingly connected to the first conductive part and/or the second conductive part.

According to some embodiments, the conductive via hole includes an upper end surface and a lower end surface that are oppositely arranged. The first conductive part covers the upper end surface, and the distance between the boundary line of the first conductive part in at least one direction and the boundary line of the upper end surface in the same direction is less than the first threshold. The second conductive part covers the lower end surface, and the distance between the boundary line of the second conductive part in at least one direction and the boundary line of the lower end surface in the same direction is less than the second threshold.

According to some embodiments, the first threshold is 0.05 to 1 times the maximum radial dimension of the upper end surface. The second threshold is 0.05 to 1 times the maximum radial dimension of the lower end surface.

According to some embodiments, both the first conductive part and the second conductive part include: a plurality of test sections extending linearly. Wherein, any test section in the second conductive part is respectively connected to two test sections in the first conductive part through two conductive via holes; both ends of the first conductive part are respectively connected to the corresponding first test pads. .

According to some embodiments, the test section extends in the first direction. The second direction is orthogonal to the first direction. The distance in the second direction between the boundary line of the test section in the first conductive part and the boundary line of the upper end surface in the corresponding conductive via hole is less than the first threshold. The distance in the second direction between the boundary line of the test section in the second conductive part and the boundary line of the lower end surface in the corresponding conductive via hole is less than the second threshold.

According to some embodiments, the first test part includes: a plurality of first test structures arranged in parallel and spaced apart, and the plurality of first test structures are connected in series in sequence.

According to some embodiments, a plurality of first test structures are connected in series in a serpentine shape.

According to some embodiments, the second test part includes: a second test structure equivalent to the first conductive part, and a second test pad connected to the second test structure.

According to some embodiments, the first conductive part includes: a plurality of test sections extending linearly. The second test structure includes: a first test line extending linearly. Wherein, the length of the first test line is the same as the equivalent length of the first conductive part.

According to some embodiments, the length of the first test line is the same as the sum of the lengths of the plurality of test sections in the first conductive part; or, the difference between the length of the first test line and the sum of the lengths of the plurality of test sections in the first conductive part The value is less than or equal to the allowable deviation value.

According to some embodiments, the second test part includes: a plurality of second test structures arranged in parallel and spaced apart, and the plurality of second test structures are connected in series in sequence.

According to some embodiments, a plurality of second test structures are connected in series in a serpentine shape.

According to some embodiments, the second test structure and the first conductive portion are formed in one process.

According to some embodiments, the third test part includes: a third test structure equivalent to the second conductive part, and a third test pad connected to the third test structure.

According to some embodiments, the second conductive part includes: a plurality of test sections extending linearly. The third test structure includes: a second test line extending linearly. Wherein, the length of the second test line is the same as the equivalent length of the second conductive part.

According to some embodiments, the length of the second test line is the same as the sum of the lengths of the plurality of test sections in the second conductive part; or, the difference between the length of the second test line and the sum of the lengths of the plurality of test sections in the second conductive part The value is less than or equal to the allowable deviation value.

According to some embodiments, the third test part includes: a plurality of third test structures arranged in parallel and spaced apart, and the plurality of third test structures are connected in series in sequence.

According to some embodiments, the third test structure and the second conductive part are formed in one process.

According to some embodiments, some embodiments of another aspect of the present disclosure provide a semiconductor testing method, which is applied to the semiconductor testing structures in some of the foregoing embodiments. The semiconductor testing method includes the following steps.

Test the electrical performance of the first test structure to obtain the first test result; the first test structure includes: a conductive via hole, and a first conductive part and a second conductive part located at both ends of the conductive via hole and connected to the conductive via hole .

Test the electrical performance of the second test structure to obtain the second test result; the second test structure is equivalent to the first conductive part.

Test the electrical performance of the third test structure to obtain the third test result; the third test structure is equivalent to the second conductive part.

According to the first detection result, the second detection result and the third detection result, the electrical performance of the conductive via hole is determined.

Embodiments of the present disclosure may/at least have the following advantages:

In the embodiment of the present disclosure, a first test part, a second test part and a third test part are respectively provided in the semiconductor test structure, and the first test part can be used to test the electrical performance of the first test structure to obtain the first test result; The second test part is used to test the electrical performance of the first conductive part in the first test structure to obtain the second detection result; the third test part is used to test the electrical performance of the second conductive part in the first test structure to obtain the third detection result. result. In this way, after obtaining these three test results, the electrical properties of the conductive vias in the first test structure can be accurately determined based on these three test results to better monitor the effects of conductive via preparation in subsequent processes. problems, thus helping to speed up the research and development process.

In addition, if the first conductive part and the second conductive part in the semiconductor test structure adopt the same size and preparation process as the conductive layer adjacent to the conductive via hole in DRAM, then the semiconductor test structure can also be used to determine the first conductive part and the second conductive part accordingly. The electrical properties of the second conductive part. In this way, problems caused by the preparation of the conductive layer in subsequent processes can be better monitored.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. Those of ordinary skill in the art can also obtain drawings of other embodiments based on these drawings without exerting creative efforts.

Figure 1 is a schematic cross-sectional view of conductive vias and conductive patterns in a DRAM;

Figure 2 is a schematic top view of a semiconductor test structure provided in an embodiment;

Figure 3 is a schematic cross-sectional view of a first test structure in a semiconductor test structure provided by an embodiment;

Figure 4 is a schematic cross-sectional view of a second test structure in a semiconductor test structure provided by an embodiment;

Figure 5 is a schematic cross-sectional view of a third test structure in a semiconductor test structure provided by an embodiment;

Figure 6 is a schematic cross-sectional view of the first test structure in Figure 3 along the A-A’ direction;

Figure 7 is a schematic top view of each structure after decomposition of a first test structure provided by an embodiment;

Figure 8 is a schematic cross-sectional view of a first test portion in a semiconductor test structure provided in an embodiment;

Figure 9 is a schematic cross-sectional view of the first test portion in another semiconductor test structure provided by an embodiment;

Figure 10 is a schematic cross-sectional view of the first test portion in yet another semiconductor test structure provided by an embodiment;

Figure 11 is a schematic cross-sectional view of a second test portion in a semiconductor test structure provided in an embodiment;

Figure 12 is a schematic cross-sectional view of a third testing portion in a semiconductor testing structure provided in an embodiment;

Figure 13 is a schematic top view of the first test portion in a semiconductor test structure provided in an embodiment;

Figure 14 is a schematic top view of a second test portion in a semiconductor test structure provided in an embodiment;

Figure 15 is a schematic top view of a third test portion in a semiconductor test structure provided in an embodiment;

FIG. 16 is a schematic flowchart of a semiconductor testing method according to an embodiment.

Detailed ways

To facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. There is illustrated in the accompanying drawings a preferred embodiment of the present disclosure. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer.

It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the invention; for example, a first element, component, region, layer, doping type or section could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; The first doping type becomes the second doping type, and similarly, the second doping type can become the first doping type; the first doping type and the second doping type are different doping types, for example, The first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "consist" and/or "comprise" are used in this specification, the presence of stated features, integers, steps, operations, elements and/or parts may be identified but not to the exclusion of one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown are contemplated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the specific shapes of the regions shown herein but include deviations in shapes due, for example, to manufacturing techniques. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its boundary lines rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the invention.

When preparing DRAM, transistors can be prepared on the substrate in advance. After the transistors are prepared, subsequent processes need to be performed to connect multiple transistors on the substrate according to design requirements through conductive vias and conductive pattern layers, so that specific functions can be achieved.

For example, please refer to Figure 1. In DRAM, it can be understood that on the substrate 1 on which the transistors are prepared, each transistor and other conductive structures (such as conductive lines, capacitors or resistors, etc.) can be connected in series and parallel to form multiple Circuits with different functions. Each circuit is not shown in FIG. 1 , and only the substrate 1 and the first layer conductive pattern M0 located on the surface of the substrate 1 are used as illustrations. Here, the first layer conductive pattern M0 can be regarded as the lead-out terminal of the corresponding transistor on the substrate 1 . Based on this, by matching the structure of the DRAM and the conductive requirements of each circuit on the substrate 1, and performing subsequent processes on the substrate 1, a multi-layer conductive pattern (such as M1 in Figure 1) located above the first layer conductive pattern M0 can be formed. , M2, M3 and M4), and conductive vias located between any two adjacent layers of conductive patterns (such as V1, V2, V3 and V4 in Figure 1). The first conductive via V1 is used to realize the corresponding connection between the first layer conductive pattern M0 and the second layer conductive pattern M1. The second conductive via V2 is used to realize the corresponding connection between the second layer conductive pattern M1 and the third layer conductive pattern M2. The third conductive via V3 is used to realize the corresponding connection between the third layer conductive pattern M2 and the fourth layer conductive pattern M3. The fourth conductive via V4 is used to realize the corresponding connection between the fourth layer conductive pattern M3 and the fifth layer conductive pattern M4. The conductive patterns of adjacent layers and the adjacent conductive via holes are insulated from each other by an insulating material Ins.

Moreover, conductive vias located in different layers can be designed and prepared using different parameters, and conductive patterns located in different layers can also be designed and prepared using different parameters, thereby facilitating the interaction between each conductive via hole and the conductive pattern of each layer. Designed to implement circuits with specific functions.

It is understandable that during the execution of subsequent processes, problems that may affect DRAM product yield may easily occur. For example, when forming a conductive pattern layer covering a conductive via hole, it may happen that the conductive via hole and the adjacent conductive pattern layer are not completely connected together, that is, between the conductive via hole and the adjacent conductive pattern layer There may be partial open circuits. For another example, during the process of forming conductive vias, there may be voids in some of the conductive vias.

In some embodiments, the test structure used to test the conductive vias usually tests the conductive vias and adjacent conductive pattern layers together, and designs the area of the adjacent conductive pattern layers to be larger, so that the adjacent conductive patterns The influence of layers on the electrical performance test results of conductive vias can be ignored. In this way, when there is a void in the conductive via hole or there is a partial open circuit between the conductive via hole and the adjacent conductive pattern layer, there will be no obvious abnormalities in the test data obtained by the test structure detection. This means that the test data obtained based on this test structure can hardly reflect the above-mentioned problems existing in the subsequent processes.

Therefore, for subsequent processes, the ability to perform better process monitoring during their execution is an important link, which can easily affect the production yield of DRAM.

From the above, embodiments of the present disclosure provide a semiconductor test structure. The conductive pattern layers adjacent to the conductive vias in the test structure are designed. The influence of the adjacent conductive pattern layers on the electrical performance test results of the conductive vias can be used as a measurement factor. One of them is measured to better accurately monitor the preparation process of the conductive vias and adjacent conductive pattern layers.

In some embodiments, please refer to FIG. 2 and FIG. 3 . The semiconductor test structure includes: a substrate 1 and a first test part 2 , a second test part 3 and a third test part 4 respectively provided on one side of the substrate 1 . Wherein, the first testing part 2 is configured to test the electrical performance of the first testing structure 21 to obtain the first detection result. The second testing part 3 is configured to test the electrical performance of the first conductive part 212 to obtain a second detection result. The third testing part 4 is configured to test the electrical performance of the second conductive part 213 to obtain a third detection result. Wherein, the electrical performance of the conductive via 211 is determined based on the first detection result, the second detection result and the third detection result.

The above-mentioned first test structure 21 includes: a conductive via 211, and a first conductive part 212 and a second conductive part 213 located at both ends of the conductive via 211 and connected to the conductive via 211.

By way of example, the substrate 1 includes, but is not limited to, a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon nitride substrate. Transistors and other electronic components may also be provided within the substrate 1. The axis of the conductive via 211 is perpendicular to the substrate 1 (that is, the axis of the conductive via 211 extends along the Z direction). An insulating layer is provided between the first conductive part 212 and the second conductive part 213, and the first conductive part 212, the insulating layer and the second conductive part 213 are sequentially stacked in the direction away from the substrate, and the conductive via hole is formed in the insulating layer. , and connected to the first conductive part and the second conductive part on both sides of the insulating layer.

For example, the conductive via 211 may be a metal via with good conductivity, such as a tungsten via or a copper via. The cross-sectional shape of the conductive via 211 along the direction perpendicular to the substrate 1 includes but is not limited to rectangle, square, trapezoid, etc.

For example, both the first conductive part 212 and the second conductive part 213 may be made of a metal material with good conductive properties, such as copper, gold, silver, aluminum, titanium or alloys thereof. Both the first conductive part 212 and the second conductive part 213 may be patterned and formed by a conductive layer.

Please refer to FIG. 4 , the above-mentioned second test part 3 includes: a second test structure 31 equivalent to the first conductive part 212 . The second test structure 31 can be formed using the same material and the same process as the first conductive portion 212, and has an equivalent structure.

Please refer to FIG. 5 . The above-mentioned third test part 4 includes: a third test structure 41 equivalent to the second conductive part 213 . The third test structure 41 can be formed using the same material and the same process as the second conductive portion 213, and has an equivalent structure.

It should be noted that the equivalence mentioned in some of the above embodiments means that both equivalent parties can have the same electrical properties, such as the same electrical parameters. Moreover, the structures of the equivalent parties can be matched in design, for example, using the same design or a similar design, and verified through experiments to ensure that they are equivalent.

In embodiments of the present disclosure, the electrical properties may be target electrical parameters corresponding to the conductive structure, such as resistance value, current value or voltage value, etc. For convenience of description, in some of the following embodiments, the electrical performance to be measured is the resistance value of the corresponding conductive structure.

In some examples, the resistance value of the conductive via 211 may be determined according to the following method. Here, the conductive via 211 in the first test structure 21 is taken as an example. The resistance value of the conductive via 211 can be regarded as the contact resistance value with the corresponding conductive part.

First, the overall resistance of the first test structure 21 is tested based on the first test part 2 , that is, the sum R1 of the resistance values of the conductive via 211 , the first conductive part 212 and the second conductive part 213 (first detection result). Then, the resistance value R2 of the first conductive part 212 is tested based on the second testing part 2 (second detection result). The resistance value R3 of the second conductive part 212 is tested based on the third testing part 4 (third detection result). In this way, the value of R1 minus R2 and then minus R3 can be used to characterize the resistance value of the conductive via 211 .

Optionally, please continue to refer to FIG. 3 , a plurality of conductive vias 211 are provided in the first test structure 21 , and accordingly, both the first conductive part 212 and the second conductive part 213 adopt: multiple test vias extending linearly. segments (T1 and T2). Wherein, both ends of the first conductive part 212 are respectively connected to the corresponding first test pads 22 . Any test section T2 in the second conductive part 213 is connected to the two test sections T1 in the first conductive part 212 through two conductive vias 211 respectively. In this way, the test section T1 of the first conductive part 211 , the conductive via hole 211 and the test section T2 of the second conductive part 213 can be connected in series in order to form the first test structure 21 . On this basis, the overall resistance of the first test structure 21 tested by the first test part 2 includes the resistance values of the plurality of conductive vias 211 . Therefore, the value calculated using the aforementioned method (ie: R1-R2-R3) needs to be divided by the number of conductive vias 211 before it can be used to characterize the resistance value of the conductive vias 211.

From the above, after testing using the above test method, if the obtained resistance value of the conductive via hole 211 deviates greatly from the resistance reference value of the conductive via hole 211 , it means that there may be an abnormality in the preparation process of the conductive via hole 211 . In this way, by comparing the obtained resistance value of the conductive via hole 211 with the resistance reference value, it is possible to analyze and determine whether there is an abnormality in the conductive via hole 211 and what kind of abnormality may exist based on the difference between the two. For example, the resistance reference value is an average value or a reasonable value range of the resistance values of the conductive vias 211 determined through multiple preparation processes and tests (excluding abnormal test results).

In addition, in the embodiment of the present disclosure, multiple conductive vias 211 are provided in the first test structure 21. By measuring the total resistance values of the multiple conductive vias 211 and then averaging the values, the conductivity can be effectively improved by increasing the number of samples. The accuracy of the resistance value detection of the via 211 is evaluated, and the stability of the preparation process of the conductive via 211 is evaluated.

It should be noted that the semiconductor test structure provided by the embodiment of the present disclosure is an independent test structure. The conductive via 211 in the semiconductor test structure can be obtained by referring to the size and preparation process of the conductive via in DRAM. For example, the semiconductor test structure The size and preparation process of the conductive vias 211 in the structure and the conductive vias in the DRAM are the same. That is to say, the semiconductor test structure in the embodiment of the present disclosure can be used as a simulation structure to test the electrical performance of the conductive via 211, the first conductive part 212 and the second conductive part 213 through the semiconductor test structure, and evaluate accordingly. The electrical properties of conductive vias in DRAM can be effectively monitored during the preparation process of conductive vias.

It should be added that in the embodiment of the present disclosure, for the size design of the conductive via 211 in the semiconductor test structure, the minimum process size feasible under the same manufacturing process conditions can be selected. In this way, under the same preparation process conditions, if the electrical performance of the conductive via 211 designed with the minimum process size can be tested and qualified after preparation, then for the conductive via 211 designed with a larger process size, it will be prepared using the same preparation process. Finally, its electrical performance qualification rate can also be guaranteed.

In addition, the semiconductor test structure provided by the embodiment of the present disclosure can be directly incorporated into the wafer acceptance test (Wafer Acceptance Test, WAT for short). That is, the test data of the electrical properties of the conductive via 211 can be obtained through the WAT test, and the preparation process of the conductive via 211 can be monitored simultaneously.

To sum up, in the embodiment of the present disclosure, the first test part 2, the second test part 3 and the third test part 4 are respectively provided in the semiconductor test structure. The first test part 2 can be used to test the electrical performance of the first test structure 21, so as to Obtain the first test result; use the second test part 3 to test the electrical performance of the first conductive part 212 in the first test structure 21 to obtain the second test result; use the third test part 4 to test the second conductive part 212 in the first test structure 21 The electrical performance of the conductive part 213 is used to obtain the third detection result. In this way, after obtaining these three test results, the electrical properties of the conductive vias 211 in the first test structure 21 can be accurately determined based on these three test results to better monitor the preparation of the conductive vias in subsequent processes. problems, thus helping to speed up the research and development process.

In addition, if the first conductive part 212 and the second conductive part 213 in the semiconductor test structure adopt the same size and preparation process as the conductive layer adjacent to the conductive via in DRAM, then the semiconductor test structure can also be used to determine the first conductive part accordingly. part 212 and the second conductive part 213. In this way, problems caused by the preparation of the conductive layer in subsequent processes can be better monitored.

It is worth mentioning that the first test part 2 is used to test the overall electrical performance of the first test structure 21 , that is, the first conductive part 212 and the second conductive part 213 can be used to test the electrical performance test results of the first test structure 21 The influence is one of the measurement factors. This also means that the structural design of the first conductive part 212 and the second conductive part 213 needs to meet this principle.

Referring to FIG. 3 , FIG. 6 and FIG. 7 , in some embodiments, the conductive via 211 includes an upper end surface S1 and a lower end surface S2 arranged oppositely. The first conductive part 212 covers the upper end surface S1, and the distance between the boundary line of the first conductive part 212 in at least one direction and the boundary line of the upper end surface S1 in the same direction is less than the first threshold. The second conductive part 213 covers the lower end surface S2, and the distance between the boundary line of the second conductive part 213 in at least one direction and the boundary line of the lower end surface S2 in the same direction is less than the second threshold.

Here, combined with the arrangement positions of the first conductive part 212 and the second conductive part 213, the distance between the boundary line corresponding to at least one direction and the boundary line in the same direction of the end surface contacted by the conductive via hole 211 is small, so that The first conductive part 212 and the second conductive part 213 have smaller process dimensions in at least one vertical direction. The at least one direction is, for example, the extending direction of the first conductive part 212 and the second conductive part 213 (for example, the X direction). For example, in the example where the first conductive part 212 and the second conductive part 213 are test lines, the at least one direction is the length direction of the first conductive part 212 and the second conductive part 213, so that the first conductive part 212 and the second conductive part 213 can be The conductive portion 213 has a smaller process size in the width direction.

In addition, the above-mentioned first threshold and second threshold can be selected and set according to actual needs, as long as the first conductive part 212 and the second conductive part 213 will affect the test results of the first test structure 21 .

For example, the first threshold is 0.05 times to 1 times the maximum radial dimension of the upper end surface S1, such as 0.05 times, 0.1 times, 0.3 times, 0.6 times, 0.9 times or 1 times. The second threshold is 0.05 times to 1 times the maximum radial dimension of the lower end surface S2, for example, 0.05 times, 0.1 times, 0.3 times, 0.6 times, 0.9 times or 1 times.

It can be understood that the shapes of the upper end surface S1 and the lower end surface S2 of the conductive via 211 may be the same or similar, and the shapes of the upper end surface S1 and the lower end surface S2 may be regular shapes or irregular shapes. Optionally, the shapes of the upper end surface S1 and the lower end surface S2 of the conductive via hole 211 are circular, elliptical, rectangular or irregular shapes. Correspondingly, the maximum radial size of the upper end surface S1 and the lower end surface S2 may be the size between the two farthest boundary points that pass through the geometric center. Optionally, the maximum radial size of the upper end surface S1 and the lower end surface S2 is located in the vertical direction (for example, Y direction) of the extending direction of the first conductive part 212 and the second conductive part 213 .

In some examples, the maximum radial dimension of the end surface S1 of the conductive via 211 ranges from 40 nm to 250 nm, such as 40 nm, 80 nm, 120 nm, 180 nm, 220 nm or 250 nm. The maximum radial size of the lower end surface S2 of the conductive via 211 ranges from 40 nm to 250 nm, such as 40 nm, 80 nm, 120 nm, 180 nm, 220 nm or 250 nm.

In the embodiment of the present disclosure, the first conductive part 212 and the second conductive part 213 respectively cover the two end surfaces of the conductive via hole 211, which can ensure that the space between the conductive via hole 211 and the first conductive part 212, and the distance between the conductive via hole 211 and the conductive via hole 211 are ensured. There is good contact between the second conductive parts 213 . Moreover, by defining the boundary line of the first conductive part 212 and the second conductive part 213, the present disclosure can ensure that the first conductive part 212 and the second conductive part 213 have smaller process dimensions in at least one direction, thereby ensuring The first conductive part 212 and the second conductive part 213 will affect the test results of the first test structure 21 and help reduce the space occupied by the semiconductor test structure.

In order to explain the embodiments of the present disclosure more clearly, some of the following embodiments describe in detail a semiconductor test structure in which a plurality of conductive vias 211 are provided in the first test structure 21 .

Referring to FIGS. 8 to 10 , in some embodiments, the first conductive part 212 includes a plurality of first test sections T1 , and the second conductive part 213 includes a plurality of second test sections T2 . Wherein, the first test section T1 and the second test section T2 both extend along the first direction (for example, the X direction). The distance H1 between the boundary line extending in the X direction of the first test section T1 and the boundary line with the upper end surface of the corresponding conductive via hole 211 in the same direction is less than the first threshold, and the distance H1 is located in the second direction (for example, the Y direction) . The distance H2 between the boundary line extending in the X direction of the second test section T2 and the boundary line in the same direction as the lower end surface of the corresponding conductive via hole 211 is less than the second threshold, and the distance H2 is located in the second direction (for example, the Y direction). In this way, it is ensured that both the test section in the first conductive part 212 and the test section in the second conductive part 213 have smaller process dimensions in the second direction.

Please continue to refer to Figures 8 to 10. In some embodiments, the first test part 2 includes: a first test structure 21, and a first test solder correspondingly connected to the first conductive part 212 and/or the second conductive part 213. Plate 22. Here, the first test pads 22 are used to form a conductive path with the first test structure 21 . The number of the first test pads 22 can be two, and they are respectively connected to two ends of the first test structure 21 . The first test pad 22 may have a single-layer structure or a stacked structure. For example, the first test pad 22 has a single-layer structure; the first test pad 22 can be formed simultaneously with the first conductive portion 212 or with the second conductive portion 213. For example, the first test pad 22 has a laminated structure; the first test pad 22 includes: two pad conductive layers 222 arranged in the same layer as the first conductive part 212 and the second conductive part 213, and a conductive layer 222 with a conductive layer. The connection via hole 221 is provided in the same layer as the hole 211, and the connection via hole 221 connects the two aforementioned pad conductive layers 222. In the embodiment of the present disclosure, by setting the first test pad 22, it is convenient to contact the first test pad 22 with the test probe used for electrical testing to test the electrical performance of the first test structure 21. . For example, the area of the first test pad 22 is relatively large, and its resistance can be ignored during the electrical test; the second test pad 32 and the third test pad 42 that will be introduced below are different from the first test pad 22 . Disk 22 is similar and will not be repeated later.

There can be many different connection methods between the first test structure 21 and the first test pad 22 . In actual application, the corresponding connection method can be selected according to needs. Referring to FIG. 8 , in some examples, two first test pads 22 are located on both sides of the first test structure 21 and are respectively connected to two ends of the first conductive part 212 . Referring to FIG. 9 , in other examples, two first test pads 22 may be connected to two ends of the second conductive part 213 respectively. Referring to FIG. 10 , in some further examples, one of the two first test pads 22 is connected to one end of the first conductive part 212 , and the other is connected to one end of the second conductive part 213 . That is, the first test pad 22 can be connected to the first conductive part 212 or the second conductive part 213. This depends on whether the first test structure 21 is led out through the first conductive part 212 or the second conductive part 213 .

Some of the foregoing embodiments have introduced the relevant content of the first test part 2 in the semiconductor test structure of the present disclosure. Next, the relevant contents of the second test part 3 and the third test part 4 in the semiconductor test structure of the present disclosure will be described in detail.

Referring to FIG. 11 , in some embodiments, the second test part 3 includes: a second test structure 31 equivalent to the first conductive part 212 , and a second test pad 32 connected to the second test structure 31 . The structure and function of the second test pad 32 can be set with reference to the structure and function of the aforementioned first test pad, and will not be described again here.

In some embodiments, the first conductive part 212 includes: a plurality of test sections (first test sections T1) extending linearly. The second test structure 31 includes: a first test line L1 extending linearly. Since the second test part 3 can use the first test line L1 to test the electrical performance of the first conductive part 212 , the first test line L1 has a structure equivalent to the electrical performance of the first conductive part 212 . For example, the first test line L1 and the first conductive part 212 are formed using the same material and the same preparation process, and the first test line L1 and the first conductive part 212 may have the same or similar deposition thickness. For example, the first test line L1 and the first conductive portion 212 have the same or similar shape. For example, the width of the first test line L1 is the same as the width of the first conductive portion 212 . For example, the length of the first test line L1 is the same as the equivalent length of the first conductive part 212 .

Here, the length of the first test line L1 is the same as the equivalent length of the first conductive part 212, which can be expressed as: the length of the first test line L1 is the same as the sum of the lengths of the multiple test sections in the first conductive part 212; Or, the difference between the length of the first test line L1 and the sum of the lengths of the plurality of test sections in the first conductive part 212 is less than or equal to the allowable deviation value. The allowable deviation value can be determined according to actual requirements to ensure the equivalence of electrical performance between the first test line L1 and the first conductive part 212 .

In the embodiment of the present disclosure, based on the fact that the conductive length is the main influencing factor on the electrical performance of the first test line L1 and the first conductive part 212, by designing the length of the first test line L1 and the equivalent length of the first conductive part 212 to be the same, It is beneficial to ensure that the first test line L1 and the first conductive part 212 can have equivalent electrical properties, so that the second test part 3 can test the electrical performance of the first conductive part 212 through the first test line L1.

In some embodiments, the second test structure 31 and the first conductive portion 212 are formed in one process. In this way, it is helpful to simplify the preparation process of the semiconductor test structure and shorten the preparation process.

Referring to FIG. 12 , in some embodiments, the third test part 4 includes: a third test structure 41 equivalent to the second conductive part 213 , and a third test pad 42 connected to the third test structure 41 . The structure and function of the third test pad 42 can be set with reference to the structure and function of the aforementioned first test pad, and will not be described again here.

In some embodiments, the second conductive part 213 includes: a plurality of test sections (second test sections T2) extending linearly. The third test structure 41 includes: a second test line L2 extending linearly. Since the third testing part 4 can use the second test line L2 to test the electrical performance of the second conductive part 213 , the second test line L2 has a structure equivalent to the electrical performance of the second conductive part 213 . For example, the second test line L2 and the second conductive part 213 are formed using the same material and the same preparation process, and the second test line L2 and the second conductive part 213 may have the same or similar deposition thickness. For example, the second test line L2 and the second conductive part 213 have the same or similar shape. For example, the width of the second test line L2 is the same as the width of the second conductive portion 213 . For example, the length of the second test line L2 is the same as the equivalent length of the second conductive part 213 .

Here, the length of the second test line L2 is the same as the equivalent length of the second conductive part 213, which can be expressed as: the length of the second test line L2 is the same as the sum of the lengths of the multiple test sections in the second conductive part 213; Or, the difference between the length of the second test line L2 and the sum of the lengths of the plurality of test sections in the second conductive part 213 is less than or equal to the allowable deviation value. The above allowable deviation value can be determined according to actual requirements to ensure the equivalence of electrical performance between the second test line L2 and the second conductive part 213 .

In the embodiment of the present disclosure, the conductive length is the main influencing factor on the electrical performance of the second test line L2 and the second conductive part 213. Therefore, the length of the second test line L2 is the same as the equivalent length of the second conductive part 213, which is beneficial to It is ensured that the second test line L2 and the second conductive part 213 can have equivalent electrical properties, so that the third test part 4 can test the electrical performance of the second conductive part 213 through the second test line L2.

In some embodiments, the third test structure 41 and the second conductive portion 213 are formed in one process. In this way, it is helpful to simplify the preparation process of the semiconductor test structure and shorten the preparation process.

It should be understood that the first test part 2, the second test part 3 and the third test part 4 in the embodiment of the present disclosure may each include only one corresponding test structure, or may include multiple corresponding test structures, where No restrictions.

Referring to FIG. 13 , in some embodiments, the first test part 2 includes: a plurality of first test structures 21 arranged in parallel and spaced apart, and the plurality of first test structures 21 are connected in series in sequence.

By way of example, multiple first test structures 21 are connected in series in a serpentine shape. Among the plurality of first test structures 21 connected in series, the first test structure 21 located at the head is connected to one first test pad 22 , and the first test structure 21 located at the tail is connected to another first test pad 22 .

Referring to FIG. 14 , in some embodiments, the second test part 3 includes: a plurality of second test structures 31 arranged in parallel and spaced apart, and the plurality of second test structures 31 are connected in series in sequence.

By way of example, multiple second test structures 31 are connected in series in a serpentine shape. Among the plurality of second test structures 31 connected in series, the second test structure 32 located at the head is connected to a second test pad 32 , and the second test structure 31 located at the tail is connected to another first test pad 32 .

Referring to FIG. 15 , in some embodiments, the third test part 4 includes: a plurality of third test structures 41 arranged in parallel and spaced apart, and the plurality of third test structures 41 are connected in series in sequence.

By way of example, a plurality of third test structures 41 are connected in series in a serpentine shape. Among the plurality of third test structures 41 connected in series, the third test structure 41 located at the head is connected to one third test pad 42 , and the third test structure 41 located at the tail is connected to another third test pad 42 .

In the embodiment of the present disclosure, the first test part 2, the second test part 3 and the third test part 4 each include a plurality of corresponding test structures, and the test structures in each test part can be connected in series in sequence. In this way, the space occupied by the corresponding test portion on the substrate 1 can be reduced.

In some embodiments, the number of the second test structures 31 is the same as the number of the first conductive parts 212 , and the number of the third test structures 41 is the same as the number of the second conductive parts 213 . In this way, it can be ensured that the sum of the resistance values of the plurality of second test structures 31 is the same as the sum of the resistance values of the plurality of first conductive parts 212 , and the sum of the resistance values of the plurality of third test structures 41 is the same as the sum of the resistance values of the plurality of second conductive parts 212 . The sum of the resistance values of parts 213 is the same.

It should be noted that the first test part 2 includes a plurality of first test structures 21 , and each first test structure 21 includes a plurality of conductive vias 211 . In this way, the resistance value of the conductive via hole 211 calculated based on the first detection result, the second detection result and the third detection result includes the resistance value of all the conductive via holes 211 . Therefore, the resistance value of each conductive via hole 211 needs to be divided by the number of conductive via holes 211 to determine the resistance value of each conductive via hole 211 .

Referring to FIGS. 13 to 15 , in some embodiments, a redundant test structure (ie, Dummy area) that is not connected to other test structures may also be provided at the edge of each test part. These redundant test structures are located at the edge of the corresponding test part and can be formed synchronously with each test structure in the test part. In this way, among the multiple test structures formed simultaneously, some test structures located in the central area are selected to be connected to form a test part, which can ensure that the corresponding test part has high structural stability and process accuracy, thereby conducive to improving the semiconductor test structure test accuracy.

It should be understood that the semiconductor test structures in some of the foregoing embodiments can be used to test the electrical performance of any layer of conductive vias in DRAM. Since the structural parameters and process parameters of conductive vias in different layers of DRAM may be different, the semiconductor test structure provided by the embodiment of the present disclosure needs to be designed and prepared by matching the structural parameters and process parameters of the conductive vias of the layer to be tested, so as to facilitate More accurately monitor the electrical properties of conductive vias in the layer to be measured.

For example, please understand in conjunction with Figure 1 that the number of layers of conductive vias in DRAM is 4. The first direction is the X direction, the second direction is the Y direction, and the first direction and the second direction are orthogonal.

For example, the parameters of the semiconductor test structure used to test the first layer conductive via V1 in the DRAM can be set as follows. It should be added that the values of each of the following parameters can fluctuate within a range of 5% above and below the stated values, and are not limited thereto.

The maximum size of the conductive via 211 along the first direction is 50 nm, and the maximum size along the second direction is 37 nm. In the first direction, the distance between two adjacent conductive via holes 211 is 945 nm, and in the second direction, the distance between two adjacent conductive via holes 211 is 154 nm. Furthermore, the conductive vias 211 are arranged in rows (for example, 10 rows) along the first direction and in columns (for example, 30 columns) along the second direction. The number of the conductive vias 211 is, for example, 300.

The size of the test section in the first conductive part 212 along the first direction is 1918 nm, and the size along the second direction is 136 nm. In the first direction, the distance between two adjacent test sections in the first conductive part 212 is 72 nm. In the second direction, the distance between two adjacent test sections in the first conductive part 212 is 55 nm. Furthermore, the test segments in the first conductive part 212 are arranged in rows (for example, 10 rows) along the first direction and in columns (for example, 15 columns) along the second direction. For the corresponding connection between the test section and the conductive via 211 in the first conductive part 212, please refer to the relevant descriptions in some of the foregoing embodiments. The number of test segments in the first conductive part 212 is, for example, 150. The distance between the boundary line of the test section extending in the first direction in the first conductive part 212 and the boundary line of the conductive via hole 211 in the same direction is 49 nm. The distance between the boundary line of the test section in the first conductive part 212 extending in the second direction and the boundary line of the conductive via hole 211 in the same direction is 436 nm.

The size of the test section in the second conductive part 213 along the first direction is 1090 nm, and the size along the second direction is 65 nm. In the first direction, the distance between two adjacent test sections in the second conductive part 213 is 900 nm. In the second direction, the distance between two adjacent test sections in the second conductive part 213 is 125 nm. Furthermore, the test segments in the second conductive part 213 are arranged in rows (for example, 10 rows) along the first direction and in columns (for example, 15 columns) along the second direction. For the corresponding connection between the test section and the conductive via 211 in the second conductive part 213, please refer to the relevant descriptions in some of the foregoing embodiments. The number of test segments in the second conductive part 213 is, for example, 150. The distance between the boundary line of the test section in the second conductive part 213 extending in the first direction and the boundary line of the conductive via hole 211 in the same direction is 15 nm. The distance between the boundary line of the test section extending in the second direction in the second conductive part 213 and the boundary line of the conductive via hole 211 in the same direction is 22 nm.

The size of the second test structure 31 along the first direction is 12886 nm, and the size along the second direction is 136 nm. In the second direction, the spacing between two adjacent second test structures is 55 nm.

The size of the third test structure 41 along the first direction is 12886 nm, and the size along the second direction is 65 nm. In the second direction, the distance between two adjacent third test structures 41 is 125 nm.

It can be understood that the parameters of the semiconductor test structure used to test the second layer conductive via V2, the third layer conductive via V3 and the fourth layer conductive via V4 in DRAM can be set according to actual needs. For example, you can refer to The method of setting the parameters of the semiconductor test structure used to test the first layer conductive via V1 in the DRAM, but is not limited to this.

Referring to Figure 16, the semiconductor testing method includes steps S10 to S40.

S10, test the electrical performance of the first test structure to obtain the first test result; the first test structure includes: a conductive via hole, and a first conductive part and a second conductive part located at both ends of the conductive via hole and connected to the conductive via hole. Conductive part.

S20, test the electrical performance of the second test structure to obtain the second test result; the second test structure is equivalent to the first conductive part.

S30, test the electrical performance of the third test structure to obtain the third test result; the third test structure is equivalent to the second conductive part.

S40: Determine the electrical performance of the conductive via according to the first detection result, the second detection result and the third detection result.

The technical effects that can be achieved by the semiconductor testing structures in some of the foregoing embodiments can also be achieved by this semiconductor testing method, and will not be described in detail here.

In some examples, the resistance value of the conductive via can be determined according to the following method. Here, the conductive via in the first test structure is used as an example.

First, the resistance of the entire first test structure is tested based on the first test part, that is, the sum of the resistance values R1 of the conductive via, the first conductive part, and the second conductive part (first detection result). Then, the resistance value R2 of the first conductive part is tested based on the second test part (second detection result). The resistance value R3 of the second conductive part is tested based on the third test part (third detection result). In this way, the value of R1 minus R2 and then minus R3 can be used to characterize the resistance value of the conductive via.

Optionally, a plurality of conductive vias are provided in the first test structure. Correspondingly, both the first conductive part and the second conductive part adopt a plurality of test sections extending linearly. Wherein, two ends of the first conductive part are respectively connected to the corresponding first test pads. Any test section in the second conductive part is connected to the two test sections in the first conductive part through two conductive via holes. In this way, the test section of the first conductive part, the conductive via hole, and the test section of the second conductive part can be connected in series to form the first test structure. On this basis, the overall resistance of the first test structure tested by the first test part includes resistance values of multiple conductive vias. Therefore, the value calculated using the aforementioned method (ie: R1-R2-R3) needs to be divided by the number of conductive vias before it can be used to characterize the resistance value of the conductive vias.

From the above, after testing using the above test method, if the obtained resistance value of the conductive via hole deviates greatly from the resistance reference value of the conductive via hole, it means that there may be an abnormality in the preparation process of the conductive via hole. In this way, by comparing the obtained resistance value of the conductive via with the resistance reference value, it is possible to analyze and determine whether there is an abnormality in the conductive via and what kind of abnormality may exist based on the difference between the two. For example, the resistance reference value is the average value or a reasonable value range of the resistance values of the conductive vias determined through multiple preparation processes and tests (excluding abnormal test results).

In addition, in the embodiment of the present disclosure, multiple conductive vias are provided in the first test structure. By measuring the total resistance values of the multiple conductive vias and then averaging the values, the conductive via resistance can be effectively increased by increasing the number of samples. The accuracy of value detection was evaluated, and the stability of the conductive via preparation process was evaluated.

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed should be determined by the appended claims.

Claims

A semiconductor test structure, including: a substrate and a first test part, a second test part and a third test part respectively provided on one side of the substrate; wherein,

The first test part is configured to: test the electrical performance of the first test structure to obtain a first detection result; the first test structure includes: a conductive via, and a conductive via located at both ends of the conductive via and connected to the conductive via. The first conductive part and the second conductive part connected by the conductive via hole;

The second testing part is configured to: test the electrical performance of the first conductive part to obtain a second detection result;

The third testing part is configured to: test the electrical performance of the second conductive part to obtain a third detection result;

Wherein, the electrical performance of the conductive via hole is determined based on the first detection result, the second detection result and the third detection result.
The semiconductor test structure according to claim 1, wherein the first test part includes: the first test structure, and a first conductive part correspondingly connected to the first conductive part and/or the second conductive part. Test pad.
The semiconductor test structure according to claim 2, wherein the conductive via hole includes an upper end surface and a lower end surface arranged oppositely;

The first conductive part covers the upper end surface, and the distance between the boundary line of the first conductive part in at least one direction and the boundary line of the upper end surface in the same direction is less than a first threshold;

The second conductive part covers the lower end surface, and a distance between a boundary line of the second conductive part in at least one direction and a boundary line of the lower end surface in the same direction is less than a second threshold.
The semiconductor test structure of claim 3, wherein

The first threshold is 0.05 to 1 times the maximum radial dimension of the upper end surface;

The second threshold is 0.05 to 1 times the maximum radial dimension of the lower end surface.
The semiconductor test structure according to claim 3, wherein the first conductive part and the second conductive part each include: a plurality of test sections extending linearly;

Wherein, any one of the test sections in the second conductive part is correspondingly connected to the two test sections in the first conductive part through two conductive via holes;

Two ends of the first conductive part are respectively connected to the corresponding first test pads.
The semiconductor test structure of claim 5, wherein

The test section extends along the first direction; the second direction is orthogonal to the first direction;

The distance in the second direction between the boundary line of the test section in the first conductive part and the boundary line corresponding to the upper end face in the conductive via hole is less than the first threshold;

The distance in the second direction between the boundary line of the test section in the second conductive part and the boundary line corresponding to the lower end face in the conductive via hole is less than the second threshold.
The semiconductor test structure according to claim 2, wherein the first test part includes a plurality of first test structures arranged in parallel and spaced apart, and the plurality of first test structures are connected in series in sequence.
The semiconductor test structure according to claim 7, wherein a plurality of the first test structures are connected in series in a serpentine shape.
The semiconductor test structure according to claim 1, wherein the second test part includes: a second test structure equivalent to the first conductive part, and a second test solder connected to the second test structure. plate.
The semiconductor test structure of claim 9, wherein:

The first conductive part includes: a plurality of test sections extending linearly;

The second test structure includes: a first test line extending linearly;

Wherein, the length of the first test line is the same as the equivalent length of the first conductive part.
The semiconductor test structure according to claim 10, wherein the length of the first test line is the same as the sum of the lengths of a plurality of the test sections in the first conductive part;

Or, the difference between the length of the first test line and the sum of the lengths of multiple test sections in the first conductive part is less than or equal to the allowable deviation value.
The semiconductor test structure according to claim 9, wherein the second test part includes a plurality of second test structures arranged in parallel and spaced apart, and the plurality of second test structures are connected in series in sequence.
The semiconductor test structure according to claim 12, wherein a plurality of the second test structures are connected in series in a serpentine shape.
The semiconductor test structure according to any one of claims 9 to 13, wherein the second test structure and the first conductive part are formed in one process.
The semiconductor test structure according to claim 1, wherein the third test part includes: a third test structure equivalent to the second conductive part, and a third test solder connected to the third test structure. plate.
The semiconductor test structure of claim 15, wherein:

The second conductive part includes: a plurality of test sections extending linearly;

The third test structure includes: a second test line extending linearly;

Wherein, the length of the second test line is the same as the equivalent length of the second conductive part.
The semiconductor test structure according to claim 16, wherein the length of the second test line is the same as the sum of the lengths of a plurality of the test sections in the second conductive part;

Or, the difference between the length of the second test line and the sum of the lengths of multiple test sections in the second conductive part is less than or equal to the allowable deviation value.
The semiconductor test structure according to claim 15, wherein the third test part includes a plurality of third test structures arranged in parallel and spaced apart, and the plurality of third test structures are connected in series in sequence.
The semiconductor test structure according to any one of claims 15 to 18, wherein the third test structure and the second conductive part are formed in one process.
A semiconductor testing method, including:

Test the electrical performance of the first test structure to obtain the first test result; the first test structure includes: a conductive via hole, and a first conductive hole located at both ends of the conductive via hole and connected to the conductive via hole. part and the second conductive part;

Test the electrical performance of the second test structure to obtain a second test result; the second test structure is equivalent to the first conductive part;

Test the electrical performance of the third test structure to obtain a third detection result; the third test structure is equivalent to the second conductive part;

The electrical performance of the conductive via is determined according to the first detection result, the second detection result and the third detection result.