CN110416108B - Test structure of MIM capacitor and preparation method thereof - Google Patents
Test structure of MIM capacitor and preparation method thereof Download PDFInfo
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- CN110416108B CN110416108B CN201910698755.6A CN201910698755A CN110416108B CN 110416108 B CN110416108 B CN 110416108B CN 201910698755 A CN201910698755 A CN 201910698755A CN 110416108 B CN110416108 B CN 110416108B
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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Abstract
The invention discloses a test structure of an MIM capacitor and a preparation method thereof, wherein the preparation method comprises the following steps: presetting the position of the MIM capacitor to be tested; providing a semiconductor substrate and a preset test structure model; and forming the MIM capacitor to be tested and a test structure for testing the MIM capacitor to be tested in the gap region on the semiconductor substrate according to the preset test structure model and the position of the MIM capacitor to be tested. The invention is beneficial to improving the preparation efficiency of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a test structure of an MIM capacitor and a preparation method thereof.
Background
Capacitive elements are commonly used as electronic passive devices in integrated circuits such as radio frequency ICs, monolithic microwave ICs, etc. Common capacitor elements include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, and MIM (metal-insulator-metal) capacitors. The MIM capacitor provides electrical characteristics better than MOS capacitors and PN junction capacitors in some special applications, because the MOS capacitors and PN junction capacitors are limited by their structures, and the electrodes easily generate a hole layer during operation, which reduces the frequency characteristics. Whereas MIM capacitors may provide better frequency and temperature dependent characteristics. In addition, MIM capacitors may be formed in the interlayer metal and metal (copper) interconnect processes in semiconductor manufacturing, which also reduces the difficulty and complexity of integration with CMOS front-end processes.
Due to the randomness of the process for manufacturing the MIM capacitor, the manufactured MIM capacitor may have various defects, for example, in the manufacturing process of the MIM capacitor, the metal of the upper plate may not be completely etched due to the process problem, so that the upper plate has metal material residue, which causes a risk of short circuit with the via hole of the lower plate in the subsequent process.
In order to improve the reliability of a chip, the formed MIM capacitor needs to be detected before a chip is subjected to a packaging process, but the existing MIM capacitor has a complex test structure, and different WAT (wafer acceptance test) keys (test patterns or test structures) need to be designed for the MIM capacitors formed between different metal layers, after a semiconductor silicon wafer completes all process technologies, for various test structures on the silicon wafer), that is, the WAT tests a special test structure, and monitors whether each process is normal and stable through electrical parameters. If the metal layers have 6 layers, 5 different test structures of the MIM capacitors need to be designed, which is not universal, if an incorrect test structure of the MIM capacitor is selected during the preparation of the test structure, the prepared test structure fails, and different MIM capacitor test structures need to be designed for the MIM capacitors located in different metal layers, which leads to the extension of the design period, while the preparation of the MIM capacitor test structure is usually integrated with the preparation process of a semiconductor device, which leads to the extension of the preparation process period of the semiconductor device due to the extension of the design period, which is not beneficial to the improvement of the preparation efficiency of the semiconductor device; in addition, if an incorrect test structure is selected, the MIM capacitor cannot be detected, and actually, when the problem that the MIM capacitor cannot be detected is solved, an analysis process is required, which results in extra time for failure analysis, thereby prolonging the preparation period of the semiconductor device and being not beneficial to improving the preparation efficiency of the semiconductor device.
Disclosure of Invention
The invention aims to provide a test structure of an MIM capacitor and a preparation method thereof, which are used for solving the problems that the design cycle of the MIM capacitor test structure is prolonged, so that the preparation process cycle of a semiconductor device is prolonged, and the preparation efficiency of the semiconductor device is not improved.
In order to solve the above problems, the present invention is realized by the following technical scheme:
a method for preparing a test structure of an MIM capacitor comprises the following steps:
presetting the position of the MIM capacitor to be tested;
providing a semiconductor substrate and a preset test structure model;
and forming the MIM capacitor to be tested and a test structure for testing the MIM capacitor to be tested in the gap area on the semiconductor substrate according to the preset test structure model and the position of the MIM capacitor to be tested.
Further, the preset test structure model includes: a test pad group including a first test pad, a second test pad, a third test pad, and a fourth test pad arranged in a first direction;
a metal lead group including a first metal lead, a second metal lead, a third metal lead, and a fourth metal lead arranged in a first direction;
the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group;
and the plurality of preset test structure submodels are arranged along the second direction and are positioned below the metal lead group.
Further, the preset test structure submodel of each metal lead group comprises: the MIM capacitor group comprises a first MIM capacitor, a second MIM capacitor, a third MIM capacitor, two first lower plate metal layers and two second lower plate metal layers which are arranged in a column along a second direction;
the upper polar plate of the first MIM capacitor is led out through a conductive contact plug;
the lower pole plate of the first MIM capacitor penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug and then is led out;
the two first lower plate metal layers are respectively positioned on the same row with the lower plate of the first MIM capacitor, are respectively positioned on two sides of the lower plate of the first MIM capacitor and respectively correspond to the first metal lead and the fourth metal lead one by one; each first lower pole plate metal layer is led out through a conductive contact plug;
the upper plate of the second MIM capacitor is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower pole plate of the second MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the first lower pole plate metal layer corresponding to the first metal lead layer;
the second lower plate metal layer and the lower plate of the second MIM capacitor are positioned in the same row and correspond to the fourth metal lead; the second lower pole plate metal layer is connected with the first lower pole plate metal layer positioned above the second lower pole plate metal layer through a conductive contact plug;
the upper plate of the third MIM capacitor is connected with the lower plate of the second MIM capacitor through a conductive contact plug;
and the lower plate of the third MIM capacitor penetrates through the insulating layer of the third MIM capacitor through a conductive contact plug and is connected with the second lower plate metal layer.
Furthermore, an upper electrode plate of the first MIM capacitor in the preset test structure submodel close to the metal wire lead group is connected with the second metal lead through a conductive contact plug;
the lower pole plate of the first MIM capacitor penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug and then is connected with the third metal lead;
and the first lower pole plate metal layer corresponding to the first metal lead in the two first lower pole plate metal layers is connected with the first metal lead through a conductive contact plug, and the other first lower pole plate metal layer corresponding to the fourth metal lead is connected with the fourth metal lead through a conductive contact plug.
Further, the upper electrode plate of the first MIM capacitor in the lower preset test structure submodel of the two adjacent preset test structure submodels is connected to the lower electrode plate of the third MIM capacitor in the other preset test structure submodel through a conductive contact plug;
the lower pole plate of the first MIM capacitor in the lower preset test structure submodel penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug and is connected with the lower pole plate of a third MIM capacitor in the other preset test structure submodel;
and the first lower plate metal layer corresponding to the first metal lead in the two first lower plate metal layers in the lower preset test structure submodel is connected with the lower plate of the second MIM capacitor in the other preset test structure submodel through a conductive contact plug, and the other first lower plate metal layer corresponding to the fourth metal lead is connected with the lower plate of the third MIM capacitor in the other preset test structure submodel through a conductive contact plug.
Preferably, when the to-be-tested MIM capacitor is a first MIM capacitor in the preset test structure sub-model close to the metal wire lead group in the preset test structure model,
the preset test structure model comprises: the first MIM capacitor is configured to have a first MIM capacitance,
the second metal lead is connected with the upper plate of the first MIM capacitor through a conductive contact plug; the third metal lead connected to the lower plate of the first MIM capacitor through a conductive contact plug through an insulating layer of the first MIM capacitor;
and the second test pad and the third test pad connected to the second metal lead and the third metal lead, respectively; the second test pad and the third test pad are connected with a test voltage.
Preferably, when the MIM capacitor to be tested is a second MIM capacitor in the preset test structure submodel close to the metal wire lead group in the preset test structure model,
the preset test structure model comprises: the second MIM capacitor is provided with a first MIM capacitor,
the first test pad, the second test pad, and the third test pad in the set of test pads; the first metal lead, the second metal lead, and the third metal lead in the metal lead group; each metal lead in the metal lead group is connected with each test pad in the test pad group in a one-to-one correspondence manner; the first bottom plate metal layer is opposite to and connected with the first metal lead; and a lower plate of the first MIM capacitor;
the lower pole plate of the second MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the first lower pole plate metal layer;
the upper plate of the second MIM capacitor is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead through conductive contact plugs;
the first test pad and the second test pad are connected with a test voltage at the same time, or the first test pad and the third test pad are connected with the test voltage at the same time.
Preferably, when the MIM capacitor to be tested is a third MIM capacitor in the preset test structure submodel close to the metal wire lead group in the preset test structure model,
the preset test structure model comprises: the third MIM capacitor, the test pad set, the metal lead set, the first bottom plate metal layer opposite to and connected with the first metal lead, the other first bottom plate metal layer opposite to and connected with the fourth metal lead, and the bottom plate of the first MIM capacitor;
a lower plate of the second MIM capacitor and the second lower plate metal layer;
the upper plate of the third MIM capacitor is connected with the lower plate of the second MIM capacitor through a conductive contact plug;
the lower plate of the second MIM capacitor is connected with the first lower plate metal layer opposite to the first metal lead in the metal lead group through a conductive contact plug, and is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead in the metal lead group through conductive contact plugs;
the lower pole plate of the third MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the second lower pole plate metal layer;
the second lower pole plate metal layer is connected with the other first lower pole plate metal layer below a fourth metal lead in the metal lead group;
the first test pad and the fourth test pad in the test pad group are simultaneously connected with a test voltage, or the second test pad and the fourth test pad are simultaneously connected with the test voltage, or the third test pad and the fourth test pad are simultaneously connected with the test voltage.
In another aspect, the present invention provides a test structure of an MIM capacitor, which is prepared by the above method for preparing a test structure of an MIM capacitor; the test structure includes: the first MIM capacitor, the second metal lead connected with the upper plate of the first MIM capacitor through a conductive contact plug; the third metal lead connected to the lower plate of the first MIM capacitor through a conductive contact plug through an insulating layer of the first MIM capacitor; and the second test pad and the third test pad connected to the second metal lead and the third metal lead, respectively; the second test pad and the third test pad are connected with a test voltage.
In another aspect, the present invention provides a test structure of an MIM capacitor, which is prepared by the above method for preparing a test structure of an MIM capacitor; the test structure includes: the second MIM capacitor, the first test pad, the second test pad, and the third test pad of the set of test pads; the first metal lead, the second metal lead, and the third metal lead in the metal lead group; each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group; the first bottom plate metal layer is opposite to and connected with the first metal lead; and a lower plate of the first MIM capacitor;
the lower pole plate of the second MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the first lower pole plate metal layer;
the upper plate of the second MIM capacitor is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead through conductive contact plugs;
the first test pad and the second test pad are connected with a test voltage at the same time, or the first test pad and the third test pad are connected with the test voltage at the same time.
In other aspects, the present invention provides a test structure for MIM capacitors, using a MIM as described above
Preparing a preparation method of a capacitor test structure; the test structure includes: the third MIM capacitor
A capacitor, a test pad group, a metal lead group, two first bottom plate metal layers, and a first MIM
A lower plate of a capacitor, a lower plate of the second MIM capacitor, and the second lower plate metal layer;
the test pad group comprises a first test pad, a second test pad, a third test pad and a fourth test pad which are arranged along a first direction;
the metal lead group comprises a first metal lead, a second metal lead, a third metal lead and a fourth metal lead which are arranged along a first direction;
the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group;
one of the two first lower plate metal layers is opposite to and connected with the first metal lead, and the other one of the two first lower plate metal layers is opposite to and connected with the fourth metal lead;
the upper plate of the third MIM capacitor is connected with the lower plate of the second MIM capacitor through a conductive contact plug;
the lower plate of the second MIM capacitor is connected to the first lower plate metal layer opposite the first metal lead by a conductive contact plug and to the lower plate of the first MIM capacitor by a conductive contact plug;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead through conductive contact plugs;
the lower pole plate of the third MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the second lower pole plate metal layer;
the second lower pole plate metal layer is connected with the other first lower pole plate metal layer corresponding to the fourth metal lead;
the first test pad and the fourth test pad in the test pad group are simultaneously connected with a test voltage, or the second test pad and the fourth test pad are simultaneously connected with the test voltage, or the third test pad and the fourth test pad are simultaneously connected with the test voltage.
Compared with the prior art, the invention has the following advantages:
the position of the MIM capacitor to be tested is preset; providing a semiconductor substrate and a preset test structure model; and forming the MIM capacitor and a test structure for testing the MIM capacitor in a gap area on the semiconductor substrate according to the preset test structure model and the position of the MIM capacitor to be tested. The invention provides the test structure model of the MIM capacitor in advance, which has universality, namely, no matter which interlayer metal of the semiconductor device to be prepared or which interconnection structure layer of the metal (copper) interconnection structure the MIM capacitor is positioned in, the preset test structure model can be adopted to prepare the test structure matched with the MIM capacitor, so that the test structure of the MIM capacitor does not need to be designed respectively when being prepared, the design cycle of the MIM capacitor test structure is shortened, the artificial error rate is reduced, the preparation process cycle of the semiconductor device is shortened, and the preparation efficiency of the semiconductor device is improved.
Drawings
Fig. 1 is a schematic structural diagram of a preset test structure model when three MIM capacitors exist in a method for manufacturing a test structure of an MIM capacitor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a preset test structure model when a capacitor to be tested is a first MIM capacitor in a method for manufacturing a test structure of an MIM capacitor according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a preset test structure model when a capacitor to be tested is a second MIM capacitor in a method for manufacturing a test structure of an MIM capacitor according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a preset test structure model of a test structure of an MIM capacitor according to yet another embodiment of the present invention, when a capacitor to be tested is a third MIM capacitor;
fig. 5 is a schematic flowchart of a method for manufacturing a test structure of an MIM capacitor according to an embodiment of the present invention.
Detailed Description
The present invention will now be described in more detail with reference to the accompanying drawings, in which a preferred embodiment of the invention is shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous results of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and employ non-precise ratios for the purpose of facilitating and distinctly facilitating the description of one embodiment of the present invention.
With reference to fig. 1 to fig. 5, a method for manufacturing a test structure of an MIM capacitor according to this embodiment includes:
step S1, presetting the position of the MIM capacitor to be tested;
step S2, providing a semiconductor substrate and a preset test structure model;
and step S3, forming the MIM capacitor to be tested and a test structure for testing the MIM capacitor to be tested in the gap area on the semiconductor substrate according to the preset test structure model and the position of the MIM capacitor to be tested.
In this embodiment, a plurality of functional regions and a plurality of void regions (scribe lane regions or scribe lane regions) are formed on the semiconductor substrate, and each of the void regions is located between the functional regions. The functional region is used for manufacturing a functional device (such as an MOS tube), and the gap region is used for arranging a detection piece. Each void region is provided with a detection structure of the MIM capacitor as described below at a position corresponding to the position where the MIM capacitor is provided. The semiconductor substrate may be a front-end device structure formed with a semiconductor device; on this basis, a metal (copper) interconnection structure is formed, and it should be understood that the metal interconnection structure may include several metal interconnection structure layers, and the MIM capacitor or the MIM capacitor to be tested may be formed between any two adjacent metal interconnection structure layers in the metal interconnection structure.
With continued reference to fig. 1, the preset test structure model includes: a test pad group including a first test pad P1, a second test pad P2, a third test pad P3, and a fourth test pad P4 arranged in a first direction; the first direction is a planar direction parallel to the semiconductor substrate, i.e., a lateral direction.
A metal lead group including a first metal lead T10, a second metal lead T11, a third metal lead T12, and a fourth metal lead T13 arranged in a first direction;
the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group;
and a plurality of preset test structure submodels (not numbered in the figure) arranged along the second direction and positioned below the metal lead group. The second direction is a longitudinal direction, i.e., a direction perpendicular to the surface of the semiconductor substrate.
Each of the preset test structure submodels includes: a MIM capacitor bank including a first MIM capacitor (not numbered), a second MIM capacitor (not numbered), and a third MIM capacitor (not numbered) arranged in a column along a second direction; in this embodiment, the MIM capacitor, i.e., the conventional capacitor structure, includes an upper plate, a lower plate, and an insulating layer located between the upper plate and the lower plate, where the upper plate may be made of metal or alloy, and specifically may be TIN, the insulating layer may be made of SIN, and the lower plate may be made of copper.
The upper plate M1 of the first MIM capacitor is led out through a conductive contact plug;
the lower plate T22 of the first MIM capacitor penetrates through the insulating layer I1 of the first MIM capacitor through a conductive contact plug and then is led out;
two first bottom plate metal layers T21 and T23, which are located in the same row as the bottom plate T22 of the first MIM capacitor, are located on two sides of the bottom plate T22 of the first MIM capacitor, and are in one-to-one correspondence with the first metal lead T10 and the fourth metal lead T13; each first lower pole plate metal layer is led out through a conductive contact plug;
the upper plate M2 of the second MIM capacitor is connected to the lower plate T22 of the first MIM capacitor by a conductive contact plug;
the lower plate T31 of the second MIM capacitor is connected with the first lower plate metal layer T21 corresponding to the first metal lead layer T10 through a conductive contact plug penetrating through the insulating layer I2 of the second MIM capacitor;
a second bottom plate metal layer T32, which is located in the same row as the bottom plate T31 of the second MIM capacitor and corresponds to the fourth metal lead T13; the second lower plate metal layer T32 is connected to the first lower plate metal layer T23 located above it through a conductive contact plug;
the upper plate M3 of the third MIM capacitor is connected to the lower plate T31 of the second MIM capacitor by a conductive contact plug;
the lower plate T41 of the third MIM capacitor is connected to the second lower plate metal layer T32 through an insulating layer I3 of the third MIM capacitor by a conductive contact plug.
With continued reference to fig. 1, the upper plate M1 of the first MIM capacitor in the predetermined test structure submodel adjacent to the set of metal line leads is connected to the second metal lead T11 by a conductive contact plug V;
the lower plate T22 of the first MIM capacitor penetrates through the insulating layer I1 of the first MIM capacitor through a conductive contact plug V and then is connected with the third metal lead T12;
the first bottom plate metal layer T21 corresponding to the first metal lead T10 of the two first bottom plate metal layers is connected to the first metal lead T10 by a conductive contact plug V, and the other first bottom plate metal layer T23 corresponding to the fourth metal lead T13 is connected to the fourth metal lead T13 by a conductive contact plug V.
Further, the upper plate of the first MIM capacitor in the lower preset test structure submodel of the two adjacent preset test structure submodels is connected to the lower plate of the third MIM capacitor in the other preset test structure submodel through a conductive contact plug V;
the lower pole plate of the first MIM capacitor in the lower preset test structure submodel penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug V and is connected with the lower pole plate of a third MIM capacitor in the other preset test structure submodel;
and the first lower plate metal layer corresponding to the first metal lead in the two first lower plate metal layers in the lower preset test structure submodel is connected with the lower plate of the second MIM capacitor in the other preset test structure submodel through a conductive contact plug V, and the other first lower plate metal layer corresponding to the fourth metal lead is connected with the lower plate of the third MIM capacitor in the other preset test structure submodel through a conductive contact plug V. Therefore, the preset test structure model provided by the embodiment can longitudinally extend to a plurality of layers, and has universality.
With reference to fig. 2, preferably, when the to-be-tested MIM capacitor is a first MIM capacitor in the preset test structure submodel close to the metal line lead group in the preset test structure model, the preset test structure model includes: the first MIM capacitor, the second metal lead T11 connected with the upper plate M1 of the first MIM capacitor through a conductive contact plug V; the third metal lead T12 connected to the lower plate T22 of the first MIM capacitor through the insulating layer I1 of the first MIM capacitor by a conductive contact plug V;
and the second and third test pads P2 and P3 connected to the second and third metal leads T11 and T12, respectively; the second test pad P2 and the third test pad P3 are connected to a test voltage.
Specifically, according to the preset test structure model, a first metal interconnection structure layer is formed on the global surface of the semiconductor substrate, the first metal interconnection structure layer is subjected to photolithography and etching processes by using an MCT mask as a mask, the first metal interconnection structure layer is patterned to form a required first metal interconnection structure and a bottom plate T22 of the first MIM capacitor in the void region, an insulating thin film layer is formed on the global surface of the semiconductor substrate, and the insulating thin film layer is patterned by using photolithography and etching processes to form an insulating layer I1 of the first MIM capacitor; forming a metal film on the global surface of the semiconductor substrate, patterning the metal film by using photolithography and etching processes to form an upper electrode plate M1 of the first MIM capacitor, then forming a metal lead film on a void region of the semiconductor substrate, patterning the metal lead film by using photolithography and etching processes to form the second metal lead T11 and the third metal lead T12, and then forming the second test pad P2 and the third test pad P3 on the second metal lead T11 and the third metal lead T12, respectively. Therefore, the manufacturing process of the test structure in the embodiment can be combined with the manufacturing process of the metal interconnection structure in the semiconductor device, so that the production efficiency is improved.
Preferably, when the to-be-tested MIM capacitor is a second MIM capacitor in the preset test structure submodel close to the metal wire lead group in the preset test structure model, please refer to fig. 3 continuously, where the preset test structure model includes: the second MIM capacitor, the first test pad P1, the second test pad P2, and the third test pad P3 of the set of test pads; the first metal lead T10, the second metal lead T11 and the third metal lead T12 in the metal lead group; each metal lead in the metal lead group is connected with each test pad in the test pad group in a one-to-one correspondence manner; the first lower plate metal layer T21 opposite to and connected to the first metal lead T11; and a lower plate T22 of the first MIM capacitor;
the lower plate T31 of the second MIM capacitor is connected with the first lower plate metal layer T21 through the insulating layer I2 of the second MIM capacitor by a conductive contact plug V;
the upper plate M2 of the second MIM capacitor is connected to the lower plate T22 of the first MIM capacitor by a conductive contact plug V;
the lower plate T22 of the first MIM capacitor is connected with the second metal lead T11 and the third metal lead T12 through conductive contact plugs;
the first test pad P1 and the second test pad P2 are simultaneously connected to a test voltage, or the first test pad P1 and the third test pad P3 are simultaneously connected to the test voltage.
The first bottom plate metal layer T21 and the bottom plate T22 of the first MIM capacitor may be formed in the same process, that is, a first metal interconnect structure layer is formed on the global surface of the semiconductor substrate, and the first metal interconnect structure layer is subjected to photolithography and etching processes to pattern the first metal interconnect structure layer, so as to form the first bottom plate metal layer T21 and the bottom plate T22 of the first MIM capacitor.
The other preparation processes are the same as the preparation process of the first MIM capacitor as described above, and are not described herein again.
Preferably, when the MIM capacitor to be tested is a third MIM capacitor in the preset test structure submodel close to the metal wire lead group in the preset test structure model,
referring to fig. 4, the preset test structure model includes: the third MIM capacitor, a set of test pads comprising a first test pad P1, a second test pad P2, a third test pad P3, and a fourth test pad P4 arranged in a first direction; the first direction is a planar direction parallel to the semiconductor substrate, i.e., a lateral direction. A metal lead group including a first metal lead T10, a second metal lead T11, a third metal lead T12, and a fourth metal lead T13 arranged in a first direction; the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group;
the first lower plate metal layer T21 opposite to and connected to the first metal lead T10, and the other first lower plate metal layer T23 opposite to and connected to the fourth metal lead T13; and the lower plate T22 of the first MIM capacitor;
a bottom plate T31 of the second MIM capacitor and the second bottom plate metal layer T32;
the upper plate M3 of the third MIM capacitor is connected to the lower plate T31 of the second MIM capacitor by a conductive contact plug V;
the lower plate T31 of the second MIM capacitor is connected to the first lower plate metal layer T21 opposite the first metal lead T10 of the metal lead group by a conductive contact plug V and to the lower plate T22 of the first MIM capacitor by a conductive contact plug V;
the lower plate T22 of the first MIM capacitor is respectively connected with the second metal lead T11 and the third metal lead T12 in the metal lead group through a conductive contact plug V;
the lower plate T41 of the third MIM capacitor is connected with the second lower plate metal layer T32 through the insulating layer I2 of the second MIM capacitor by a conductive contact plug V;
the second lower plate metal layer T32 is connected with another first lower plate metal layer T23 under a fourth metal lead T13 in the metal lead group;
the first test pad P1 and the fourth test pad P4 in the test pad group are simultaneously connected with a test voltage, or the second test pad P2 and the fourth test pad P4 are simultaneously connected with the test voltage, or the third test pad P3 and the fourth test pad P4 are simultaneously connected with the test voltage.
In this example, the test structure was prepared as follows: according to the preset test structure model, a third metal interconnection structure layer is firstly formed on the global surface of the semiconductor substrate, photoetching and etching processes are carried out on the third metal interconnection structure layer by adopting an MCT photomask as a mask, the third metal interconnection structure layer is patterned to form a required third metal interconnection structure and a lower plate T41 of the third MIM capacitor in the gap area, an insulating film layer is formed on the global surface of the semiconductor substrate, and the insulating film layer is patterned by adopting photoetching and etching processes to form an insulating layer I3 of the third MIM capacitor; forming a metal film on the global surface of the semiconductor substrate, patterning the metal film by using a photolithography and etching process to form an upper plate M3 of the third MIM capacitor, forming a second metal interconnection structure layer on the global surface of the semiconductor substrate (before forming the second metal interconnection structure layer, forming an insulating layer on the global surface of the semiconductor substrate), performing a photolithography and etching process on the second metal interconnection structure layer, that is, patterning the second metal interconnection structure layer, and forming the second lower plate metal layer T32 and the lower plate T31 of the second MIM capacitor; then, a metal lead film is formed on the void region of the semiconductor substrate, the metal lead film is patterned by adopting photolithography and etching processes to form the first metal lead T10, the second metal lead T11, the third metal lead T12 and the fourth metal lead T13, and then a first test pad P1, a second test pad P2, a third test pad P3 and a fourth test pad P4 are respectively formed on the first metal lead T10, the second metal lead T11, the third metal lead T12 and the fourth metal lead T13. Therefore, the manufacturing process of the test structure in the embodiment can be combined with the manufacturing process of the metal interconnection structure in the semiconductor device, so that the production efficiency is improved.
On the other hand, the invention also discloses a test structure of the MIM capacitor, which is prepared by the preparation method of the test structure of the MIM capacitor; the test structure includes: a first MIM capacitor, the second metal lead T11 connected to the upper plate M1 of the first MIM capacitor through a conductive contact plug V; the third metal lead T12 connected to the lower plate T22 of the first MIM capacitor through the insulating layer I1 of the first MIM capacitor by a conductive contact plug V; and the second and third test pads P2 and P3 connected to the second and third metal leads T11 and T12, respectively; the second test pad P2 and the third test pad P3 are connected to a test voltage.
As can be seen from the foregoing, the metal interconnect structure may include several metal interconnect structure layers, and the MIM capacitor or the MIM capacitor to be tested may be formed between any two adjacent metal interconnect structure layers in the metal interconnect structure. The plurality of metal interconnection structure layers are named as a first metal interconnection structure layer to an Nth metal interconnection structure layer from top to bottom in sequence, the first MIM capacitor is the MIM capacitor formed on the first metal interconnection structure layer, one part of the first metal interconnection structure layer can be used as the lower plate of the first MIM capacitor, and the like, the second MIM capacitor is the MIM capacitor formed on the second metal interconnection structure layer, and the third MIM capacitor is the MIM capacitor formed on the third metal interconnection structure layer.
In another aspect, the present invention discloses a test structure of an MIM capacitor, which is prepared by the above method for preparing a test structure of an MIM capacitor; the test structure includes: a second MIM capacitor, the first test pad P1, the second test pad P2, and the third test pad P3 of the set of test pads; the first metal lead T10, the second metal lead T11 and the third metal lead T12 in the metal lead group; each metal lead in the metal lead group is connected with each test pad in the test pad group in a one-to-one correspondence manner; the first lower plate metal layer T21 opposite to and connected to the first metal lead T11; and the bottom plate T22 of the first MIM capacitor;
the lower plate T31 of the second MIM capacitor is connected with the first lower plate metal layer T21 through the insulating layer I2 of the second MIM capacitor by a conductive contact plug V;
the upper plate M2 of the second MIM capacitor is connected to the lower plate T22 of the first MIM capacitor via a conductive contact plug V;
the lower plate T22 of the first MIM capacitor is connected with the second metal lead T11 and the third metal lead T12 through conductive contact plugs;
the first test pad P1 and the second test pad P2 are simultaneously connected to a test voltage, or the first test pad P1 and the third test pad P3 are simultaneously connected to the test voltage.
In other aspects, the invention also discloses a test structure of the MIM capacitor, which is prepared by the preparation method of the test structure of the MIM capacitor; the test structure includes: a third MIM capacitor, a set of test pads including a first test pad P1, a second test pad P2, a third test pad P3, and a fourth test pad P4 arranged in a first direction; the first direction is a planar direction parallel to the semiconductor substrate, i.e., a lateral direction. A metal lead group including a first metal lead T10, a second metal lead T11, a third metal lead T12, and a fourth metal lead T13 arranged in a first direction; the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group;
the first lower plate metal layer T21 opposite to and connected to the first metal lead T10, and the other first lower plate metal layer T23 opposite to and connected to the fourth metal lead T13; and the lower plate T22 of the first MIM capacitor;
the lower plate T31 of the second MIM capacitor and the second lower plate metal layer T32;
the upper plate M3 of the third MIM capacitor is connected to the lower plate T31 of the second MIM capacitor by a conductive contact plug V;
the lower plate T31 of the second MIM capacitor is connected to the first lower plate metal layer T21 opposite the first metal lead T10 of the metal lead group by a conductive contact plug V and to the lower plate T22 of the first MIM capacitor by a conductive contact plug V;
the lower plate T22 of the first MIM capacitor is respectively connected with the second metal lead T11 and the third metal lead T12 in the metal lead group through a conductive contact plug V;
the lower plate T41 of the third MIM capacitor is connected with the second lower plate metal layer T32 through the insulating layer I2 of the second MIM capacitor by a conductive contact plug V;
the second lower plate metal layer T32 is connected with another first lower plate metal layer T23 under a fourth metal lead T13 in the metal lead group;
the first test pad P1 and the fourth test pad P4 in the test pad group are simultaneously connected with a test voltage, or the second test pad P2 and the fourth test pad P4 are simultaneously connected with the test voltage, or the third test pad P3 and the fourth test pad P4 are simultaneously connected with the test voltage.
In summary, the present invention presets the position of the MIM capacitor to be tested; providing a semiconductor substrate and a preset test structure model; and forming the MIM capacitor and a test structure for testing the MIM capacitor in a gap area on the semiconductor substrate according to the preset test structure model and the position of the MIM capacitor to be tested. The invention provides a test structure model of the MIM capacitor in advance, which has universality, namely, no matter which interlayer metal of the semiconductor device to be prepared or which interconnection structure layer of the metal (copper) interconnection structure the MIM capacitor is positioned in, the preset test structure model can be adopted to prepare a test structure matched with the MIM capacitor, so that when the test structure of the MIM capacitor is prepared, the test structure of the MIM capacitor does not need to be designed respectively, the design cycle of the MIM capacitor test structure is shortened, the artificial error rate is reduced, the preparation process cycle of the semiconductor device is further shortened, and the preparation efficiency of the semiconductor device is favorably improved.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers (e.g., "between … …" and "directly between … …", "adjacent to … …" and "directly adjacent to … …", "on … …" and "directly on … …", etc.) should be interpreted in the same manner.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
Spatially relative terms, such as "below … …," "above … …," "below," "above … …," "above," "upper" and "lower" may be used herein for ease of description to describe the spatial relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention are described herein with reference to schematic cross-sectional views of preferred embodiments (and intermediate structures) as exemplary embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features at its edges and/or a gradient change in implant concentration, rather than just a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation also in the region between the buried region and the surface through which the implantation passes. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of the regions in a device and are not intended to limit the scope of exemplary embodiments in accordance with the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. A preparation method of a test structure of an MIM capacitor is characterized by comprising the following steps:
presetting the position of the MIM capacitor to be tested;
providing a semiconductor substrate and a preset test structure model, wherein the preset test structure model comprises: the test pad group is provided with at least two test pads arranged along a first direction; a metal lead group including at least two metal leads arranged in a first direction; the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group; the preset test structure submodel comprises an MIM capacitor group with a plurality of MIN capacitors and a plurality of lower plate metal layers, and the MIM capacitor group is electrically led out by utilizing the lower plate metal layers, the metal lead groups and the test pad groups;
according to the preset test structure model and the position of the MIM capacitor to be tested, the void region on the semiconductor substrate forms the MIM capacitor to be tested and a test structure used for testing the MIM capacitor to be tested, and the test structure takes the MIM capacitor to be tested as the preset test structure model of the MIM capacitor.
2. The method of claim 1, wherein the pre-testing model comprises: the test pad group comprises a first test pad, a second test pad, a third test pad and a fourth test pad which are arranged along a first direction;
a metal lead group including a first metal lead, a second metal lead, a third metal lead, and a fourth metal lead arranged in a first direction;
the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group; and
and the plurality of preset test structure submodels are arranged along the second direction and are positioned below the metal lead group.
3. The method of fabricating the test structure of the MIM capacitor of claim 2, wherein the test structure of the MIM capacitor is formed by a process of forming a test pattern on a substrate,
the preset test structure submodel of each metal lead group comprises: the MIM capacitor group comprises a first MIM capacitor, a second MIM capacitor, a third MIM capacitor, two first lower plate metal layers and a second lower plate metal layer which are arranged in a column along a second direction;
the upper polar plate of the first MIM capacitor is led out through a conductive contact plug;
the lower pole plate of the first MIM capacitor penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug and then is led out;
the two first lower plate metal layers and the lower plate of the first MIM capacitor are positioned in the same row, positioned on two sides of the lower plate of the first MIM capacitor respectively and corresponding to the first metal lead and the fourth metal lead one by one respectively; each first lower electrode plate metal layer is led out through a conductive contact plug;
the upper plate of the second MIM capacitor is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower pole plate of the second MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the first lower pole plate metal layer corresponding to the first metal lead layer;
the second lower plate metal layer and the lower plate of the second MIM capacitor are positioned in the same row and correspond to the fourth metal lead; the second lower pole plate metal layer is connected with the first lower pole plate metal layer positioned above the second lower pole plate metal layer through a conductive contact plug;
the upper plate of the third MIM capacitor is connected with the lower plate of the second MIM capacitor through a conductive contact plug;
the lower plate of the third MIM capacitor is connected to the second lower plate metal layer by a conductive contact plug that penetrates through the insulating layer of the third MIM capacitor.
4. The method of claim 3, wherein the top plate of the first MIM capacitor in the predetermined test structure submodel proximate to the set of metal leads is connected to the second metal lead by a conductive contact plug;
the lower pole plate of the first MIM capacitor penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug and then is connected with the third metal lead;
and the first lower pole plate metal layer corresponding to the first metal lead in the two first lower pole plate metal layers is connected with the first metal lead through a conductive contact plug, and the other first lower pole plate metal layer corresponding to the fourth metal lead is connected with the fourth metal lead through a conductive contact plug.
5. The method of claim 4, wherein the upper plate of the first MIM capacitor of the lower one of the two neighboring pre-test structure submodels is connected to the lower plate of the third MIM capacitor of the other pre-test structure submodel via a conductive contact plug;
the lower pole plate of the first MIM capacitor in the lower preset test structure submodel penetrates through the insulating layer of the first MIM capacitor through a conductive contact plug and is connected with the lower pole plate of a third MIM capacitor in the other preset test structure submodel;
and the first lower plate metal layer corresponding to the first metal lead in the two first lower plate metal layers in the lower preset test structure submodel is connected with the lower plate of the second MIM capacitor in the other preset test structure submodel through a conductive contact plug, and the other first lower plate metal layer corresponding to the fourth metal lead is connected with the lower plate of the third MIM capacitor in the other preset test structure submodel through a conductive contact plug.
6. The method of fabricating the test structure of the MIM capacitor of claim 5, wherein the test structure of the MIM capacitor is formed by a process of forming a test pattern on a substrate,
when the MIM capacitor to be tested is the first MIM capacitor in the preset test structure submodel close to the metal lead group in the preset test structure model,
the preset test structure model comprises: the first MIM capacitor is configured to have a first MIM capacitance,
the second metal lead is connected with the upper plate of the first MIM capacitor through a conductive contact plug; the third metal lead connected to the lower plate of the first MIM capacitor through a conductive contact plug through an insulating layer of the first MIM capacitor;
and the second test pad and the third test pad connected to the second metal lead and the third metal lead, respectively; the second test pad and the third test pad are connected with a test voltage.
7. The method of fabricating the test structure of the MIM capacitor of claim 5, wherein the test structure of the MIM capacitor is formed by a process of forming a test pattern on a substrate,
when the MIM capacitor to be tested is a second MIM capacitor in the preset test structure submodel close to the metal lead group in the preset test structure model,
the preset test structure model comprises: the second MIM capacitor is provided with a first MIM capacitor,
the first test pad, the second test pad, and the third test pad in the set of test pads; the first metal lead, the second metal lead, and the third metal lead in the metal lead group; each metal lead in the metal lead group is connected with each test pad in the test pad group in a one-to-one correspondence manner; the first bottom plate metal layer is opposite to and connected with the first metal lead; and a lower plate of the first MIM capacitor;
the lower pole plate of the second MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the first lower pole plate metal layer;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead through conductive contact plugs;
the first test pad and the second test pad are connected with a test voltage at the same time, or the first test pad and the third test pad are connected with the test voltage at the same time.
8. The method of fabricating the test structure of the MIM capacitor of claim 5, wherein the test structure of the MIM capacitor is formed by a process of forming a test pattern on a substrate,
when the MIM capacitor to be tested is a third MIM capacitor in the preset test structure submodel close to the metal lead group in the preset test structure model,
the preset test structure model comprises: the third MIM capacitor, the test pad set, the metal lead set, the first bottom plate metal layer opposite to and connected with the first metal lead, the other first bottom plate metal layer opposite to and connected with the fourth metal lead, and the bottom plate of the first MIM capacitor;
a lower plate of the second MIM capacitor and the second lower plate metal layer;
the lower plate of the second MIM capacitor is connected with the first lower plate metal layer opposite to the first metal lead in the metal lead group through a conductive contact plug, and is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead in the metal lead group through conductive contact plugs;
the lower pole plate of the third MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the second lower pole plate metal layer;
the second lower pole plate metal layer is connected with the other first lower pole plate metal layer below a fourth metal lead in the metal lead group;
the first test pad and the fourth test pad in the test pad group are simultaneously connected with a test voltage, or the second test pad and the fourth test pad are simultaneously connected with the test voltage, or the third test pad and the fourth test pad are simultaneously connected with the test voltage.
9. A test structure of an MIM capacitor, characterized by being prepared by the method for preparing a test structure of an MIM capacitor according to claim 6; the test structure includes: the first MIM capacitor, the second metal lead connected with the upper plate of the first MIM capacitor through a conductive contact plug; the third metal lead connected to the lower plate of the first MIM capacitor through a conductive contact plug through an insulating layer of the first MIM capacitor; and the second test pad and the third test pad connected to the second metal lead and the third metal lead, respectively; the second test pad and the third test pad are connected with a test voltage.
10. A test structure of an MIM capacitor manufactured by the method of manufacturing a test structure of an MIM capacitor according to claim 7; the test structure includes: the second MIM capacitor, the first test pad, the second test pad, and the third test pad of the set of test pads; the first metal lead, the second metal lead, and the third metal lead in the metal lead group; each metal lead in the metal lead group is connected with each test pad in the test pad group in a one-to-one correspondence manner; the first bottom plate metal layer is opposite to and connected with the first metal lead; and a lower plate of the first MIM capacitor; the lower pole plate of the second MIM capacitor penetrates through the insulating layer of the second MIM capacitor through a conductive contact plug and is connected with the first lower pole plate metal layer;
the upper plate of the second MIM capacitor is connected with the lower plate of the first MIM capacitor through a conductive contact plug;
the lower plate of the first MIM capacitor is respectively connected with the second metal lead and the third metal lead through conductive contact plugs;
the first test pad and the second test pad are connected with a test voltage at the same time, or the first test pad and the third test pad are connected with the test voltage at the same time.
11. A test structure of an MIM capacitor manufactured by the method of manufacturing a test structure of an MIM capacitor according to claim 8; the test structure includes: the third MIM capacitor, the test pad group, the metal lead group, the two first bottom plate metal layers, the bottom plate of the first MIM capacitor, the bottom plate of the second MIM capacitor and the second bottom plate metal layer;
the test pad group comprises a first test pad, a second test pad, a third test pad and a fourth test pad which are arranged along a first direction;
the metal lead group comprises a first metal lead, a second metal lead, a third metal lead and a fourth metal lead which are arranged along a first direction;
the metal lead group is positioned below the test pad group, and each metal lead in the metal lead group is in one-to-one correspondence with and connected with each test pad in the test pad group;
one of the two first lower plate metal layers is opposite to and connected with the first metal lead, and the other one of the two first lower plate metal layers is opposite to and connected with the fourth metal lead;
the lower plate of the second MIM capacitor is connected to the first lower plate metal layer opposite the first metal lead by a conductive contact plug and to the lower plate of the first MIM capacitor by a conductive contact plug;
the second lower pole plate metal layer is connected with the other first lower pole plate metal layer corresponding to the fourth metal lead;
the first test pad and the fourth test pad in the test pad group are simultaneously connected with a test voltage, or the second test pad and the fourth test pad are simultaneously connected with the test voltage, or the third test pad and the fourth test pad are simultaneously connected with the test voltage.
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